code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 13;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd13;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 13;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd13;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_3_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_3_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [59 ... | 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_... | 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 60;
parameter AWIDTH = 8;
parameter MEM_SIZE = 240;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZ... | 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd60;
parameter AddressRange = 32'd240;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 13;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd13;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_4_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_4_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_cud_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_cud (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_... | 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_dEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 10;
parameter MEM_SIZE = 600;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZ... | 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_dEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd600;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 9;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd9;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_5_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_5_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_6_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_6_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_7_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_7_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;... | 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth ... | 6.840686 |
module StreamingFCLayer_Batch_8_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_8_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_9_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_9_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module streamlined_divider_4bit (
clk,
rst_n,
start_sig,
dividend,
divisor,
dong_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [3:0] dividend;
input [3:0] divisor;
output dong_sig;
output [3:0] quotient;
output [3:0] reminder;
/**********... | 6.71682 |
module streamlined_divider_4bit_improve (
clk,
rst_n,
start_sig,
dividend,
divisor,
dong_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [3:0] dividend;
input [3:0] divisor;
output dong_sig;
output [3:0] quotient;
output [3:0] reminder;
/**... | 6.71682 |
module streamlined_divider_4bit_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [3:0] dividend;
reg [3:0] divisor;
wire dong_sig;
wire [3:0] quotient;
wire [3:0] reminder;
streamlined_divider_4bit u1 (
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.dividend(dividend),
.... | 6.71682 |
module streamlined_divider_8bit_improve (
clk,
rst_n,
start_sig,
dividend,
divisor,
dong_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [7:0] dividend;
input [7:0] divisor;
output dong_sig;
output [7:0] quotient;
output [7:0] reminder;
/**... | 6.71682 |
module streamlined_divider_8bit_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [7:0] dividend;
reg [7:0] divisor;
wire dong_sig;
wire [7:0] quotient;
wire [7:0] reminder;
streamlined_divider_8bit_improve u1 (
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.dividend(dividend),... | 6.71682 |
module streamlined_divider_demo (
input CLK,
input RSTn,
input Start_Sig,
input [7:0] Dividend,
input [7:0] Divisor,
output Done_Sig,
output [7:0] Quotient,
output [7:0] Reminder
/**************************/
// output [15:0]SQ_Diff,
// output [15:0]SQ_Temp
);
/********... | 6.71682 |
module StreamSink #(
parameter SIZE = 256
, parameter WIDTH = 8
, parameter OUTPUT_FILE = ""
, parameter BURST = "yes"
) (
input iValid_AM
, output oReady_AM
, input [WIDTH-1:0] iData_AM
, output oEnd
, input i... | 7.162723 |
module StreamSource #(
parameter SIZE = 256
, parameter WIDTH = 8
, parameter INPUT_FILE = ""
, parameter BURST = "yes"
) (
input iStart
, output oValid_BM
, input iReady_BM
, output [WIDTH-1:0] oData_BM
, input i... | 6.724612 |
module streamToFinn_AXI_CPU_s_axi_ram #(
parameter BYTES = 4,
DEPTH = 256,
AWIDTH = log2(DEPTH)
) (
input wire clk0,
input wire [ AWIDTH-1:0] address0,
input wire ce0,
input wire we0,
input wire [ BYTES-1:0] be0,
input wire [BYTES*8-1:... | 6.924516 |
module streamToFinn_image_buffer_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram... | 6.924516 |
module streamToFinn_image_buffer (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd6144;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth... | 6.924516 |
module streamToFinn_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire... | 6.924516 |
module streamToFinn_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
... | 6.924516 |
module StreamWidthAdapter_1 (
input io_din_valid,
output io_din_ready,
input [31:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [ 7:0] io_dout_payload,
input clk,
input reset
);
wire [ 1:0] _zz__zz_io_din_ready_1;
... | 6.769753 |
module StreamWidthAdapter_2 (
input io_din_valid,
output io_din_ready,
input [ 7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [31:0] io_dout_payload,
input clk,
input reset
);
wire [ 1:0] _zz__zz_io_din_ready_1;
... | 6.769753 |
module Stream_1 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload,
input clk,
input reset
);
wire io_din_s2mPipe_valid;
wire io_din_s2mPi... | 6.733735 |
module Stream_2 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload
);
wire [7:0] _zz_tmp;
wire [7:0] _zz_tmp_1;
wire [7:0] tmp;
wire io_din_translated_valid;
wi... | 6.739889 |
module stream_buf (
input i_clk,
input i_rst,
// Upstream
input [7:0] i_data,
input i_valid,
output o_ready,
// Downstream
output [7:0] o_data,
output o_valid,
input i_ready
);
reg [7:0] buf_data;
reg [7:0] buf_data_ovfl;
reg buf_valid;
reg buf_ready;
reg buf_overflown... | 7.007997 |
module Stream_Buffer #(
// Primary parameters
parameter WIDTH = 128, // Width of an entry in the stream buffer
parameter DEPTH = 4, // Number of cache blocks that can be stored within the buffer
parameter T = 1, // 2^T is the number of stream buffer lines per cache block
// Calculated pa... | 7.727296 |
module stream_buffer_0_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_00 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_0_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_10 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_0_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_20 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_0_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_30 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_1_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_01 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_1_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_11 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_1_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_21 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_1_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_31 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
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