code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ag8j_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 13;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd13;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_ahbi_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 13;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd13;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aibs_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [59 : 0] din0,
input [59 : 0] din1,
input [59 : 0] din2,
input [59 : 0] din3,
input [ 1 : 0] din4,
output [59 : 0] dout
);
// puts internal signals
wire [ 1 : 0] sel;
// level 1 signals
wire [59 : 0] mux_1_0;
wire [59 : 0] mux_1_1;
// level 2 signals
wire [59 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
StreamingFCLayer_Batch_3_StreamingFCLayer_fYi_Mul_LUT_0 StreamingFCLayer_Batch_3_StreamingFCLayer_fYi_Mul_LUT_0_U(
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 60;
parameter AWIDTH = 8;
parameter MEM_SIZE = 240;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_3_qmc881x2/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_StreamingFCLayer_g8j_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd60;
parameter AddressRange = 32'd240;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_StreamingFCLayer_g8j_rom StreamingFCLayer_Batch_3_StreamingFCLayer_g8j_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_4_yxvt0poh/project_StreamingFCLayer_Batch_4/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb_rom StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ubkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 13;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_4_yxvt0poh/project_StreamingFCLayer_Batch_4/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd13;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud_rom StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ucud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_4_yxvt0poh/project_StreamingFCLayer_Batch_4/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe_rom StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2udEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_4_yxvt0poh/project_StreamingFCLayer_Batch_4/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg_rom StreamingFCLayer_Batch_4_Matrix_Vector_Activate_Stream_Batch_1152u_256u_16u_2u_Slice_Slice_ap_int_2_2ueOg_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_cud_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_cud (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
StreamingFCLayer_Batch_4_StreamingFCLayer_cud_Mul_LUT_0 StreamingFCLayer_Batch_4_StreamingFCLayer_cud_Mul_LUT_0_U(
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_dEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 10;
parameter MEM_SIZE = 600;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_4_rsiqbi19/project_StreamingFCLayer_Batch_4/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_4_StreamingFCLayer_dEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_4_StreamingFCLayer_dEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd600;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_4_StreamingFCLayer_dEe_rom StreamingFCLayer_Batch_4_StreamingFCLayer_dEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_5_u8mvjgu2/project_StreamingFCLayer_Batch_5/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb_rom StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_5_u8mvjgu2/project_StreamingFCLayer_Batch_5/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud_rom StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 9;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_5_u8mvjgu2/project_StreamingFCLayer_Batch_5/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd9;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe_rom StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apdEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_5_u8mvjgu2/project_StreamingFCLayer_Batch_5/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg_rom StreamingFCLayer_Batch_5_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_2u_Slice_ap_int_2u_Slice_apeOg_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_5_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_6_h23mbxdx/project_StreamingFCLayer_Batch_6/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb_rom StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_6_h23mbxdx/project_StreamingFCLayer_Batch_6/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud_rom StreamingFCLayer_Batch_6_Matrix_Vector_Activate_Stream_Batch_2304u_256u_8u_1u_Slice_ap_int_2u_Slice_apcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_6_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_6_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_7_ifvft2ge/project_StreamingFCLayer_Batch_7/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb_rom StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_7_ifvft2ge/project_StreamingFCLayer_Batch_7/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud_rom StreamingFCLayer_Batch_7_Matrix_Vector_Activate_Stream_Batch_1024u_256u_4u_1u_Slice_ap_int_2u_Slice_apcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_7_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_7_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_8_pmijdtqk/project_StreamingFCLayer_Batch_8/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb_rom StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_bkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_8_pmijdtqk/project_StreamingFCLayer_Batch_8/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud_rom StreamingFCLayer_Batch_8_Matrix_Vector_Activate_Stream_Batch_256u_256u_8u_1u_Slice_ap_int_2u_Slice_ap_cud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_8_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_8_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_9_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_9_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module streamlined_divider_4bit (
clk,
rst_n,
start_sig,
dividend,
divisor,
dong_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [3:0] dividend;
input [3:0] divisor;
output dong_sig;
output [3:0] quotient;
output [3:0] reminder;
/******************************/
reg [7:0] temp;
reg [7:0] diff;
reg [4:0] s;
reg [3:0] n;
/******************************/
reg isDone;
reg isNeg;
reg [3:0] q;
reg [3:0] r;
assign dong_sig = isDone;
assign quotient = q;
assign reminder = r;
/******************************/
reg [3:0] i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
temp <= 8'd0;
diff <= 8'd0;
s <= 5'd0;
isDone <= 1'b0;
isNeg <= 1'b0;
q <= 4'd0;
r <= 4'd0;
i <= 4'd0;
n <= 4'd0;
end else if (start_sig)
case (i)
0: begin
isNeg <= dividend[3] ^ divisor[3];
temp <= {4'd0, dividend};
diff <= 8'd0;
s <= divisor[3] ? {divisor[3], divisor} : {1'b1, (~divisor + 1'b1)};
q <= 4'd0;
r <= 4'd0;
i <= i + 1'b1;
end
1:
if (n == 4) begin
n <= 3'd0;
i <= 4'd3;
end else begin
diff <= temp + {s, 3'b0};
i <= i + 1'b1;
end
2: begin
if (diff[7]) temp <= {temp[6:0], 1'b0};
else temp <= {diff[6:0], 1'b1};
i <= 4'd1;
n <= n + 1'b1;
end
3: begin
q <= isNeg ? (~temp[3:0] + 1'b1) : temp[3:0];
r <= temp[7:4];
i <= i + 1'b1;
end
4: begin
isDone <= 1'b1;
i <= i + 1'b1;
end
5: begin
isDone <= 1'b0;
i <= 4'd0;
end
endcase
end
endmodule
| 6.71682 |
module streamlined_divider_4bit_improve (
clk,
rst_n,
start_sig,
dividend,
divisor,
dong_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [3:0] dividend;
input [3:0] divisor;
output dong_sig;
output [3:0] quotient;
output [3:0] reminder;
/******************************/
reg [7:0] temp;
reg [7:0] diff;
reg [4:0] s;
/******************************/
reg isDone;
reg [3:0] q;
reg [3:0] r;
assign dong_sig = isDone;
assign quotient = q;
assign reminder = r;
/******************************/
reg [2:0] i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i <= 3'd0;
isDone <= 1'b0;
q <= 4'd0;
r <= 4'd0;
temp <= 8'd0;
diff <= 8'd0;
s <= 5'd0;
end else if (start_sig)
case (i)
0: //初始化
begin
temp <= {4'd0, dividend};
s <= divisor[3] ? {divisor[3], divisor} : {~divisor[3], (~divisor + 1'b1)};
diff <= 8'd0;
q <= 4'd0;
r <= 4'd0;
i <= i + 1'b1;
end
1, 2, 3, 4: //计算
begin
diff = temp + {s, 3'b0}; //"="表示当前步骤取得结果 便于待会的diff[7]判断
if (diff[7]) temp <= {temp[6:0], 1'b0};
else temp <= {diff[6:0], 1'b1};
i <= i + 1'b1;
end
5: //求得结果
begin
q <= temp[3:0];
r <= temp[7:4];
i <= i + 1'b1;
end
6: begin
isDone <= 1'b1;
i <= i + 1'b1;
end
7: begin
isDone <= 1'b0;
i <= 3'd0;
end
endcase
end
endmodule
| 6.71682 |
module streamlined_divider_4bit_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [3:0] dividend;
reg [3:0] divisor;
wire dong_sig;
wire [3:0] quotient;
wire [3:0] reminder;
streamlined_divider_4bit u1 (
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.dividend(dividend),
.divisor(divisor),
.dong_sig(dong_sig),
.quotient(quotient),
.reminder(reminder)
);
initial begin
clk = 0;
rst_n = 0;
#250;
rst_n = 1;
forever #25 clk = ~clk;
end
reg [3:0] i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i <= 4'd0;
start_sig <= 1'b0;
dividend <= 4'd0;
divisor <= 4'd0;
end else
case (i)
0: // 7 / 2
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 4'd7;
divisor <= 4'd2;
end
1: // 7 / -2
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 4'd7;
divisor <= 4'b1110;
end
2: // -7 / 2
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 4'b1001;
divisor <= 4'd2;
end
3: // -7 / -2
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 4'b1001;
divisor <= 4'b1110;
end
4: i <= 4'd4;
endcase
end
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
endmodule
| 6.71682 |
module streamlined_divider_8bit_improve (
clk,
rst_n,
start_sig,
dividend,
divisor,
dong_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [7:0] dividend;
input [7:0] divisor;
output dong_sig;
output [7:0] quotient;
output [7:0] reminder;
/******************************/
reg [15:0] temp;
reg [15:0] diff;
reg [8:0] s;
/******************************/
reg isDone;
reg isqNeg;
reg isrNeg;
reg [7:0] q;
reg [7:0] r;
assign dong_sig = isDone;
assign quotient = q;
assign reminder = r;
/******************************/
reg [3:0] i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
temp <= 16'd0;
diff <= 16'd0;
s <= 9'd0;
isDone <= 1'b0;
isqNeg <= 1'b0;
isrNeg <= 1'b0;
q <= 8'd0;
r <= 8'd0;
i <= 4'd0;
end else if (start_sig)
case (i)
0: begin
isqNeg <= dividend[7] ^ divisor[7];
isrNeg <= dividend[7];
// temp <= {8'd0, dividend};
temp <= dividend[7] ? {8'd0, ~dividend + 1'b1} : {8'd0, dividend};
// temp <= dividend[7] ? {8'hff, ~dividend+1'b1} : {8'h00, dividend};
diff <= 16'd0;
s <= divisor[7] ? {1'b1, divisor} : {1'b1, (~divisor + 1'b1)};
q <= 8'd0;
r <= 8'd0;
i <= i + 1'b1;
end
1, 2, 3, 4, 5, 6, 7, 8: begin
diff = temp + {s, 7'd0};
if (diff[15]) temp <= {temp[14:0], 1'b0};
else temp <= {diff[14:0], 1'b1};
i <= i + 1'b1;
end
9: begin
q <= isqNeg ? (~temp[7:0] + 1'b1) : temp[7:0];
r <= isrNeg ? (~temp[15:8] + 1'b1) : temp[15:8];
i <= i + 1'b1;
end
10: begin
isDone <= 1'b1;
i <= i + 1'b1;
end
11: begin
isDone <= 1'b0;
i <= 4'd0;
end
endcase
end
endmodule
| 6.71682 |
module streamlined_divider_8bit_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [7:0] dividend;
reg [7:0] divisor;
wire dong_sig;
wire [7:0] quotient;
wire [7:0] reminder;
streamlined_divider_8bit_improve u1 (
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.dividend(dividend),
.divisor(divisor),
.dong_sig(dong_sig),
.quotient(quotient),
.reminder(reminder)
);
// streamlined_divider_demo u1(
// .CLK(clk),
// .RSTn(rst_n),
// .Start_Sig(start_sig),
// .Dividend(dividend),
// .Divisor(divisor),
// .Done_Sig(dong_sig),
// .Quotient(quotient),
// .Reminder(reminder)
// );
initial begin
clk = 0;
rst_n = 0;
#250;
rst_n = 1;
forever #25 clk = ~clk;
end
reg [3:0] i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i <= 4'd0;
start_sig <= 1'b0;
dividend <= 8'd0;
divisor <= 8'd0;
end else
case (i)
0: // 7 / 2
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 8'd7;
divisor <= 8'd2;
end
1: // 8 / -3
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 8'd8;
divisor <= 8'b1111_1101;
end
2: // -19 / 6
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 8'b1110_1101;
divisor <= 8'd6;
end
3: // -120 / -7
if (dong_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
dividend <= 8'b1000_1000;
divisor <= 8'b1111_1001;
end
4: i <= 4'd4;
endcase
end
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
endmodule
| 6.71682 |
module streamlined_divider_demo (
input CLK,
input RSTn,
input Start_Sig,
input [7:0] Dividend,
input [7:0] Divisor,
output Done_Sig,
output [7:0] Quotient,
output [7:0] Reminder
/**************************/
// output [15:0]SQ_Diff,
// output [15:0]SQ_Temp
);
/******************************/
reg [3:0] i;
reg [8:0] s;
reg [15:0] Temp;
reg [15:0] Diff;
reg isNeg;
reg isDone;
always @(posedge CLK or negedge RSTn)
if (!RSTn) begin
i <= 4'd0;
s <= 9'd0;
Temp <= 16'd0;
Diff <= 16'd0;
isNeg <= 1'b0;
isDone <= 1'b0;
end else if (Start_Sig)
case (i)
0: begin
isNeg <= Dividend[7] ^ Divisor[7];
s <= Divisor[7] ? {1'b1, Divisor} : {1'b1, ~Divisor + 1'b1};
Temp <= Dividend[7] ? {8'd0, ~Dividend + 1'b1} : {8'd0, Dividend};
Diff <= 16'd0;
i <= i + 1'b1;
end
1, 2, 3, 4, 5, 6, 7, 8: begin
Diff = Temp + {s, 7'd0};
if (Diff[15]) Temp <= {Temp[14:0], 1'b0};
else Temp <= {Diff[14:0], 1'b1};
i <= i + 1'b1;
end
9: begin
isDone <= 1'b1;
i <= i + 1'b1;
end
10: begin
isDone <= 1'b0;
i <= 2'd0;
end
endcase
/*********************************/
assign Done_Sig = isDone;
assign Quotient = isNeg ? (~Temp[7:0] + 1'b1) : Temp[7:0];
assign Reminder = Temp[15:8];
/**********************************/
// assign SQ_Diff = Diff;
// assign SQ_Temp = Temp;
/**********************************/
endmodule
| 6.71682 |
module StreamSink #(
parameter SIZE = 256
, parameter WIDTH = 8
, parameter OUTPUT_FILE = ""
, parameter BURST = "yes"
) (
input iValid_AM
, output oReady_AM
, input [WIDTH-1:0] iData_AM
, output oEnd
, input iRST
, input iCLK
);
integer i;
wire wrdy;
wire wvld;
wire [ WIDTH-1:0] wdata;
reg [$clog2(SIZE)-1:0] raddr;
reg [ WIDTH-1:0] rmem [0:SIZE-1];
reg ren;
generate
if (OUTPUT_FILE == "")
initial begin
wait (raddr == SIZE);
for (i = 0; i < SIZE; i = i + 1) $display("%b", rmem[i]);
end
else
initial begin
wait (raddr == SIZE);
$writememb(OUTPUT_FILE, rmem, 0, SIZE - 1);
end
endgenerate
//Register
Register #(
.WIDTH(WIDTH)
, .BURST(BURST)
) register (
.iValid_AM(iValid_AM)
, .oReady_AM(oReady_AM)
, .iData_AM(iData_AM)
, .oValid_BM(wvld)
, .iReady_BM(wrdy)
, .oData_BM(wdata)
, .iRST(iRST)
, .iCLK(iCLK)
);
//Address
always @(posedge iCLK)
if (iRST) raddr <= {$clog2(SIZE) {1'b0}};
else if (wrdy) raddr <= raddr + 1'b1;
assign wrdy = wvld && raddr < SIZE;
always @(posedge iCLK) if (wrdy) rmem[raddr] <= wdata;
//Enable
always @(posedge iCLK)
if (iRST) ren <= 1'b1;
else if (raddr == SIZE) ren <= 1'b0;
assign oEnd = !ren;
endmodule
| 7.162723 |
module StreamSource #(
parameter SIZE = 256
, parameter WIDTH = 8
, parameter INPUT_FILE = ""
, parameter BURST = "yes"
) (
input iStart
, output oValid_BM
, input iReady_BM
, output [WIDTH-1:0] oData_BM
, input iRST
, input iCLK
);
integer i;
wire wrdy;
wire wvld;
wire [ WIDTH-1:0] wdata;
reg [$clog2(SIZE)-1:0] raddr;
reg [ WIDTH-1:0] rmem [0:SIZE-1];
reg ren;
generate
if (INPUT_FILE == "") begin
integer bf;
initial begin
bf = 123456789;
for (i = 0; i < SIZE; i = i + 1) rmem[i] = $random(bf);
end
end else initial $readmemb(INPUT_FILE, rmem, 0, SIZE - 1);
endgenerate
//Enable
always @(posedge iCLK)
if (iRST) ren <= 1'b0;
else if (iStart) ren <= 1'b1;
//Address
always @(posedge iCLK)
if (iRST) raddr <= {$clog2(SIZE) {1'b0}};
else if (wvld) raddr <= raddr + 1'b1;
assign wvld = ren && wrdy && raddr < SIZE;
assign wdata = rmem[raddr];
//Register
Register #(
.WIDTH(WIDTH)
, .BURST(BURST)
) register (
.iValid_AM(wvld)
, .oReady_AM(wrdy)
, .iData_AM(wdata)
, .oValid_BM(oValid_BM)
, .iReady_BM(iReady_BM)
, .oData_BM(oData_BM)
, .iRST(iRST)
, .iCLK(iCLK)
);
endmodule
| 6.724612 |
module streamToFinn_AXI_CPU_s_axi_ram #(
parameter BYTES = 4,
DEPTH = 256,
AWIDTH = log2(DEPTH)
) (
input wire clk0,
input wire [ AWIDTH-1:0] address0,
input wire ce0,
input wire we0,
input wire [ BYTES-1:0] be0,
input wire [BYTES*8-1:0] d0,
output reg [BYTES*8-1:0] q0,
input wire clk1,
input wire [ AWIDTH-1:0] address1,
input wire ce1,
input wire we1,
input wire [ BYTES-1:0] be1,
input wire [BYTES*8-1:0] d1,
output reg [BYTES*8-1:0] q1
);
//------------------------Local signal-------------------
reg [BYTES*8-1:0] mem[0:DEPTH-1];
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 1;
m = 2;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Body---------------------------
// read port 0
always @(posedge clk0) begin
if (ce0) q0 <= mem[address0];
end
// read port 1
always @(posedge clk1) begin
if (ce1) q1 <= mem[address1];
end
genvar i;
generate
for (i = 0; i < BYTES; i = i + 1) begin : gen_write
// write port 0
always @(posedge clk0) begin
if (ce0 & we0 & be0[i]) begin
mem[address0][8*i+7:8*i] <= d0[8*i+7:8*i];
end
end
// write port 1
always @(posedge clk1) begin
if (ce1 & we1 & be1[i]) begin
mem[address1][8*i+7:8*i] <= d1[8*i+7:8*i];
end
end
end
endgenerate
endmodule
| 6.924516 |
module streamToFinn_image_buffer_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
endmodule
| 6.924516 |
module streamToFinn_image_buffer (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd6144;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
streamToFinn_image_buffer_ram streamToFinn_image_buffer_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0)
);
endmodule
| 6.924516 |
module streamToFinn_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.924516 |
module streamToFinn_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.924516 |
module StreamWidthAdapter_1 (
input io_din_valid,
output io_din_ready,
input [31:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [ 7:0] io_dout_payload,
input clk,
input reset
);
wire [ 1:0] _zz__zz_io_din_ready_1;
wire [ 0:0] _zz__zz_io_din_ready_1_1;
wire [31:0] _zz__zz_io_dout_payload;
reg [ 7:0] _zz_io_dout_payload_1;
wire io_dout_fire;
reg _zz_io_din_ready;
reg [ 1:0] _zz_io_din_ready_1;
reg [ 1:0] _zz_io_din_ready_2;
wire _zz_io_din_ready_3;
wire [31:0] _zz_io_dout_payload;
assign _zz__zz_io_din_ready_1_1 = _zz_io_din_ready;
assign _zz__zz_io_din_ready_1 = {1'd0, _zz__zz_io_din_ready_1_1};
assign _zz__zz_io_dout_payload = io_din_payload;
always @(*) begin
case (_zz_io_din_ready_2)
2'b00: _zz_io_dout_payload_1 = _zz_io_dout_payload[31 : 24];
2'b01: _zz_io_dout_payload_1 = _zz_io_dout_payload[23 : 16];
2'b10: _zz_io_dout_payload_1 = _zz_io_dout_payload[15 : 8];
default: _zz_io_dout_payload_1 = _zz_io_dout_payload[7 : 0];
endcase
end
assign io_dout_fire = (io_dout_valid && io_dout_ready);
always @(*) begin
_zz_io_din_ready = 1'b0;
if (io_dout_fire) begin
_zz_io_din_ready = 1'b1;
end
end
assign _zz_io_din_ready_3 = (_zz_io_din_ready_2 == 2'b11);
always @(*) begin
_zz_io_din_ready_1 = (_zz_io_din_ready_2 + _zz__zz_io_din_ready_1);
if (1'b0) begin
_zz_io_din_ready_1 = 2'b00;
end
end
assign io_dout_valid = io_din_valid;
assign _zz_io_dout_payload = _zz__zz_io_dout_payload;
assign io_dout_payload = _zz_io_dout_payload_1;
assign io_din_ready = (io_dout_ready && _zz_io_din_ready_3);
always @(posedge clk or posedge reset) begin
if (reset) begin
_zz_io_din_ready_2 <= 2'b00;
end else begin
_zz_io_din_ready_2 <= _zz_io_din_ready_1;
end
end
endmodule
| 6.769753 |
module StreamWidthAdapter_2 (
input io_din_valid,
output io_din_ready,
input [ 7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [31:0] io_dout_payload,
input clk,
input reset
);
wire [ 1:0] _zz__zz_io_din_ready_1;
wire [ 0:0] _zz__zz_io_din_ready_1_1;
wire [15:0] _zz__zz_io_dout_payload;
wire [31:0] _zz_io_dout_payload_1;
wire [31:0] _zz_io_dout_payload_2;
wire io_din_fire;
reg _zz_io_din_ready;
reg [ 1:0] _zz_io_din_ready_1;
reg [ 1:0] _zz_io_din_ready_2;
wire _zz_io_din_ready_3;
reg [23:0] _zz_io_dout_payload;
wire io_din_fire_1;
assign _zz__zz_io_din_ready_1_1 = _zz_io_din_ready;
assign _zz__zz_io_din_ready_1 = {1'd0, _zz__zz_io_din_ready_1_1};
assign _zz__zz_io_dout_payload = (_zz_io_dout_payload >>> 8);
assign _zz_io_dout_payload_2 = {io_din_payload, _zz_io_dout_payload};
assign _zz_io_dout_payload_1 = _zz_io_dout_payload_2;
assign io_din_fire = (io_din_valid && io_din_ready);
always @(*) begin
_zz_io_din_ready = 1'b0;
if (io_din_fire) begin
_zz_io_din_ready = 1'b1;
end
end
assign _zz_io_din_ready_3 = (_zz_io_din_ready_2 == 2'b11);
always @(*) begin
_zz_io_din_ready_1 = (_zz_io_din_ready_2 + _zz__zz_io_din_ready_1);
if (1'b0) begin
_zz_io_din_ready_1 = 2'b00;
end
end
assign io_din_fire_1 = (io_din_valid && io_din_ready);
assign io_dout_valid = (io_din_valid && _zz_io_din_ready_3);
assign io_dout_payload = _zz_io_dout_payload_1;
assign io_din_ready = (!((!io_dout_ready) && _zz_io_din_ready_3));
always @(posedge clk or posedge reset) begin
if (reset) begin
_zz_io_din_ready_2 <= 2'b00;
end else begin
_zz_io_din_ready_2 <= _zz_io_din_ready_1;
end
end
always @(posedge clk) begin
if (io_din_fire_1) begin
_zz_io_dout_payload <= {io_din_payload, _zz__zz_io_dout_payload};
end
end
endmodule
| 6.769753 |
module Stream_1 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload,
input clk,
input reset
);
wire io_din_s2mPipe_valid;
wire io_din_s2mPipe_ready;
wire [7:0] io_din_s2mPipe_payload;
reg io_din_rValid;
reg [7:0] io_din_rData;
assign io_din_ready = (!io_din_rValid);
assign io_din_s2mPipe_valid = (io_din_valid || io_din_rValid);
assign io_din_s2mPipe_payload = (io_din_rValid ? io_din_rData : io_din_payload);
assign io_dout_valid = io_din_s2mPipe_valid;
assign io_din_s2mPipe_ready = io_dout_ready;
assign io_dout_payload = io_din_s2mPipe_payload;
always @(posedge clk or posedge reset) begin
if (reset) begin
io_din_rValid <= 1'b0;
end else begin
if (io_din_valid) begin
io_din_rValid <= 1'b1;
end
if (io_din_s2mPipe_ready) begin
io_din_rValid <= 1'b0;
end
end
end
always @(posedge clk) begin
if (io_din_ready) begin
io_din_rData <= io_din_payload;
end
end
endmodule
| 6.733735 |
module Stream_2 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload
);
wire [7:0] _zz_tmp;
wire [7:0] _zz_tmp_1;
wire [7:0] tmp;
wire io_din_translated_valid;
wire io_din_translated_ready;
wire [7:0] io_din_translated_payload;
assign _zz_tmp = (io_din_payload + 8'h01);
assign _zz_tmp_1 = (io_din_payload - 8'h01);
assign tmp = ((8'h80 < io_din_payload) ? _zz_tmp : _zz_tmp_1);
assign io_din_translated_valid = io_din_valid;
assign io_din_ready = io_din_translated_ready;
assign io_din_translated_payload = tmp;
assign io_dout_valid = io_din_translated_valid;
assign io_din_translated_ready = io_dout_ready;
assign io_dout_payload = io_din_translated_payload;
endmodule
| 6.739889 |
module stream_buf (
input i_clk,
input i_rst,
// Upstream
input [7:0] i_data,
input i_valid,
output o_ready,
// Downstream
output [7:0] o_data,
output o_valid,
input i_ready
);
reg [7:0] buf_data;
reg [7:0] buf_data_ovfl;
reg buf_valid;
reg buf_ready;
reg buf_overflown;
wire up_transfer_ok;
wire down_transfer_ok;
assign up_transfer_ok = i_valid && o_ready;
assign down_transfer_ok = o_valid && i_ready;
// Output pins
assign o_data = buf_overflown ? buf_data_ovfl : buf_data;
assign o_valid = buf_valid;
assign o_ready = buf_ready && (!buf_overflown);
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
buf_data <= 8'b0;
buf_data_ovfl <= 8'b0;
buf_valid <= 1'b0;
buf_ready <= 1'b0;
buf_overflown <= 1'b0;
end else begin
// Buffer ready signal
buf_ready <= i_ready | (~buf_valid);
if (up_transfer_ok) begin
// Buffer data, set valid and overflow flags
buf_data_ovfl <= buf_data;
buf_data <= i_data;
buf_valid <= 1'b1;
// Overflow
if (!down_transfer_ok && buf_valid) begin
buf_overflown <= 1'b1;
end
end else begin
// Clear overflow and valid flags
if (down_transfer_ok) begin
if (buf_overflown) begin
buf_overflown <= 1'b0;
end else begin
buf_valid <= 1'b0;
end
end
end
end
end
endmodule
| 7.007997 |
module Stream_Buffer #(
// Primary parameters
parameter WIDTH = 128, // Width of an entry in the stream buffer
parameter DEPTH = 4, // Number of cache blocks that can be stored within the buffer
parameter T = 1, // 2^T is the number of stream buffer lines per cache block
// Calculated parameters
localparam ADDR_WIDTH = logb2(DEPTH),
localparam BLOCK_SECTIONS = 1 << T
) (
input CLK,
input RESET,
input [T - 1 : 0] SECTION_SEL,
input RD_ENB,
input WR_ENB,
input [WIDTH - 1 : 0] DATA_IN,
output reg [WIDTH - 1 : 0] DATA_OUT,
output EMPTY,
output FULL
);
reg [ WIDTH - 1 : 0] memory [0 : DEPTH * BLOCK_SECTIONS - 1];
reg [ADDR_WIDTH - 1 : 0] rd_counter;
reg rd_counter_msb;
reg [ADDR_WIDTH + T - 1 : 0] wr_counter;
reg wr_counter_msb;
assign FULL = (rd_counter_msb != wr_counter_msb) & ({rd_counter, {T{1'b0}}} == wr_counter);
assign EMPTY = ({rd_counter_msb, rd_counter, {T{1'b0}}} == {wr_counter_msb, wr_counter});
always @(posedge CLK) begin
if (RESET) begin
rd_counter <= 0;
rd_counter_msb <= 0;
wr_counter <= 0;
wr_counter_msb <= 0;
DATA_OUT <= 0;
end else begin
if (RD_ENB & !EMPTY) begin
{rd_counter_msb, rd_counter} <= {rd_counter_msb, rd_counter} + 1;
end
DATA_OUT <= memory[{rd_counter, SECTION_SEL}];
if (WR_ENB & !FULL) begin
{wr_counter_msb, wr_counter} <= {wr_counter_msb, wr_counter} + 1;
memory[wr_counter] <= DATA_IN;
end
end
end
initial begin
rd_counter = 0;
rd_counter_msb = 0;
wr_counter = 0;
wr_counter_msb = 0;
DATA_OUT = 0;
end
// Log value calculation
function integer logb2;
input integer depth;
for (logb2 = 0; depth > 1; logb2 = logb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 7.727296 |
module stream_buffer_0_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_00 buffer_16_24200_buffer_init_00_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_00 buffer_16_24200_buffer_init_00_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_00 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_0_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_10 buffer_16_24200_buffer_init_10_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_10 buffer_16_24200_buffer_init_10_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_10 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_0_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_20 buffer_16_12100_buffer_init_20_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_20 buffer_16_12100_buffer_init_20_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_20 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_0_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_30 buffer_16_12100_buffer_init_30_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_30 buffer_16_12100_buffer_init_30_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_30 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_1_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_01 buffer_16_24200_buffer_init_01_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_01 buffer_16_24200_buffer_init_01_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_01 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_1_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_11 buffer_16_24200_buffer_init_11_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_11 buffer_16_24200_buffer_init_11_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_11 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_1_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_21 buffer_16_12100_buffer_init_21_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_21 buffer_16_12100_buffer_init_21_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_21 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_1_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_31 buffer_16_12100_buffer_init_31_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_31 buffer_16_12100_buffer_init_31_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_31 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
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