code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module stream_buffer_2_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_02 buffer_16_24200_buffer_init_02_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_02 buffer_16_24200_buffer_init_02_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_02 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_2_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_12 buffer_16_24200_buffer_init_12_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_12 buffer_16_24200_buffer_init_12_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_12 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_2_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_22 buffer_16_12100_buffer_init_22_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_22 buffer_16_12100_buffer_init_22_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_22 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_2_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_32 buffer_16_12100_buffer_init_32_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_32 buffer_16_12100_buffer_init_32_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_32 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_3_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_03 buffer_16_24200_buffer_init_03_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_03 buffer_16_24200_buffer_init_03_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_03 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_3_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_13 buffer_16_24200_buffer_init_13_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_13 buffer_16_24200_buffer_init_13_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_13 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_3_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_23 buffer_16_12100_buffer_init_23_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_23 buffer_16_12100_buffer_init_23_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_23 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_3_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_33 buffer_16_12100_buffer_init_33_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_33 buffer_16_12100_buffer_init_33_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_33 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_4_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_04 buffer_16_24200_buffer_init_04_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_04 buffer_16_24200_buffer_init_04_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_04 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_4_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_14 buffer_16_24200_buffer_init_14_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_14 buffer_16_24200_buffer_init_14_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_14 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_4_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_24 buffer_16_12100_buffer_init_24_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_24 buffer_16_12100_buffer_init_24_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_24 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_4_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_34 buffer_16_12100_buffer_init_34_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_34 buffer_16_12100_buffer_init_34_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_34 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_5_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_05 buffer_16_24200_buffer_init_05_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_05 buffer_16_24200_buffer_init_05_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_05 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_5_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0] base_addr;
reg [14:0] offset;
reg [14:0] base_addr_b1;
reg [14:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 1) && (L_counter == 2)) begin
base_addr <= base_addr + 5;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 2) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 2;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 1) && (L_counter_b1 == 2)) begin
base_addr_b1 <= base_addr_b1 + 5;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 2) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 2;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 1) && (L_counter == 2)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [14:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_24200_buffer_init_15 buffer_16_24200_buffer_init_15_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_24200_buffer_init_15 buffer_16_24200_buffer_init_15_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_24200_buffer_init_15 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_5_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_25 buffer_16_12100_buffer_init_25_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_25 buffer_16_12100_buffer_init_25_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_25 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_buffer_5_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0] base_addr;
reg [13:0] offset;
reg [13:0] base_addr_b1;
reg [13:0] offset_b1;
reg [ 1:0] L_counter;
reg [ 1:0] C_counter;
reg [ 1:0] W_counter;
reg [ 1:0] L_counter_b1;
reg [ 1:0] C_counter_b1;
reg [ 1:0] W_counter_b1;
reg done, done_1, done_2, done_3;
reg valid, valid_1, valid_2;
wire [15:0] feature_out_b0;
wire [15:0] feature_out_b1;
always @(posedge clk) begin
if (i_reset) begin
base_addr <= 0;
offset <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
end else if (done == 0) begin
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
base_addr <= 0;
C_counter <= 0;
L_counter <= 0;
W_counter <= 0;
offset <= 0;
end else if ((C_counter == 0) && (L_counter == 3)) begin
base_addr <= base_addr + 4;
W_counter <= W_counter + 1'b1;
C_counter <= 0;
L_counter <= 0;
offset <= 0;
end else if (L_counter == 3) begin
base_addr <= base_addr + 1'b1;
C_counter <= C_counter + 1'b1;
L_counter <= 0;
offset <= 0;
end else begin
offset <= offset + 1;
L_counter <= L_counter + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset) begin
base_addr_b1 <= 0;
offset_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
end else if (done == 0) begin
if ((W_counter_b1 == 1443) && (C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= 0;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
W_counter_b1 <= 0;
offset_b1 <= 0;
end else if ((C_counter_b1 == 0) && (L_counter_b1 == 3)) begin
base_addr_b1 <= base_addr_b1 + 4;
W_counter_b1 <= W_counter_b1 + 1'b1;
C_counter_b1 <= 0;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else if (L_counter_b1 == 3) begin
base_addr_b1 <= base_addr_b1 + 1'b1;
C_counter_b1 <= C_counter_b1 + 1'b1;
L_counter_b1 <= 0;
offset_b1 <= 0;
end else begin
offset_b1 <= offset_b1 + 1;
L_counter_b1 <= L_counter_b1 + 1'b1;
end
end
end
always @(posedge clk) begin
if (i_reset == 1'b1) begin
done <= 0;
done_1 <= 0;
done_2 <= 0;
done_3 <= 0;
valid <= 0;
valid_1 <= 0;
valid_2 <= 0;
end else begin
valid <= 1;
if ((W_counter == 1443) && (C_counter == 0) && (L_counter == 3)) begin
done <= 1;
end
done_1 <= done;
done_2 <= done_1;
done_3 <= done_2;
valid_1 <= valid;
valid_2 <= valid_1;
end
end
reg [13:0] b0_waddr, b0_raddr, b1_raddr;
always @(*) begin
b0_waddr <= base_addr + offset;
b0_raddr <= base_addr + offset;
b1_raddr <= base_addr_b1 + offset_b1;
end
buffer_16_12100_buffer_init_35 buffer_16_12100_buffer_init_35_B0 (
.clk (clk),
.wen (i_wen0),
.waddr(b0_waddr),
.wdata(i_ddr),
.raddr(b0_raddr),
.rdata(feature_out_b0)
);
reg [15:0] B1_wdata;
always @(*) begin
if (i_eltwise_sel) begin
B1_wdata <= i_eltwise;
end else begin
B1_wdata <= i_pool;
end
end
buffer_16_12100_buffer_init_35 buffer_16_12100_buffer_init_35_B1 (
.clk (clk),
.wen (i_wen1),
.waddr(i_waddr),
.wdata(B1_wdata),
.raddr(b1_raddr),
.rdata(feature_out_b1)
);
assign o_done = valid_2 && (~done_3);
assign o_feature_0 = feature_out_b0;
assign o_feature_1 = feature_out_b1;
endmodule
| 6.648114 |
module buffer_16_12100_buffer_init_35 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module stream_cap #(
parameter SCR_SIZE_BIT
) (
input wire i_pxl_clk,
input wire i_reset_n,
// internal bus
input wire i_clk_bus,
input wire [ 4:0] i_addr,
input wire [ 7:0] i_data_wr,
input wire i_select,
input wire i_wr_req,
output wire [ 7:0] o_data_wr,
//
input wire [ 3:0] i_R,
input wire [ 3:0] i_G,
input wire [ 3:0] i_B,
input wire i_I,
input wire i_HS,
input wire i_VS,
//
output wire [ 11:0] o_fifo_data,
output wire o_active,
output wire o_active_negedge,
output wire [ 8:0] o_line,
//
output wire [SCR_SIZE_BIT:0] o_x_size,
output wire [SCR_SIZE_BIT:0] o_y_size
);
wire [11:0] w_x_start, w_x_size, w_y_start, w_y_size;
wire w_HS_inv, w_VS_inv;
wire [2:0] w_mux_mode;
vcap_regs u_regs (
.i_clk (i_clk_bus),
.i_reset_n (i_reset_n),
.i_addr (i_addr[4:0]),
.i_data_wr (i_data_wr),
.i_select (i_select),
.i_wr_req (i_wr_req),
.o_data_wr (o_data_wr),
//
.o_x_start (w_x_start),
.o_x_size (w_x_size),
.o_y_start (w_y_start),
.o_y_size (w_y_size),
.o_HS_inv (w_HS_inv),
.o_VS_inv (w_VS_inv),
.o_mux_mode (w_mux_mode)
);
wire [3:0] w_R, w_G, w_B;
assign w_R = (w_mux_mode == 3'd0) ? i_R :
(w_mux_mode == 3'd1) ? { i_R[0], i_R[0] & i_I, i_R[0], i_R[0] } :
(w_mux_mode == 3'd2) ? 4'b0 :
i_R;
assign w_G = (w_mux_mode == 3'd0) ? i_G :
(w_mux_mode == 3'd1) ? { i_G[0], i_G[0] & i_I, i_G[0], i_G[0] } :
(w_mux_mode == 3'd2) ? 4'b0 :
i_G;
assign w_B = (w_mux_mode == 3'd0) ? i_B :
(w_mux_mode == 3'd1) ? { i_B[0], i_B[0] & i_I, i_B[0], i_B[0] } :
(w_mux_mode == 3'd2) ? 4'b0 :
i_B;
reg [3:0] r_R, r_G, r_B;
reg r_HS, r_VS, r_HS_prev, r_VS_prev;
always @(posedge i_pxl_clk) begin
r_R <= w_R;
r_G <= w_G;
r_B <= w_B;
r_HS <= i_HS ^ w_HS_inv;
r_VS <= i_VS ^ w_VS_inv;
r_HS_prev <= r_HS;
r_VS_prev <= r_VS;
end
wire w_HS_negedge = (!r_HS) & r_HS_prev;
wire w_VS_negedge = (!r_VS) & r_VS_prev;
reg [(SCR_SIZE_BIT-1):0] r_x_cnt;
reg [(SCR_SIZE_BIT-1):0] r_y_cnt;
always @(posedge i_pxl_clk) begin
if (w_HS_negedge) r_x_cnt <= {SCR_SIZE_BIT{1'b0}};
else r_x_cnt <= r_x_cnt + 1'b1;
end
always @(posedge i_pxl_clk) begin
if (w_VS_negedge) r_y_cnt <= {SCR_SIZE_BIT{1'b0}};
else if (w_HS_negedge == 1'b1) r_y_cnt <= r_y_cnt + 1'b1;
end
wire w_x_active = (r_x_cnt >= w_x_start) && (r_x_cnt <= (w_x_start + w_x_size));
wire w_y_active = (r_y_cnt >= w_y_start) && (r_y_cnt <= (w_y_start + w_y_size));
wire w_active = w_x_active & w_y_active;
reg r_active;
reg r_active_prev;
wire w_active_negedge = (!r_active) && r_active_prev;
reg [11:0] r_data_pipe0, r_data_pipe1, r_data_pipe2;
always @(posedge i_pxl_clk) begin
r_active <= w_active;
r_active_prev <= r_active;
r_data_pipe0 <= {r_R, r_G, r_B};
r_data_pipe1 <= r_data_pipe0;
r_data_pipe2 <= r_data_pipe1;
end
wire r_active_negedge;
always @(posedge i_pxl_clk) begin
r_active_negedge <= w_active_negedge;
end
wire [(SCR_SIZE_BIT-1):0] w_y_act = (r_y_cnt - w_y_start);
reg [(SCR_SIZE_BIT-1):0] r_y_act;
always @(posedge i_pxl_clk) begin
r_y_act <= w_y_act;
end
assign o_x_size = w_x_size;
assign o_y_size = w_y_size;
assign o_fifo_data = r_data_pipe2;
assign o_active = r_active;
assign o_active_negedge = r_active_negedge;
assign o_line = r_y_act[8:0];
endmodule
| 7.720136 |
module stream_collector #(
parameter NS = 2, // number of sources
parameter DW = 32 // data width
) (
// system
input wire clk, // clock
input wire clk_en, // clock enable
input wire rst, // reset
// input
input wire [NS-1:0] in_vld, // input valid
output wire [NS-1:0] in_rdy, // input ack
input wire [NS-1:0][DW-1:0] in_dat, // input data
// output
output wire out_vld, // output valid
input wire out_rdy, // output ack
output wire [DW-1:0] out_dat // output data
);
//// one-hot source select, priority encoded ////
wire [NS-1:0] ss;
assign ss[0] = in_vld[0];
genvar s;
generate
for (s = 1; s < NS; s = s + 1) begin : SS_GEN_BLK
assign ss[s] = in_vld[s] && ~|in_vld[s-1:0];
end
endgenerate
////
localparam NSLOG = $clog2(NS);
wire [NSLOG-1:0] ss_a;
genvar i, j;
generate
for (j = 0; j < NSLOG; j = j + 1) begin : SS_MASK_OL
wire [NS-1:0] ss_msk;
for (i = 0; i < NS; i = i + 1) begin : SS_MASK_IL
assign ss_msk[i] = i[j];
end
assign ss_a[j] = |(ss & ss_msk);
end
endgenerate
//// handle ////
wire or_in_vld;
wire or_in_rdy;
wire [DW-1:0] or_in_dat;
assign or_in_vld = |in_vld;
assign or_in_dat = in_dat[ss_a];
assign in_rdy = {NS{or_in_rdy}} & ss;
//// output stream reg ////
stream_reg #(
.DW(DW) // data width
) str_reg (
.clk (clk), // clock
.clk_en (clk_en), // clock enable
.rst (rst), // reset
.in_vld (or_in_vld), // input valid
.in_rdy (or_in_rdy), // input ack
.in_dat (or_in_dat), // input data
.out_vld(out_vld), // output valid
.out_rdy(out_rdy), // output ack
.out_dat(out_dat) // output data
);
endmodule
| 6.965826 |
module
`timescale 1ns/1ns
module stream_cypher_tb;
reg clk;
reg rst;
reg en;
reg init;
reg [8*8-1:0] ck;
reg [8*8-1:0] sb;
wire [8*8-1:0] cb;
reg [24*8-1:0] tt; // input
initial
begin
// $read_data(
// "../test_dat/stream_cypher.in"
// ,tt
// );
tt=192'b001001110001111100011000000100010000101000000010111110111111010011101101111001101101111011010111110100001100100111000001101110101011001110101100101001001001110110010110100011111000011110000000;
@(posedge rst);
ck =tt[ 24* 8-1: 16* 8];
en=1;
init=1;
sb =tt[ 16*8-1:8* 8];
@(posedge clk);
en=1;
init=0;
sb =tt[ 8*8-1:0* 8];
// $write_data(
// "../test_dat/stream_cypher.out.v"
// ,"w"
// ,cb
// );
@(posedge clk);
$display("\ncb=%b\n",cb);
$display("b.b.b1.b1.op=%b\n",b.b.b1.b1.op);
$display("b.b.b1.b1.Do=%b\n",b.b.b1.b1.Do);
$display("b.b.b1.b1.Ei=%b\n",b.b.b1.b1.Ei);
$display("b.b.b1.b1.Zi=%b\n",b.b.b1.b1.Zi);
$display("b.b.b1.b1.extra_B=%b\n",b.b.b1.b1.extra_B);
$display("b.b.b1.b2.op=%b\n",b.b.b1.b2.op);
$display("b.b.b1.b3.op=%b\n",b.b.b1.b3.op);
$display("b.b.b1.b4.op=%b\n",b.b.b1.b4.op);
// $write_data(
// "../test_dat/stream_cypher.out.v"
// ,"a"
// ,cb
// );
@(posedge clk);
$finish;
end
initial
begin
clk<=1'b0;
forever #5 clk=~clk;
end
initial
begin
rst<=1'b0;
@(posedge clk);
@(posedge clk);
rst=1'h1;
end
stream_cypher b(
.clk (clk)
,.rst_n (rst)
,.en (en)
,.init (init)
,.ck (ck)
,.sb (sb)
,.cb (cb)
);
endmodule
| 6.608387 |
module stream_distributor #(
parameter NS = 2, // number of sinks
parameter DW = 32 // data width
) (
// system
input wire clk, // clock
input wire clk_en, // clock enable
input wire rst, // reset
// input
input wire in_vld, // input valid
output wire in_rdy, // input ack
input wire [DW-1:0] in_dat, // input data
// output
output wire [NS-1:0] out_vld, // output valid
input wire [NS-1:0] out_rdy, // output ack
output wire [DW-1:0] out_dat // output data
);
//// input stream reg ////
wire ir_out_vld;
wire ir_out_rdy;
stream_reg #(
.DW(DW) // data width
) str_reg (
.clk (clk), // clock
.clk_en (clk_en), // clock enable
.rst (rst), // reset
.in_vld (in_vld), // input valid
.in_rdy (in_rdy), // input ack
.in_dat (in_dat), // input data
.out_vld(ir_out_vld), // output valid
.out_rdy(ir_out_rdy), // output ack
.out_dat(out_dat) // output data
);
//// one-hot sink select, priority encoded ////
wire [NS-1:0] ss;
assign ss[0] = out_rdy[0];
genvar s;
generate
for (s = 1; s < NS; s = s + 1) begin : SS_GEN_BLK
assign ss[s] = out_rdy[s] && ~|out_rdy[s-1:0];
end
endgenerate
//// handle out_rdy & out_vld ////
assign ir_out_rdy = |out_rdy;
assign out_vld = {NS{ir_out_vld}} & ss;
endmodule
| 6.719628 |
module stream_fifo #(
parameter AW = 8,
parameter DW = 8,
parameter USE_SHORTFIFO = 1
) (
input clk,
input [DW-1:0] d_in,
input d_in_valid,
input d_in_last,
output d_in_ready,
input d_out_ready,
output [DW-1:0] d_out,
output d_out_last,
output d_out_valid,
output fifo_empty
);
wire d_out_last_i;
wire fifo_re = ~fifo_empty & d_out_ready;
wire fifo_full;
generate
if (USE_SHORTFIFO)
shortfifo #(
.dw(DW + 1),
.aw(AW)
) stream_tx_i (
.clk(clk),
.din({d_in, d_in_last}),
.we(d_in_valid),
.dout({d_out, d_out_last_i}),
.re(fifo_re),
.full(fifo_full),
.empty(fifo_empty)
);
else
fifo #(
.dw(DW + 1),
.aw(AW)
) stream_tx_i (
.clk(clk),
.din({d_in, d_in_last}),
.we(d_in_valid),
.dout({d_out, d_out_last_i}),
.re(fifo_re),
.full(fifo_full),
.empty(fifo_empty)
);
endgenerate
assign d_out_valid = ~fifo_empty;
assign d_out_last = d_out_last_i & d_out_valid;
assign d_in_ready = !fifo_full || fifo_re;
endmodule
| 7.864008 |
module stream_fifo_if #(
parameter DW = 0
) (
input clk,
input rst,
//FIFO Interface
input [DW-1:0] fifo_data_i,
output fifo_rd_en_o,
input fifo_empty_i,
//Stream Interface
output reg [DW-1:0] stream_m_data_o,
output reg stream_m_valid_o,
input stream_m_ready_i
);
reg fifo_valid, middle_valid;
reg [DW-1:0] middle_dout;
wire will_update_dout = (middle_valid || fifo_valid) && (stream_m_ready_i || !stream_m_valid_o);
wire will_update_middle = fifo_valid && (middle_valid == will_update_dout);
assign fifo_rd_en_o = (!fifo_empty_i) && !(middle_valid && stream_m_valid_o && fifo_valid);
always @(posedge clk)
if (rst) begin
fifo_valid <= 0;
middle_valid <= 0;
stream_m_valid_o <= 0;
stream_m_data_o <= 0;
middle_dout <= 0;
end else begin
if (will_update_middle) middle_dout <= fifo_data_i;
if (will_update_dout) stream_m_data_o <= middle_valid ? middle_dout : fifo_data_i;
if (fifo_rd_en_o) fifo_valid <= 1;
else if (will_update_middle || will_update_dout) fifo_valid <= 0;
if (will_update_middle) middle_valid <= 1;
else if (will_update_dout) middle_valid <= 0;
if (will_update_dout) stream_m_valid_o <= 1;
else if (stream_m_ready_i) stream_m_valid_o <= 0;
end
endmodule
| 6.889887 |
module stream_fifo_tb;
localparam DW = 16;
localparam AW = 4;
localparam WORDS = 4800;
vlog_tb_utils vtu ();
vlog_tap_generator #("stream_fifo.tap", 1) vtg ();
reg clk = 1'b1;
reg rst = 1'b1;
always #5 clk <= !clk;
initial #100 rst <= 1'b0;
wire [DW-1:0] dut_in_data;
wire dut_in_valid;
wire dut_in_ready;
wire [DW-1:0] dut_out_data;
wire dut_out_valid;
wire dut_out_ready;
stream_writer #(
.WIDTH(DW),
.MAX_BLOCK_SIZE(WORDS)
) writer (
.clk(clk),
.stream_m_data_o(dut_in_data),
.stream_m_valid_o(dut_in_valid),
.stream_m_ready_i(dut_in_ready)
);
stream_reader #(
.WIDTH(DW),
.MAX_BLOCK_SIZE(WORDS)
) reader (
.clk(clk),
.stream_s_data_i(dut_out_data),
.stream_s_valid_i(dut_out_valid),
.stream_s_ready_o(dut_out_ready)
);
stream_fifo #(
.DW(DW),
.AW(AW)
) dut (
.clk(clk),
.rst(rst),
.s_data_i(dut_in_data),
.s_valid_i(dut_in_valid),
.s_ready_o(dut_in_ready),
.m_data_o (dut_out_data),
.m_valid_o(dut_out_valid),
.m_ready_i(dut_out_ready)
);
reg [DW-1:0] expected [0:WORDS-1];
//integer i;
real write_rate;
real read_rate;
initial begin
create_stimuli();
if ($value$plusargs("write_rate=%f", write_rate)) begin
$display("Setting stream write rate to %0f", write_rate);
writer.rate = write_rate;
end
if ($value$plusargs("read_rate=%f", read_rate)) begin
$display("Setting stream read rate to %0f", read_rate);
reader.rate = read_rate;
end
fork
begin
@(posedge clk);
stream_write();
end
begin
stream_read();
$display("Reader done");
end
join
$finish;
end
task stream_write;
integer idx;
begin
for (idx = 0; idx < WORDS; idx = idx + 1) writer.write_word(expected[idx]);
$display("Writer done");
end
endtask
task stream_read;
reg [ DW-1:0] word;
integer idx;
reg [8*50-1:0] s;
begin
for (idx = 0; idx < WORDS; idx = idx + 1) begin
reader.read_word(word);
if (word !== expected[idx]) begin
$sformat(s, "Error on index %0d. Expected 0x%4x. Got 0x%4x", idx, expected[idx], word);
$display("%0s", s);
vtg.nok(s);
#100 $finish;
end
end
vtg.ok("All tests passed");
end
endtask
task create_stimuli;
integer idx;
integer tmp;
integer seed;
begin
for (idx = 0; idx < WORDS; idx = idx + 1) begin
tmp = $random(seed);
expected[idx] = tmp[DW-1:0];
end
end
endtask
endmodule
| 6.635976 |
module Stream_Flow_Control #(
parameter PACKET_BITS = 97,
parameter NUM_LEAF_BITS = 6,
parameter NUM_PORT_BITS = 4,
parameter NUM_ADDR_BITS = 7,
parameter PAYLOAD_BITS = 64,
parameter NUM_IN_PORTS = 7,
parameter NUM_OUT_PORTS = 7,
parameter NUM_BRAM_ADDR_BITS = 7,
parameter FREESPACE_UPDATE_SIZE = 64,
localparam OUT_PORTS_REG_BITS=NUM_LEAF_BITS+NUM_PORT_BITS+NUM_ADDR_BITS+NUM_ADDR_BITS+3,
localparam IN_PORTS_REG_BITS = NUM_LEAF_BITS + NUM_PORT_BITS,
localparam REG_CONTROL_BITS=OUT_PORTS_REG_BITS*NUM_OUT_PORTS+IN_PORTS_REG_BITS*NUM_IN_PORTS
) (
input resend,
input clk,
input reset,
input [PACKET_BITS-1:0] stream_in,
output [PACKET_BITS-1:0] stream_out,
input [REG_CONTROL_BITS-1:0] control_reg,
//data to USER
output [PAYLOAD_BITS*NUM_IN_PORTS-1:0] dout_leaf_interface2user,
output [NUM_IN_PORTS-1:0] vld_interface2user,
input [NUM_IN_PORTS-1:0] ack_user2interface,
//data from USER
output [NUM_OUT_PORTS-1:0] ack_interface2user,
input [NUM_OUT_PORTS-1:0] vld_user2interface,
input [PAYLOAD_BITS*NUM_OUT_PORTS-1:0] din_leaf_user2interface
);
wire [NUM_IN_PORTS-1:0] freespace_update;
wire [NUM_OUT_PORTS-1:0] empty;
wire [PACKET_BITS*NUM_IN_PORTS-1:0] packet_from_input_ports;
wire [PACKET_BITS*NUM_OUT_PORTS-1:0] packet_from_output_ports;
wire [NUM_OUT_PORTS-1:0] rd_en_sel;
converge_ctrl #(
.PACKET_BITS (PACKET_BITS),
.NUM_PORT_BITS(NUM_PORT_BITS),
.NUM_IN_PORTS (NUM_IN_PORTS),
.NUM_OUT_PORTS(NUM_OUT_PORTS)
) ConCtrl (
.clk(clk),
.reset(reset),
.outport_sel(rd_en_sel),
.stream_out(stream_out),
.freespace_update(freespace_update),
.packet_from_input_ports(packet_from_input_ports),
.packet_from_output_ports(packet_from_output_ports),
.empty(empty),
.resend(resend)
);
Input_Port_Cluster #(
.PACKET_BITS(PACKET_BITS),
.NUM_LEAF_BITS(NUM_LEAF_BITS),
.NUM_PORT_BITS(NUM_PORT_BITS),
.NUM_ADDR_BITS(NUM_ADDR_BITS),
.PAYLOAD_BITS(PAYLOAD_BITS),
.NUM_IN_PORTS(NUM_IN_PORTS),
.NUM_OUT_PORTS(NUM_OUT_PORTS),
.NUM_BRAM_ADDR_BITS(NUM_BRAM_ADDR_BITS),
.FREESPACE_UPDATE_SIZE(FREESPACE_UPDATE_SIZE)
) ipc (
.clk(clk),
.reset(reset),
.freespace_update(freespace_update),
.packet_from_input_ports(packet_from_input_ports),
.stream_in(stream_in),
.in_control_reg(control_reg[IN_PORTS_REG_BITS*NUM_IN_PORTS-1:0]),
.dout2user(dout_leaf_interface2user),
.vld2user(vld_interface2user),
.ack_user2b_in(ack_user2interface)
);
Output_Port_Cluster #(
.PACKET_BITS(PACKET_BITS),
.NUM_LEAF_BITS(NUM_LEAF_BITS),
.NUM_PORT_BITS(NUM_PORT_BITS),
.NUM_ADDR_BITS(NUM_ADDR_BITS),
.PAYLOAD_BITS(PAYLOAD_BITS),
.NUM_IN_PORTS(NUM_IN_PORTS),
.NUM_OUT_PORTS(NUM_OUT_PORTS),
.NUM_BRAM_ADDR_BITS(NUM_BRAM_ADDR_BITS),
.FREESPACE_UPDATE_SIZE(FREESPACE_UPDATE_SIZE)
) opc (
.clk(clk),
.reset(reset),
.out_control_reg(control_reg[REG_CONTROL_BITS-1:IN_PORTS_REG_BITS*NUM_IN_PORTS]),
.internal_out(packet_from_output_ports),
.empty(empty),
.rd_en_sel(rd_en_sel),
.ack_b_out2user(ack_interface2user),
.din_leaf_user2interface(din_leaf_user2interface),
.vld_user2b_out(vld_user2interface)
);
endmodule
| 7.361273 |
module stream_master_v1_0 #(
// Users to add parameters here
parameter NUMBER_OF_OUTPUT_WORDS = 8,
parameter INITIAL_NUMBER = 1,
parameter ITERATION_NUMBER = 2,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M_AXIS
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_START_COUNT = 32
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M_AXIS
input wire m_axis_aclk,
input wire m_axis_aresetn,
output wire m_axis_tvalid,
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] m_axis_tdata,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] m_axis_tstrb,
output wire m_axis_tlast,
input wire m_axis_tready
);
// Instantiation of Axi Bus Interface M_AXIS
stream_master_v1_0_M_AXIS #(
.NUMBER_OF_OUTPUT_WORDS(NUMBER_OF_OUTPUT_WORDS),
.INITIAL_NUMBER(INITIAL_NUMBER),
.ITERATION_NUMBER(ITERATION_NUMBER),
.C_M_AXIS_TDATA_WIDTH(C_M_AXIS_TDATA_WIDTH),
.C_M_START_COUNT(C_M_AXIS_START_COUNT)
) stream_master_v1_0_M_AXIS_inst (
.M_AXIS_ACLK(m_axis_aclk),
.M_AXIS_ARESETN(m_axis_aresetn),
.M_AXIS_TVALID(m_axis_tvalid),
.M_AXIS_TDATA(m_axis_tdata),
.M_AXIS_TSTRB(m_axis_tstrb),
.M_AXIS_TLAST(m_axis_tlast),
.M_AXIS_TREADY(m_axis_tready)
);
// Add user logic here
// User logic ends
endmodule
| 7.014447 |
module stream_reader #(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024
) (
input clk,
input [WIDTH-1:0] stream_s_data_i,
output reg stream_s_ready_o = 1'b0,
input stream_s_valid_i
);
real rate = 0.5;
integer seed = 0;
time timeout = 0;
reg err_timeout = 0;
task read_word;
output [WIDTH-1:0] data_o;
reg rd;
real randval;
time t0;
begin
stream_s_ready_o = 1'b0;
rd = 1'b0;
t0 = $time;
while ((!stream_s_valid_i | !stream_s_ready_o) & !err_timeout) begin
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
rd = (randval <= rate);
stream_s_ready_o <= rd;
@(posedge clk);
data_o = stream_s_data_i;
if (timeout > 0) err_timeout = ($time - t0) > timeout;
end
stream_s_ready_o <= 1'b0;
if (err_timeout) begin
$display("%0d : Timeout in FIFO reader", $time);
$finish;
end
err_timeout = 1'b0;
end
endtask
task read_block;
output reg [WIDTH*MAX_BLOCK_SIZE-1:0] data_o;
input integer length_i;
integer index;
reg [WIDTH-1:0] word;
begin
//Cap rate to [0.0-1.0]
if (rate > 1.0) rate = 1.0;
if (rate < 0.0) rate = 0.0;
index = 0;
while (index < length_i) begin
read_word(word);
//$display("%0d : Read word 0x%8x", $time, word);
data_o[index*WIDTH+:WIDTH] = word;
index = index + 1;
end // while (index < length_i)
end
endtask
endmodule
| 7.29683 |
module STREAM_REG (
ready_out,
valid_out,
data_out,
ready_in,
valid_in,
data_in,
clk,
rst_n
);
// Input Port(s)
input clk, rst_n;
input ready_in, valid_in;
input [DATA_WIDTH-1:0] data_in;
// Output Port(s)
output ready_out, valid_out;
output reg [DATA_WIDTH-1:0] data_out;
// Parameter Declaration(s)
parameter DATA_WIDTH = 26;
reg data_valid, ready_in_d;
always @(posedge clk) begin
if (~rst_n) begin
data_out <= 1'b0;
data_valid <= 0;
ready_in_d <= 0;
end else begin
ready_in_d <= ready_in;
if (valid_in & (~data_valid | ready_in_d)) begin
data_out <= data_in;
data_valid <= 1;
end else if (ready_in_d) begin
data_valid <= 0;
end
end
end
assign ready_out = (~data_valid & ~valid_in) | ready_in;
assign valid_out = ready_in_d & data_valid;
endmodule
| 6.717989 |
module STREAM_REG_TEST (
input clk,
input reset_n,
input en_src,
input snk_ready,
output reg [7:0] src_data,
output [7:0] snk_data,
output reg [7:0] data_out,
output reg src_valid,
output reg_valid,
output reg_ready
);
always @(posedge clk) begin
if (~reset_n) begin
src_data <= 8'h0;
src_valid <= 1'b0;
end else begin
src_valid <= 1'b0;
if (en_src & reg_ready) begin
src_data = src_data + 8'h1;
src_valid <= 1'b1;
end
end
end
STREAM_REG #(
.DATA_WIDTH(8)
) SR0 (
.clk(clk),
.rst_n(reset_n),
.ready_out(reg_ready),
.valid_out(reg_valid),
.data_out(snk_data),
.ready_in(snk_ready),
.valid_in(src_valid),
.data_in(src_data)
);
always @(posedge clk) begin
if (~reset_n) begin
data_out <= 8'h0;
end else begin
if (reg_valid) begin
data_out <= snk_data;
end
end
end
endmodule
| 6.819824 |
module stream_slave_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXIS
parameter integer C_S_AXIS_TDATA_WIDTH = 32
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXIS
input wire s_axis_aclk,
input wire s_axis_aresetn,
output wire s_axis_tready,
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] s_axis_tdata,
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] s_axis_tstrb,
input wire s_axis_tlast,
input wire s_axis_tvalid
);
// Instantiation of Axi Bus Interface S_AXIS
stream_slave_v1_0_S_AXIS #(
.C_S_AXIS_TDATA_WIDTH(C_S_AXIS_TDATA_WIDTH)
) stream_slave_v1_0_S_AXIS_inst (
.S_AXIS_ACLK(s_axis_aclk),
.S_AXIS_ARESETN(s_axis_aresetn),
.S_AXIS_TREADY(s_axis_tready),
.S_AXIS_TDATA(s_axis_tdata),
.S_AXIS_TSTRB(s_axis_tstrb),
.S_AXIS_TLAST(s_axis_tlast),
.S_AXIS_TVALID(s_axis_tvalid)
);
// Add user logic here
// User logic ends
endmodule
| 8.903427 |
module stream_writer #(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024
) (
input clk,
output reg [WIDTH-1:0] stream_m_data_o,
output reg stream_m_valid_o = 1'b0,
input stream_m_ready_i
);
real rate = 0.5;
integer seed = 0;
initial begin
rate = 0.5;
end
task write_word;
input [WIDTH-1:0] word_i;
reg wr;
real randval;
begin
stream_m_valid_o = 1'b0;
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
wr = (randval <= rate);
while (!wr) begin
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
wr = (randval <= rate);
@(posedge clk);
end
stream_m_data_o <= word_i;
stream_m_valid_o <= 1'b1;
@(posedge clk);
while (!stream_m_ready_i) begin
@(posedge clk);
end
stream_m_valid_o <= 1'b0;
end
endtask
task write_block;
input [WIDTH*MAX_BLOCK_SIZE-1:0] data_i;
input integer length_i;
integer index;
begin
//Cap rate to [0.0-1.0]
if (rate > 1.0) rate = 1.0;
if (rate < 0.0) rate = 0.0;
index = 0;
while (index < length_i) begin
write_word(data_i[index*WIDTH+:WIDTH]);
index = index + 1;
end
end
endtask
endmodule
| 7.09698 |
module stretch (
input n, // 1 clock wide
output w, // 16 clocks wide (0.33 us @ 48 MHz)
input c // clock
);
// internal signals
reg t; // toggle FF
reg [15:0] d; // delay line
reg q; // output FF
// logic
always @(posedge c) begin
if (n) t <= ~t; // toggle on input pulse
d <= {d[14:0], t}; // shift register
q <= t ^ d[15]; // latch output
end
assign w = q; // always 32 clocks wide
endmodule
| 6.818439 |
module stretch32 (
input n, // 1 clock wide
output w, // 32 clocks wide (0.67 us @ 48 MHz)
input c // clock
);
// internal signals
reg t; // toggle FF
reg [31:0] d; // delay line
reg q; // output FF
// logic
always @(posedge c) begin
if (n) t <= ~t; // toggle on input pulse
d <= {d[30:0], t}; // shift register
q <= t ^ d[31]; // latch output
end
assign w = q; // always 32 clocks wide
endmodule
| 7.338956 |
module stretcher #(
parameter count = 0,
parameter high_count = count,
parameter low_count = count
) (
input enable,
input in,
output reg out,
output reg valid,
input clock,
input reset
);
`include "functions.v"
// edge detector
wire rising;
wire falling;
assign rising = ~out & in;
assign falling = out & ~in;
/// counter width is the maximum size of the loaded value
parameter counter_width = max(flog2(high_count - 1) + 1, flog2(low_count - 1) + 1);
reg [counter_width:0] counter;
reg [counter_width-1:0] counter_load;
wire counter_overflow;
assign counter_overflow = counter[counter_width];
// select counter value for rising or falling edge
always @(rising, falling) begin
case ({
rising, falling
})
'b10: counter_load = ~(high_count - 1);
'b01: counter_load = ~(low_count - 1);
default: counter_load = {counter_width{1'bx}};
endcase
end
// the counter is reset on a rising or falling edge
// overflow has priority over reset, so input changes
// will be ignored until the full count is reached
always @(posedge clock, posedge reset) begin
if (reset) counter <= {counter_width{1'b0}};
else begin
if (enable & ~counter_overflow) counter <= counter + 1;
else if ((rising | falling) & counter_overflow) counter <= {1'b0, counter_load};
end
end
// output is gated by the counter overflow
always @(posedge clock, posedge reset) begin
if (reset) out <= 1'b0;
else if (counter_overflow) out <= in;
end
always @(posedge clock, posedge reset) begin
if (reset) valid <= 0;
else valid <= counter_overflow;
end
endmodule
| 7.985278 |
module StrichLuxIOSPI (
intf_en,
i2c_scl,
i2c_sda,
spi_sclk,
spi_n_ss,
spi_miso,
spi_mosi,
status_red,
status_grn,
intf_dir_miso,
intf_dir_mosi
);
output intf_en;
inout i2c_scl;
inout i2c_sda;
output spi_sclk;
output [1:0] spi_n_ss;
input spi_miso;
output spi_mosi;
output status_red;
output status_grn;
output intf_dir_miso;
output intf_dir_mosi;
wire n_reset;
wire clk_in;
wire tx_go;
wire tx_done;
wire [1:0] io_mode;
wire [7:0] rx_buffer;
wire [11:0] divisor;
wire [11:0] divisor_mgmt;
wire [11:0] divisor_in;
wire [11:0] divisor_out;
wire [7:0] tx_buffer;
wire [7:0] tx_buffer_mgmt;
wire [7:0] tx_buffer_in;
wire [7:0] tx_buffer_out;
`define IOMODE_MGMT 2'b00 // not yet initialized
`define IOMODE_IN 2'b01 // configured as input module
`define IOMODE_OUT 2'b10 // configured as output module
`define IOMODE_FAULT 2'b11 // fault, module halted
// needed only for simulation
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
// internal oscillator
OSCH #("19.0") osc (
.STDBY(1'b0),
.OSC(clk_in),
.SEDSTDBY()
);
assign n_reset = 1'b1; // we should pin this out eventually
assign intf_en = ~spi_n_ss_intf;
assign spi_n_ss[0] = spi_n_ss_core;
assign spi_n_ss[1] = spi_n_ss_intf;
// TODO: support bidi
assign intf_dir_mosi = 1'b1;
assign intf_dir_miso = 1'b0;
// MOSI muxes
MUX41 n_ss_intf_mux (
spi_n_ss_intf_mgmt,
spi_n_ss_intf_in,
spi_n_ss_intf_out,
spi_n_ss_intf_mgmt,
io_mode[0],
io_mode[1],
spi_n_ss_intf
);
Mux41 #(1) n_ss_core_mux (
clk_in,
io_mode,
spi_n_ss_core_mgmt,
spi_n_ss_core_in,
spi_n_ss_core_out,
spi_n_ss_core_mgmt,
spi_n_ss_core
);
// Mux41 #(1) n_ss_intf_mux (clk_in, io_mode, spi_n_ss_intf_mgmt, spi_n_ss_intf_in, spi_n_ss_intf_out, spi_n_ss_intf_mgmt, spi_n_ss_intf);
Mux41 #(12) divisor_mux (
clk_in,
io_mode,
divisor_mgmt,
divisor_in,
divisor_out,
divisor_mgmt,
divisor
);
Mux41 #(1) tx_go_mux (
clk_in,
io_mode,
tx_go_mgmt,
tx_go_in,
tx_go_out,
tx_go_mgmt,
tx_go
);
Mux41 #(8) tx_buffer_mux (
clk_in,
io_mode,
tx_buffer_mgmt,
tx_buffer_in,
tx_buffer_out,
tx_buffer_mgmt,
tx_buffer
);
IOSPITXInterface intf_spi_out (
clk_in,
n_reset,
divisor,
tx_go,
tx_done,
spi_sclk,
spi_miso,
spi_mosi,
tx_buffer,
rx_buffer
);
IOSPIManagementController ctl_mgmt (
clk_in,
n_reset,
divisor_mgmt,
tx_go_mgmt,
tx_done,
spi_n_ss_core_mgmt,
spi_n_ss_intf_mgmt,
tx_buffer_mgmt,
rx_buffer,
io_mode,
status_grn,
status_red
);
IOSPIOutputController ctl_out (
clk_in,
n_reset,
divisor_out,
tx_go_out,
tx_done,
spi_n_ss_core_out,
spi_n_ss_intf_out,
tx_buffer_out,
rx_buffer
);
endmodule
| 7.766096 |
module strict_rank #(
parameter FLOW_ID_WIDTH = 16,
parameter RANK_WIDTH = 16,
parameter META_WIDTH = 16
) (
input rst,
input clk,
output reg busy,
input insert,
input [ META_WIDTH-1:0] meta_in,
input [FLOW_ID_WIDTH-1:0] flowID_in,
input remove,
output reg valid_out,
output [ RANK_WIDTH-1:0] rank_out,
output [ META_WIDTH-1:0] meta_out
);
//----------- localparams -------------
localparam L2_MAX_DEPTH = 4; // 16 entries in FIFO
//----------- wires and regs -------------
reg [META_WIDTH-1:0] fifo_meta_in;
reg fifo_wr_en;
reg fifo_rd_en;
wire fifo_nearly_full;
wire fifo_empty;
//----------- modules and logic -------------
fallthrough_small_fifo #(
.WIDTH(RANK_WIDTH + META_WIDTH),
.MAX_DEPTH_BITS(L2_MAX_DEPTH)
) rank_fifo (
.din ({flowID_in, meta_in}), // Data in
.wr_en (fifo_wr_en), // Write enable
.rd_en (fifo_rd_en), // Read the next word
.dout ({rank_out, meta_out}),
.full (),
.prog_full (),
.nearly_full(fifo_nearly_full),
.empty (fifo_empty),
.reset (rst),
.clk (clk)
);
// Insertion Logic
always @(*) begin
busy = fifo_nearly_full;
if (insert) begin
fifo_wr_en = 1;
end else begin
fifo_wr_en = 0;
end
end
// Removal Logic
always @(*) begin
valid_out = ~fifo_empty;
if (remove) begin
fifo_rd_en = 1;
end else begin
fifo_rd_en = 0;
end
end
endmodule
| 7.871378 |
module stridyULTIMATE (
add,
strobe,
ready,
clk,
out
);
input wire [11:0] add;
input wire clk;
input wire strobe;
output reg ready;
output reg out;
reg enable;
reg [15:0] counter;
reg [15:0] period;
parameter ready_shift1 = 5'b00000;
parameter shift1 = 5'b00001;
parameter ready_shift0 = 5'b00010;
parameter shift0 = 5'b00011;
parameter ready_intr0 = 5'b00100;
parameter intr0 = 5'b00101;
parameter ready_intr1 = 5'b00110;
parameter intr1 = 5'b00111;
parameter gucci = 5'b01000;
parameter send_intr = 5'b01001;
parameter pre_shift1 = 5'b01010;
parameter pre_shift0 = 5'b01011;
parameter pre_intr0 = 5'b01100;
parameter pre_intr1 = 5'b01101;
parameter mid_shift1 = 5'b01110;
parameter mid_shift0 = 5'b01111;
parameter mid_intr0 = 5'b10000;
parameter mid_intr1 = 5'b10001;
reg [3:0] state = gucci;
always @(negedge clk) begin
case (state)
gucci: //IDLE
begin
ready <= 1'bz;
out <= 1;
counter <= 0;
if ((add[11:0] == 12'h10d) && (~strobe)) begin //enable
enable <= 1;
state <= pre_intr1;
end else if ((add[11:0] == 12'h10c) && (~strobe)) begin //disable
enable <= 0;
state <= pre_intr0;
end else if ((add[11:0] == 12'h10e) && (~strobe)) begin //shift 0
period <= period << 1;
period[0] <= 0;
state <= pre_shift0;
end else if ((add[11:0] == 12'h10f) && (~strobe)) begin //shift 1
period <= period << 1;
period[0] <= 1;
state <= pre_shift1;
end
end
pre_shift1: begin
state <= mid_shift1;
end
mid_shift1: begin
state <= shift1;
end
shift1: begin
ready <= 1'b0;
state <= ready_shift1;
end
ready_shift1: begin
ready <= 1'b1;
state <= gucci;
end
pre_shift0: begin
state <= mid_shift0;
end
mid_shift0: begin
state <= shift0;
end
shift0: begin
ready <= 1'b0;
state <= ready_shift0;
end
ready_shift0: begin
ready <= 1'b1;
state <= gucci;
end
pre_intr1: begin
//counter <= counter + 1;
//if(counter == period) begin
// counter <= 0;
// state <= send_intr;
//end
//else begin
state <= mid_intr1;
//end
end
mid_intr1: begin
state <= intr1;
end
intr1: begin
ready <= 1'b0;
state <= ready_intr1;
end
ready_intr1: begin
ready <= 1'b1;
state <= gucci;
end
//send_intr:
// begin
// out <= 0;
// //ready <= 1'b1;
// //state <= gucci;
// state <= intr1;
// end
pre_intr0: begin
//enable <= 0;
//out <= 1;
state <= intr0;
end
//mid_intr0:
// begin
// state <= intr0;
// end
intr0: begin
ready <= 1'b0;
state <= ready_intr0;
end
ready_intr0: begin
ready <= 1'b1;
state <= gucci;
end
endcase
if (enable) begin
counter <= counter + 1;
end
if (counter == period) begin
counter <= 0;
out <= 0;
//state = gucci;
end else begin
out <= 1;
end
end
endmodule
| 7.392158 |
module tb_string2;
// string2 Parameters
parameter PERIOD = 10;
// string2 Inputs
reg clk = 0;
reg clr = 0;
reg [7:0] in = 0;
// string2 Outputs
wire out;
string2 u_string2 (
.clk(clk),
.clr(clr),
.in (in[7:0]),
.out(out)
);
always #5 clk = ~clk;
initial begin
$dumpfile("test.vcd");
$dumpvars;
clk = 0;
clr = 0;
in = "1";
#2 clr = 0;
#8 in = "+";
#10 in = "(";
#10 in = "1";
#10 in = "+";
#10 in = "2";
#10 in = "*";
#10 in = "1";
#10 in = "+";
#10 in = "2";
#10 in = ")";
#10 in = "*";
#10 in = "(";
#10 in = "3";
#10 in = ")";
#10;
$finish;
end
endmodule
| 6.90129 |
module strings();
// Declare a register variable that is 21 bytes
reg [8*21:0] string ;
initial begin
string = "This is sample string";
$display ("%s \n", string);
end
endmodule
| 7.214605 |
module stringToInt (
output [23:0] s,
input [ 3:0] a6,
input [ 3:0] a5,
input [ 3:0] a4,
input [ 3:0] a3,
input [ 3:0] a2,
input [ 3:0] a1
);
wire [23:0] a6v = a6 * 24'd100000;
wire [23:0] a5v = a5 * 24'd10000;
wire [23:0] tmp1 = a6v + a5v;
wire [23:0] a4v = a4 * 24'd1000;
wire [23:0] a3v = a3 * 24'd100;
wire [23:0] tmp2 = a4v + a3v;
wire [23:0] a2v = a2 * 24'd10;
wire [23:0] a1v = a1;
wire [23:0] tmp3 = a2v + a1v;
assign s = tmp1 + tmp2 + tmp3;
endmodule
| 6.62016 |
module bit_generator (
input wire rst_n, // Asynchronous reset (active low)
input wire clk, // Clock (rising edge)
input wire clear_n, // Synchronous reset (active low)
input wire tick, // 50ms tick input
input wire polarity, // Polarity of output signal
input wire bit_value, // Bit value
input wire valid, // Valid bit value (active high)
output reg ready, // Serial output
output reg sout // Serial output
);
localparam val_p = 5'b11000; //24
localparam val_1 = 5'b10000; //16
localparam val_0 = 5'b01000; // 8
reg [4:0] count;
reg dbit;
reg polar;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
count <= val_p;
ready <= 1'b0;
dbit <= 1'b0;
polar <= 1'b0;
sout <= 1'b0;
end else begin
if (clear_n == 1'b0) begin
count <= val_p;
ready <= 1'b0;
dbit <= 1'b0;
polar <= 1'b0;
sout <= 1'b0;
end else begin
if (tick == 1'b1) begin
if (count[4:3] == 2'b11) begin
if (valid == 1'b1) begin
count <= 5'b00000;
dbit <= bit_value;
polar <= polarity;
end
end else begin
count <= count + 1'b1;
end
end
if ((tick == 1'b1) && (count[4:3] == 2'b11) && (valid == 1'b1)) begin
ready <= 1'b1;
end else begin
ready <= 1'b0;
end
if (((dbit == 1'b0) && ((count[4] == 1'b1) || (count[3] == 1'b1))) ||
((dbit == 1'b1) && (count[4] == 1'b1) ) ) begin
sout <= polar;
end else begin
sout <= ~polar;
end
end
end
end
endmodule
| 7.004441 |
module string_led_controller_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [15:0] errorbits;
reg [7:0] cmd_addr;
reg [7:0] cmd_data;
assign checkbits = mprj_io[31:16];
assign errorbits = mprj_io[15:0];
assign (pull1, pull0) mprj_io[37:0] = 38'b11111111111111111111111111111111111111;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("string_led_controller.vcd");
$dumpvars(0, string_led_controller_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (7000) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
`else
$display("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
wait (checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
wait (checkbits == 16'hAB61);
if (errorbits == 16'h0000) begin
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Passed");
`else
$display("Monitor: Mega-Project WB (RTL) Passed");
`endif
end else begin
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Failed [0x%h errors]", errorbits);
`else
$display("Monitor: Mega-Project WB (RTL) Failed [0x%h errors]", errorbits);
`endif
end
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#100000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("string_led_controller.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.904792 |
module string_rom #(
parameter A_WIDTH = 13,
parameter D_WIDTH = 16,
parameter INIT_FILE = "2.mif"
) (
clock,
address,
q
);
input [A_WIDTH-1:0] address;
input clock;
output [D_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [D_WIDTH-1:0] sub_wire0;
wire [D_WIDTH-1:0] q = sub_wire0[D_WIDTH-1:0];
altsyncram altsyncram_component (
.address_a(address),
.clock0(clock),
.q_a(sub_wire0),
.aclr0(1'b0),
.aclr1(1'b0),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({D_WIDTH{1'b1}}),
.data_b(1'b1),
.eccstatus(),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
);
defparam altsyncram_component.address_aclr_a = "NONE", altsyncram_component.clock_enable_input_a =
"BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = INIT_FILE, altsyncram_component.intended_device_family =
"Cyclone V", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 2 ** A_WIDTH,
altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.widthad_a = A_WIDTH,
altsyncram_component.width_a = D_WIDTH, altsyncram_component.width_byteena_a = 1;
endmodule
| 6.714194 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.FRAME_BITS(16),
.DELAY(3)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module painter24 (
input clk,
input reset,
input [15:0] frame,
input [ 7:0] subframe,
input [ 5:0] x,
input [ 5:0] y,
output [23:0] rgb24
);
reg [7:0] hue1;
reg [5:0] yy1;
always @(posedge clk) begin
hue1 <= frame[2+:8] - x[5:1];
yy1 <= y + frame[0+:6] + x;
end
reg [7:0] hue;
reg [5:0] yy;
reg [4:0] dim;
always @(posedge clk) begin
hue <= hue1;
yy <= yy1;
dim <= yy1[5] ? 31 - yy1[4:0] : yy1[4:0];
end
// wire [7:0] hue = frame[2+:8] - x[5:1];
// wire [5:0] yy = y + frame[0+:6] + x;
// wire [4:0] dim = yy[5] ? 31 - yy[4:0] : yy[4:0];
reg [2:0] schan, gchan; // color channels that are solid, gradient.
reg [4:0] sdist, gdist;
reg in_stripe;
always @(posedge clk) begin
// in_stripe <= x[1:0] == 0;
// in_stripe <= (x[2:1] - frame[3:2]) != 0;
// in_stripe <= 1;
in_stripe <= (x[2:0] - frame[2:0]) != 0;
sdist <= 5'b11111;
case (hue[7:5])
0: begin
schan <= 3'b000;
gchan <= 3'b001;
gdist <= hue[4:0];
end
1: begin
schan <= 3'b001;
gchan <= 3'b010;
gdist <= hue[4:0];
end
2: begin
schan <= 3'b010;
gchan <= 3'b001;
gdist <= 31 - hue[4:0];
end
3: begin
schan <= 3'b010;
gchan <= 3'b100;
gdist <= hue[4:0];
end
4: begin
schan <= 3'b110;
gchan <= 3'b001;
gdist <= hue[4:0];
end
5: begin
schan <= 3'b101;
gchan <= 3'b010;
gdist <= 31 - hue[4:0];
end
6: begin
schan <= 3'b100;
gchan <= 3'b001;
gdist <= 31 - hue[4:0];
end
7: begin
schan <= 3'b000;
gchan <= 3'b100;
gdist <= 31 - hue[4:0];
end
endcase
end
wire [4:0] ssdist = sdist < dim ? 0 : sdist - dim;
wire [4:0] ggdist = gdist < dim ? 0 : gdist - dim;
wire [7:0] solid, grad;
assign solid = {ssdist[4:0], ssdist[4:2]};
assign grad = {ggdist[4:0], ggdist[4:2]};
// assign solid = {3'b0, sdist[4:0]};
// assign grad = {3'b0, gdist[4:0]};
reg [7:0] red, green, blue;
always @(posedge clk) begin
red <= in_stripe ? gchan[0] ? grad : (schan[0] ? solid : 0) : 0;
green <= in_stripe ? gchan[1] ? grad : (schan[1] ? solid : 0) : 0;
blue <= in_stripe ? gchan[2] ? grad : (schan[2] ? solid : 0) : 0;
end
assign rgb24 = {blue, green, red};
endmodule
| 6.846537 |
module stripes (
input clk,
input reset,
output vga_clk,
output vga_hs,
output vga_vs,
output valid,
output [3:0] vga_r,
output [3:0] vga_g,
output [3:0] vga_b
);
reg [11:0] vga_data;
wire [9:0] h_addr, v_addr;
parameter h_width = 640;
parameter v_width = 480;
clkgen #(
.clk_freq(25000000)
) my_vgaclk (
.clkin(clk),
.rst(reset),
.clken(1'b1),
.clkout(vga_clk)
);
vga_ctrl v1 (
.pclk(vga_clk), //25MHz 时钟
.reset(reset), // 置位
.vga_data(vga_data), // 上层模块提供的VGA 颜色数据
.h_addr(h_addr), // 提供给上层模块的当前扫描像素点坐标
.v_addr(v_addr),
.hsync(vga_hs), // 行同步和列同步信号
.vsync(vga_vs),
.valid(valid), // 消隐信号
.vga_r(vga_r), // 红绿蓝颜色信号
.vga_g(vga_g),
.vga_b(vga_b)
);
initial begin
vga_data = 0;
end
always @(posedge clk) begin
if (v_addr < 80 || (v_addr >= 240 && v_addr < 320)) vga_data <= 12'hF00;
else if ((v_addr >= 80 && v_addr < 160) || (v_addr >= 320 && v_addr < 400)) vga_data <= 12'h0F0;
else if ((v_addr >= 160 && v_addr < 240) || (v_addr >= 400 && v_addr < 480))
vga_data <= 12'h00F;
else vga_data <= 12'h0;
end
endmodule
| 7.220219 |
module strip_headers #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter IOQ_STAGE_NUM = `IO_QUEUE_STAGE_NUM
) ( // --- data path interface
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [ `UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [ UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [ `UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [ UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2 = 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
//---------------------- Wires/Regs -------------------------------
reg in_pkt;
reg full;
wire keep_data;
//----------------------- Modules ---------------------------------
// Work out whether we should forward the data
//
// We should only keep data if we're already in a packet, if the packet
// is just beginning or we're in the IOQ STAGE NUM header
assign keep_data = in_pkt || in_ctrl == 'h0 || in_ctrl == IOQ_STAGE_NUM;
always @(posedge clk) begin
if (reset) begin
in_pkt <= 1'b0;
full <= 1'b0;
out_wr <= 1'b0;
end else begin
if (full) begin
// If the output is ready and we have an item of data, sent it to
// the output
out_wr <= out_rdy;
full <= !out_rdy;
end else if (in_wr) begin
// Store the data if there's a write on the input
out_ctrl <= in_ctrl;
out_data <= in_data;
// If the output is ready then send the data there, otherwise`
if (out_rdy) begin
out_wr <= keep_data;
full <= 1'b0;
end else begin
out_wr <= 1'b0;
full <= keep_data;
end
// Work out whether we're in a packet
if (!in_pkt && in_ctrl == 'h0) in_pkt <= 1'b1;
else if (in_pkt && |in_ctrl) in_pkt <= 1'b0;
end else begin
out_wr <= 1'b0;
end
end
end
// Only accept data if the output is ready and we're not full
// (If we're full we've got to wait a cycle to give the data to the output)
assign in_rdy = out_rdy && !full;
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
endmodule
| 7.339643 |
module dflip (
input clk,
input in,
output out
);
reg [2:0] d;
always @(posedge clk) d <= {d[1:0], in};
assign out = d[2];
endmodule
| 7.275243 |
module strobed_to_axi #(
parameter WIDTH = 32,
parameter FIFO_SIZE = 1
) (
input clk,
input reset,
input clear,
input in_stb,
input [WIDTH-1:0] in_data,
input in_last,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({in_last, in_data}),
.i_tvalid(in_stb),
.i_tready(),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
endmodule
| 7.32134 |
module strober (
input clk,
input rst_n,
output reg d
);
wire [5:0] q;
shift sh (
clk,
rst_n,
d,
q
);
always @(posedge clk, negedge rst_n)
if (!rst_n) d <= 1;
else d <= q[4];
endmodule
| 7.47356 |
module strobe_ctl (
input pclk,
input clk,
input i_obj_det,
input i_obj_det_trig,
output reg o_search_mode,
output o_en_strobe,
output reg o_en_engine,
input resetn
);
parameter EN_SEQ = 1'b0;
reg [3:0] det_cnt;
reg [3:0] undet_cnt;
reg [3:0] skip_cnt;
reg r_en_engine;
assign o_en_strobe = (skip_cnt == 4'b0) | (!o_search_mode);
always @(posedge pclk or negedge resetn) begin
if (resetn == 1'b0) o_search_mode <= 1'b1;
else if (det_cnt == 4'd4) o_search_mode <= 1'b0;
else if (undet_cnt == 4'hf) o_search_mode <= 1'b1;
end
always @(posedge pclk or negedge resetn) begin
if (resetn == 1'b0) r_en_engine <= 1'b0;
else if (det_cnt == (EN_SEQ ? 4'd8 : 4'd4)) r_en_engine <= 1'b1;
else if (undet_cnt == 4'hf) r_en_engine <= 1'b0;
end
always @(posedge clk) begin
o_en_engine <= r_en_engine;
end
always @(posedge pclk or negedge resetn) begin
if (resetn == 1'b0) skip_cnt <= 4'b0;
else if (i_obj_det_trig)
skip_cnt <= i_obj_det ? 4'b0 : (skip_cnt == 4'b0) ? 4'd10 : (skip_cnt - 4'd1);
end
always @(posedge pclk or negedge resetn) begin
if (resetn == 1'b0) det_cnt <= 4'b0;
else if (i_obj_det_trig) det_cnt <= (!i_obj_det) ? 4'h0 : (det_cnt + {3'b0, (det_cnt != 4'hf)});
end
always @(posedge pclk or negedge resetn) begin
if (resetn == 1'b0) undet_cnt <= 4'b0;
else if (i_obj_det_trig)
undet_cnt <= i_obj_det ? 4'h0 : (undet_cnt + {3'b0, (undet_cnt != 4'hf)});
end
endmodule
| 6.569343 |
module strobe_gen (
input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe
);
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if (reset | ~enable) counter <= #1 8'd0;
else if (strobe_in)
if (counter == 0) counter <= #1 rate;
else counter <= #1 counter - 8'd1;
endmodule
| 7.56518 |
module strobe_gen_1K_10_5_1 #(
parameter INPUT_FREQUENCY_KHZ = 10000
) (
input CLK,
output STB_1K,
STB_10,
STB_5,
STB_1
);
reg [6:0] cnt10;
reg [2:0] cnt5;
reg [3:0] cnt1;
reg [15:0] prescaler;
reg stb_1k;
reg stb_10, stb_5, stb_1;
wire cnt10_done = (cnt10 == 99);
wire cnt5_done = (cnt5 == 4);
wire cnt1_done = (cnt1 == 9);
assign STB_1K = stb_1k, STB_10 = stb_10, STB_5 = stb_5, STB_1 = stb_1;
// we must perform initial reset, for the correct RTL simulaion
initial begin
cnt10 = 0;
cnt5 = 0;
cnt1 = 0;
end
// prescaler downto 1kHz
always @(posedge CLK)
if (prescaler == 0) begin
stb_1k <= 1;
prescaler <= INPUT_FREQUENCY_KHZ - 1;
end else begin
stb_1k <= 0;
prescaler--;
end
always @(posedge CLK)
if (stb_1k) begin
if (cnt10_done) cnt10 <= 0;
else cnt10 <= cnt10 + 1;
stb_10 <= (cnt10_done);
stb_5 <= ((cnt5_done) & (stb_10));
stb_1 <= ((cnt1_done) & (stb_10));
end
always @(posedge CLK)
if (stb_10) begin
if (cnt5_done) cnt5 <= 0;
else cnt5 <= cnt5 + 1;
if (cnt1_done) cnt1 <= 0;
else cnt1 <= cnt1 + 1;
end
endmodule
| 6.923864 |
module strobe_gen_1k_50_5_1 #(
parameter INPUT_FREQUENCY_KHZ = 10000
) (
input CLK,
output STB_1K,
STB_50,
STB_5,
STB_1
);
reg [4:0] cnt50;
reg [3:0] cnt5;
reg [6:0] cnt1;
reg [15:0] prescaler;
reg stb_1k;
reg stb_50, stb_5, stb_1;
wire cnt50_done = (cnt50 == 19);
wire cnt5_done = (cnt5 == 9);
wire cnt1_done = (cnt1 == 49);
assign STB_1K = stb_1k, STB_50 = stb_50, STB_5 = stb_5, STB_1 = stb_1;
// we must perform initial reset, for the correct RTL simulaion
initial begin
cnt50 = 0;
cnt5 = 0;
cnt1 = 0;
end
// prescaler downto 1kHz
always @(posedge CLK)
if (prescaler == 0) begin
stb_1k <= 1;
prescaler <= INPUT_FREQUENCY_KHZ - 1;
end else begin
stb_1k <= 0;
prescaler--;
end
always @(posedge CLK)
if (stb_1k) begin
if (cnt50_done) cnt50 <= 0;
else cnt50 <= cnt50 + 1;
stb_50 <= (cnt50_done);
stb_5 <= ((cnt5_done) & (stb_50));
stb_1 <= ((cnt1_done) & (stb_50));
end
always @(posedge CLK)
if (stb_50) begin
if (cnt5_done) cnt5 <= 0;
else cnt5 <= cnt5 + 1;
if (cnt1_done) cnt1 <= 0;
else cnt1 <= cnt1 + 1;
end
endmodule
| 7.195277 |
module strobe_gen_1k_50_5_1 #(
parameter INPUT_FREQUENCY_KHZ = 10000
) (
input wire CLK,
output wire STB_1K,
STB_50,
STB_5,
STB_1
);
localparam CNT_50_INIT = 20;
localparam CNT_5_INIT = 10;
localparam CNT_1_INIT = 50;
reg [4:0] cnt50;
reg [3:0] cnt5;
reg [6:0] cnt1;
reg [14:0] prescaler;
reg stb_1k;
reg stb_50, stb_5, stb_1;
wire cnt50_done = (cnt50 == 0);
wire cnt5_done = (cnt5 == 0);
wire cnt1_done = (cnt1 == 0);
assign STB_1K = stb_1k, STB_50 = stb_50, STB_5 = stb_5, STB_1 = stb_1;
// perform initial reset, for the correct RTL simulaion
initial begin
prescaler = 0;
cnt50 = 0;
cnt5 = 0;
cnt1 = 0;
end
// prescaler downto 1kHz
always @(posedge CLK)
if (prescaler == 0) begin
stb_1k <= 1;
prescaler <= INPUT_FREQUENCY_KHZ - 1;
end else begin
stb_1k <= 0;
prescaler <= prescaler - 1;
end
always @(posedge CLK)
if (stb_1k) begin
if (cnt50_done) cnt50 <= CNT_50_INIT - 1;
else cnt50 <= cnt50 - 1;
end
always @(posedge CLK)
if (stb_50) begin
if (cnt5_done) cnt5 <= CNT_5_INIT - 1;
else cnt5 <= cnt5 - 1;
if (cnt1_done) cnt1 <= CNT_1_INIT - 1;
else cnt1 <= cnt1 - 1;
end
always @(posedge CLK) begin
stb_50 <= (cnt50_done && stb_1k);
stb_5 <= ((cnt5_done) & (stb_50));
stb_1 <= ((cnt1_done) & (stb_50));
end
endmodule
| 7.195277 |
module strobe_gen_tb;
parameter PERIOD = 15.6;
parameter GATE_PER = 512000;
reg clk;
reg rst;
reg gate_enable;
reg str_in;
wire str1, str2;
reg [15:0] cntr1, cntr2;
//strobe rate
reg [7:0] strobe_rate;
reg [3:0] delay;
reg d;
//initialize variables
initial begin
//divide by 10
strobe_rate <= 8'd9;
//reset signal for initialization
rst <= 1'b0;
rst <= #(2 * PERIOD) 1'b1;
rst <= #(4 * PERIOD) 1'b0;
//strobe in signal
str_in <= 1'b0;
str_in <= #(30 * PERIOD) 1'b1;
end
//generate clock
initial begin
clk = 1'b1;
forever begin
//d = PERIOD/2;
// + $random%(3);
clk = #(PERIOD / 2 + $random % (0.4)) ~clk;
end
end
/*
generate gate_enable
*/
initial begin
gate_enable = 1'b0;
#(100) forever gate_enable = #(GATE_PER + $random % (100)) ~gate_enable;
end
//produce output to view waveforms
initial begin
$dumpfile("strobe_gen_tb.lxt");
$dumpvars;
end
initial $display("\n Display strobe counts for each gate enable");
//run length
initial begin
#5000000 $finish;
end
always @(negedge clk) begin
if (rst) cntr1 <= 16'd0;
else if (gate_enable && str1) cntr1 <= cntr1 + 16'd1;
else if (~gate_enable) cntr1 <= 16'd0;
end
always @(negedge clk) begin
if (rst) cntr2 <= 16'd0;
else if (gate_enable && str2) cntr2 <= cntr2 + 16'd1;
else if (~gate_enable) cntr2 <= 16'd0;
end
always @(negedge gate_enable) begin
$display("counter = %d<-->%d", cntr1, cntr2);
end
strobe_gen dut1 (
.clock(clk),
.reset(rst),
.enable(gate_enable),
.rate(strobe_rate),
.strobe_in(str_in),
.strobe(str1)
);
/* -----\/----- EXCLUDED -----\/-----
strobe_gen_new
dut2(
.clock(clk),
.reset(rst),
.enable(gate_enable),
.rate(strobe_rate),
.strobe_in(str_in),
.strobe(str2)
);
-----/\----- EXCLUDED -----/\----- */
endmodule
| 7.325635 |
module strobe_out4 (
clk_in,
clk_out,
strobe_in,
strobe_out,
strobe_out_dup1,
strobe_out_dup2,
strobe_out_dup3,
data_in,
data_out
);
parameter WIDTH = 1;
parameter DELAY = 2; // 2 for metastability, larger for testing
input clk_in;
input clk_out;
input strobe_in;
output strobe_out;
output strobe_out_dup1;
output strobe_out_dup2;
output strobe_out_dup3;
input [WIDTH-1:0] data_in;
output [WIDTH-1:0] data_out;
reg strobe_out;
reg strobe_out_dup1;
reg strobe_out_dup2;
reg strobe_out_dup3;
`define CLOCK_CROSS
`ifdef CLOCK_CROSS
reg flag;
reg prev_strobe;
reg [DELAY:0] sync;
reg [WIDTH-1:0] data;
initial begin
flag = 0;
prev_strobe = 0;
sync[DELAY:0] = 0;
data[WIDTH-1:0] = 0;
end
// flip the flag and clock in the data when strobe is high
always @(posedge clk_in) begin
//if ((strobe_in && !prev_strobe)
//|| (!strobe_in && prev_strobe))
flag <= flag ^ strobe_in;
if (strobe_in) data <= data_in;
prev_strobe <= strobe_in;
end
// shift through a chain of flipflop to ensure stability
always @(posedge clk_out) sync <= {sync[DELAY-1:0], flag};
//assign strobe_out = sync[DELAY] ^ sync[DELAY-1];
always @(posedge clk_out) begin
strobe_out <= sync[DELAY-1] ^ sync[DELAY-2];
strobe_out_dup1 <= sync[DELAY-1] ^ sync[DELAY-2];
strobe_out_dup2 <= sync[DELAY-1] ^ sync[DELAY-2];
strobe_out_dup3 <= sync[DELAY-1] ^ sync[DELAY-2];
end
//synthesis attribute strobe_out preserve_signal true
//synthesis attribute strobe_out_dup1 preserve_signal true
//synthesis attribute strobe_out_dup2 preserve_signal true
//synthesis attribute strobe_out_dup3 preserve_signal true
//assign strobe_out = strobe_out_reg;
assign data_out = data;
`else
assign strobe_out = strobe_in;
assign data_out = data_in;
`endif
endmodule
| 8.187165 |
module dflip (
input clk,
input in,
output out
);
reg [2:0] d;
always @(posedge clk) d <= {d[1:0], in};
assign out = d[2];
endmodule
| 7.275243 |
module strobgen (
input clk_sys,
input ss11,
ss12,
ss13,
ss14,
ss15,
input ok$,
zw,
oken,
input mode,
step,
input strob_fp,
input strobb_fp,
output ldstate,
output got,
output strob1,
output strob1b,
output strob2,
output strob2b
);
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = zw & oken;
wire es1 = ss11 | (ss12 & ok$) | (ss13 & ok$) | ss14 | ss15;
wire has_strob2 = ss11 | ss12;
wire no_strob2 = ss13 | ss14 | ss15;
assign got = state == S_GOT;
assign strob1 = (state == S_ST1) | strob_fp;
assign strob1b = (state == S_ST1B) | strobb_fp;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
// * step jest uzbrajany jeśli MODE=1 i wystąpił STROB1
// * STEP zabrania przejścia do stanu STROB2 jeśli ss11 | ss12 (czyli jeśli jesteśmy w strob1 po którym jest strob2, to będziemy trzymać strob1)
// * STEP zabrania przejścia do stanu GOT jeśli ~(ss11 | ss12) (czyli jeśli jesteśmy w strob1 bez strob2, to będziemy trzymać strob1)
// * wciśnięcie STEP zeruje przerzutnik i CPU wykonuje krok (odpala się przejście do następnego stanu)
// * MODE=0 resetuje przerzutnik i trzyma go w takim stanie (czyli step nie działa przy MODE=0)
// * podsumowując: jeśli MODE=1, to podtrzymujemy bieżący stan STROB1 dopóki użytkownik nie wciśnie STOP
// STEP
reg lstep;
always @(posedge clk_sys) begin
lstep <= step;
end
wire step_trig = ~mode | (step & ~lstep);
// STROBS
reg [0:2] state;
always @(posedge clk_sys) begin
case (state)
// GOT
S_GOT: begin
if (es1) begin
state <= S_ST1;
end else begin
state <= S_GOTW;
end
end
S_GOTW: begin
if (es1) begin
state <= S_ST1;
end
end
// STROB1 front
S_ST1: begin
if (step_trig) state <= S_ST1B;
else state <= S_ST1W;
end
// STROB1 front (wait for STEP)
S_ST1W: begin
if (step_trig) state <= S_ST1B;
end
// STROB1 back
S_ST1B: begin
if (has_strob2) begin
state <= S_ST2;
end else if (no_strob2 & ~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
// STROB2 front
S_ST2: begin
state <= S_ST2B;
end
// STROB2 back
S_ST2B: begin
if (~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
// STROB2 back (wait for I/F operation to end)
S_PGOT: begin
if (~if_busy) begin
state <= S_GOT;
end
end
endcase
end
endmodule
| 7.190363 |
module StrOPP (
input wire [31:0] Instr_Str,
input wire [31:0] InstrNO_Str,
//--regfile
output reg [ 4:0] AR1_Str,
output reg [ 4:0] AR2_Str,
output reg WE,
//--ALU
output reg [15:0] Out_LOPP,
output reg s_z,
input wire clk
);
always @(posedge clk) begin
WE = 1'b0;
end
always @(Instr_Str, InstrNO_Str) begin
#1 Out_LOPP = Instr_Str[15:0];
AR1_Str = Instr_Str[25:21];
AR2_Str = Instr_Str[20:16];
s_z = 0;
WE = 1'b1;
end
endmodule
| 7.695437 |
module strToFloat2 (
input [47:0] buffer,
output [31:0] val
);
wire [3:0] a1, a2, a3, a4, a5, a6;
wire [7:0] i1, i2, i3, i4, i5, i6;
assign {i1, i2, i3, i4, i5, i6} = buffer;
charToInt c1 (
i1,
a1
);
charToInt c2 (
i2,
a2
);
charToInt c3 (
i3,
a3
);
charToInt c4 (
i4,
a4
);
charToInt c5 (
i5,
a5
);
charToInt c6 (
i6,
a6
);
wire [19:0] v1, v2, v3, v4, v5, v6;
assign v1 = a1 * 100 * 1000;
assign v2 = a2 * 10 * 1000;
assign v3 = a3 * 1000;
assign v4 = a4 * 100;
assign v5 = a5 * 10;
assign v6 = a6;
assign val = v1 + v2 + v3 + v4 + v5 + v6;
endmodule
| 7.045005 |
module charToInt (
input wire [7:0] c,
output reg [3:0] i
);
always @(c)
case (c)
8'h30: i = 0;
8'h31: i = 1;
8'h32: i = 2;
8'h33: i = 3;
8'h34: i = 4;
8'h35: i = 5;
8'h36: i = 6;
8'h37: i = 7;
8'h38: i = 8;
8'h39: i = 9;
endcase
endmodule
| 6.821406 |
module strt_check (
input wire sampled_bit,
input wire strt_check_en,
output reg strt_err
);
always @(*) begin
if (strt_check_en)
if (!sampled_bit) strt_err = 1'b0;
else strt_err = 1'b1;
else strt_err = 1'b0;
end
endmodule
| 7.224537 |
module strt_chk (
input wire CLK,
input wire RST,
input wire sampled_bit,
input wire Enable,
output reg strt_glitch
);
// error check
always @(posedge CLK or negedge RST) begin
if (!RST) begin
strt_glitch <= 'b0;
end else if (Enable) begin
strt_glitch <= sampled_bit;
end
end
endmodule
| 7.658506 |
module divideN #(
parameter integer WIDTH = 4
) (
input [WIDTH-1:0] X,
input [1:0] in,
output [WIDTH-1:0] Z,
output [1:0] out
);
wire [WIDTH-1:0][1:0] Yin, Yout;
divide1 g1[WIDTH-1:0] (
X,
Yin,
Z,
Yout
);
assign Yin[WIDTH-1] = in;
assign Yin[WIDTH-2:0] = Yout[WIDTH-1:1];
assign out = Yout[0];
endmodule
| 8.084833 |
module tb;
parameter integer WIDTH = 6;
reg [WIDTH-1:0] X = 6'b0;
reg [1:0] in = 2'b0;
wire [WIDTH-1:0] Z;
wire [1:0] out;
divideN #(
.WIDTH(WIDTH)
) g1 (
X,
in,
Z,
out
);
initial begin
repeat (63) #15 X = X + 1;
end
initial $monitor("X=%d, quotient=%d, remainder=%d @ time=%d", X, Z, out, $time);
endmodule
| 6.612288 |
module StructsCombinationalModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] In_Op1,
input wire [7:0] In_Op2,
output wire [7:0] Op1,
output wire [7:0] Sum,
output wire [7:0] OutDirect_Op1,
output wire [7:0] OutDirect_Op2,
output wire [7:0] OutInternal_Op1,
output wire [7:0] OutInternal_Op2,
output wire [7:0] OutSwapped_Op1,
output wire [7:0] OutSwapped_Op2,
output wire [7:0] OutMath_Op1,
output wire [7:0] OutMath_Op2,
output wire [7:0] Default1_Op1,
output wire [7:0] Default1_Op2,
output wire [7:0] Default2_Op1,
output wire [7:0] Default2_Op2
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [5:0] StructsModule_L35F52T54_Expr = 6'b101010;
wire [4:0] StructsModule_L11F27T29_Expr = 5'b10100;
wire [3:0] StructsModule_L10F27T29_Expr = 4'b1010;
wire [7:0] Inputs_In_Op1;
wire [7:0] Inputs_In_Op2;
wire [7:0] internalDirect_Op1;
wire [7:0] internalDirect_Op2;
wire [7:0] internalSum;
wire [7:0] StructsModule_L22F29T66_Cast;
wire [7:0] StructsModule_L31F19T56_Cast;
wire [7:0] StructsModule_L32F19T56_Cast;
wire [9:0] StructsModule_L22F36T65_Expr;
wire signed [9:0] StructsModule_L22F36T65_Expr_1;
wire signed [9:0] StructsModule_L22F36T65_Expr_2;
wire [9:0] StructsModule_L31F26T55_Expr;
wire signed [9:0] StructsModule_L31F26T55_Expr_1;
wire signed [9:0] StructsModule_L31F26T55_Expr_2;
wire signed [9:0] StructsModule_L32F26T55_Expr;
wire signed [9:0] StructsModule_L32F26T55_Expr_1;
wire signed [9:0] StructsModule_L32F26T55_Expr_2;
assign StructsModule_L22F36T65_Expr = StructsModule_L22F36T65_Expr_1 + StructsModule_L22F36T65_Expr_2;
assign StructsModule_L31F26T55_Expr = StructsModule_L31F26T55_Expr_1 + StructsModule_L31F26T55_Expr_2;
assign StructsModule_L32F26T55_Expr = StructsModule_L32F26T55_Expr_1 - StructsModule_L32F26T55_Expr_2;
assign StructsModule_L22F36T65_Expr_1 = {{2{1'b0}}, Inputs_In_Op1} /*expand*/;
assign StructsModule_L22F36T65_Expr_2 = {{2{1'b0}}, Inputs_In_Op2} /*expand*/;
assign StructsModule_L31F26T55_Expr_1 = {{2{1'b0}}, Inputs_In_Op1} /*expand*/;
assign StructsModule_L31F26T55_Expr_2 = {{2{1'b0}}, Inputs_In_Op2} /*expand*/;
assign StructsModule_L32F26T55_Expr_1 = {{2{1'b0}}, Inputs_In_Op1} /*expand*/;
assign StructsModule_L32F26T55_Expr_2 = {{2{1'b0}}, Inputs_In_Op2} /*expand*/;
assign Inputs_In_Op1 = In_Op1;
assign Inputs_In_Op2 = In_Op2;
assign internalDirect_Op1 = Inputs_In_Op1;
assign internalDirect_Op2 = Inputs_In_Op2;
assign StructsModule_L22F29T66_Cast = StructsModule_L22F36T65_Expr[7:0] /*truncate*/;
assign internalSum = StructsModule_L22F29T66_Cast;
assign Op1 = Inputs_In_Op1;
assign Sum = internalSum;
assign OutDirect_Op1 = Inputs_In_Op1;
assign OutDirect_Op2 = Inputs_In_Op2;
assign OutInternal_Op1 = internalDirect_Op1;
assign OutInternal_Op2 = internalDirect_Op2;
assign OutSwapped_Op1 = Inputs_In_Op2;
assign OutSwapped_Op2 = Inputs_In_Op1;
assign StructsModule_L31F19T56_Cast = StructsModule_L31F26T55_Expr[7:0] /*truncate*/;
assign StructsModule_L32F19T56_Cast = StructsModule_L32F26T55_Expr[7:0] /*truncate*/;
assign OutMath_Op1 = StructsModule_L31F19T56_Cast;
assign OutMath_Op2 = StructsModule_L32F19T56_Cast;
assign Default1_Op1 = {{2{1'b0}}, StructsModule_L35F52T54_Expr} /*expand*/;
assign Default1_Op2 = {{3{1'b0}}, StructsModule_L11F27T29_Expr} /*expand*/;
assign Default2_Op1 = {{4{1'b0}}, StructsModule_L10F27T29_Expr} /*expand*/;
assign Default2_Op2 = {{3{1'b0}}, StructsModule_L11F27T29_Expr} /*expand*/;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 6.769718 |
module mux_4to1 (
input [3:0] in, // Input Set @in: choose from 4 bits
input [1:0] sel, // Select @sel: 2^2 = 4 possible values
output o // Output @o: single bit from @in
);
assign o = (~sel[1] & ~sel[0] & in[0]) | // 2'b00 selects bit 0
(~sel[1] & sel[0] & in[1]) | // 2'b01 selects bit 1
(sel[1] & ~sel[0] & in[2]) | // 2'b10 selects bit 2
(sel[1] & sel[0] & in[3]); // 2'b11 selects bit 3
endmodule
| 6.772544 |
module 'Serial'.
//
////////////////////////////////////////////////////////////////////////////////
module Serial (Rx, Tx, PT, Clk, Rst, Result, ReadEn, WriteRy, WriteEn, ReadRy,
Key, ReadyKey, ProgramSelector) ;
input Rx;
output Tx;
output [127:0]PT;
input Clk;
input Rst;
input [127:0]Result;
input ReadEn;
output WriteRy;
input WriteEn;
output ReadRy;
output [127:0]Key;
output ReadyKey;
output ProgramSelector;
// EASE/HDL end ////////////////////////////////////////////////////////////////
endmodule
| 6.850012 |
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