code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module stream_buffer_2_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_02 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_2_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_12 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_2_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_22 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_2_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_32 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_3_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_03 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_3_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_13 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_3_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_23 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_3_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_33 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_4_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_04 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_4_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_14 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_4_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_24 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_4_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_34 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_5_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_05 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_5_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_15 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module stream_buffer_5_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_25 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_buffer_5_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_35 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module stream_cap #(
parameter SCR_SIZE_BIT
) (
input wire i_pxl_clk,
input wire i_reset_n,
// internal bus
input wire i_clk_bus,
input wire [ 4:0] i_addr,
input wire [ 7:0] i_data_wr,
input wire ... | 7.720136 |
module stream_collector #(
parameter NS = 2, // number of sources
parameter DW = 32 // data width
) (
// system
input wire clk, // clock
input wire clk_en, // clock enable
input wire rst, // reset
// input
input wire [N... | 6.965826 |
module
`timescale 1ns/1ns
module stream_cypher_tb;
reg clk;
reg rst;
reg en;
reg init;
reg [8*8-1:0] ck;
reg [8*8-1:0] sb;
wire [8*8-1:0] cb;
reg [24*8-1:0] tt; // input
initial
begin
// $read_data(
// "../test_dat/stream_cypher.in"
// ,tt
// ... | 6.608387 |
module stream_distributor #(
parameter NS = 2, // number of sinks
parameter DW = 32 // data width
) (
// system
input wire clk, // clock
input wire clk_en, // clock enable
input wire rst, // reset
// input
input wire in_vld, // inpu... | 6.719628 |
module stream_fifo #(
parameter AW = 8,
parameter DW = 8,
parameter USE_SHORTFIFO = 1
) (
input clk,
input [DW-1:0] d_in,
input d_in_valid,
input d_in_last,
output d_in_ready,
input d_out_ready,
output [DW-1:0] d_out,
output d_out_last,
output d_out_valid,
output fifo... | 7.864008 |
module stream_fifo_if #(
parameter DW = 0
) (
input clk,
input rst,
//FIFO Interface
input [DW-1:0] fifo_data_i,
output fifo_rd_en_o,
input fifo_empty_i,
//Stream Interface
output reg [DW-1:0] stream_m_data_o,
output reg stream_m_valid_o,
input stream_m_ready_i
);
reg ... | 6.889887 |
module stream_fifo_tb;
localparam DW = 16;
localparam AW = 4;
localparam WORDS = 4800;
vlog_tb_utils vtu ();
vlog_tap_generator #("stream_fifo.tap", 1) vtg ();
reg clk = 1'b1;
reg rst = 1'b1;
always #5 clk <= !clk;
initial #100 rst <= 1'b0;
wire [DW-1:0] dut_in_data;
wire dut_in_valid;
wire... | 6.635976 |
module Stream_Flow_Control #(
parameter PACKET_BITS = 97,
parameter NUM_LEAF_BITS = 6,
parameter NUM_PORT_BITS = 4,
parameter NUM_ADDR_BITS = 7,
parameter PAYLOAD_BITS = 64,
parameter NUM_IN_PORTS = 7,
parameter NUM_OUT_PORTS = 7,
parameter NUM_BRAM_ADDR_BITS = 7,
parameter FREESPACE... | 7.361273 |
module stream_master_v1_0 #(
// Users to add parameters here
parameter NUMBER_OF_OUTPUT_WORDS = 8,
parameter INITIAL_NUMBER = 1,
parameter ITERATION_NUMBER = 2,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M_AXIS
par... | 7.014447 |
module stream_reader #(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024
) (
input clk,
input [WIDTH-1:0] stream_s_data_i,
output reg stream_s_ready_o = 1'b0,
input stream_s_valid_i
);
real rate = 0.5;
integer seed = 0;
time ti... | 7.29683 |
module STREAM_REG (
ready_out,
valid_out,
data_out,
ready_in,
valid_in,
data_in,
clk,
rst_n
);
// Input Port(s)
input clk, rst_n;
input ready_in, valid_in;
input [DATA_WIDTH-1:0] data_in;
// Output Port(s)
output ready_out, valid_out;
output reg [DATA_WIDTH-1:0] data_out;... | 6.717989 |
module STREAM_REG_TEST (
input clk,
input reset_n,
input en_src,
input snk_ready,
output reg [7:0] src_data,
output [7:0] snk_data,
output reg [7:0] data_out,
output reg src_valid,
output reg_valid,
output reg_ready
);
always @(posedge clk) begin
if (~reset_n) begin
... | 6.819824 |
module stream_slave_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXIS
parameter integer C_S_AXIS_TDATA_WIDTH = 32
) (
// Users to add ports here
// User ports ends
// Do not... | 8.903427 |
module stream_writer #(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024
) (
input clk,
output reg [WIDTH-1:0] stream_m_data_o,
output reg stream_m_valid_o = 1'b0,
input stream_m_ready_i
);
real rate = 0.5;
integer seed = 0;
initial be... | 7.09698 |
module stretch (
input n, // 1 clock wide
output w, // 16 clocks wide (0.33 us @ 48 MHz)
input c // clock
);
// internal signals
reg t; // toggle FF
reg [15:0] d; // delay line
reg q; // output FF
// logic
always @(posedge c) begin
if (n) t <= ~t; // toggle on input pulse
d <= ... | 6.818439 |
module stretch32 (
input n, // 1 clock wide
output w, // 32 clocks wide (0.67 us @ 48 MHz)
input c // clock
);
// internal signals
reg t; // toggle FF
reg [31:0] d; // delay line
reg q; // output FF
// logic
always @(posedge c) begin
if (n) t <= ~t; // toggle on input pulse
d <... | 7.338956 |
module stretcher #(
parameter count = 0,
parameter high_count = count,
parameter low_count = count
) (
input enable,
input in,
output reg out,
output reg valid,
input clock,
input reset
);
`include "functions.v"
// edge detector
wire rising;
wire falling;
assign rising ... | 7.985278 |
module StrichLuxIOSPI (
intf_en,
i2c_scl,
i2c_sda,
spi_sclk,
spi_n_ss,
spi_miso,
spi_mosi,
status_red,
status_grn,
intf_dir_miso,
intf_dir_mosi
);
output intf_en;
inout i2c_scl;
inout i2c_sda;
output spi_sclk;
output [1:0] spi_n_ss;
input spi_miso;
output spi_m... | 7.766096 |
module strict_rank #(
parameter FLOW_ID_WIDTH = 16,
parameter RANK_WIDTH = 16,
parameter META_WIDTH = 16
) (
input rst,
input clk,
output reg busy,
input insert,
input [ META_WIDTH-1:0] ... | 7.871378 |
module stridyULTIMATE (
add,
strobe,
ready,
clk,
out
);
input wire [11:0] add;
input wire clk;
input wire strobe;
output reg ready;
output reg out;
reg enable;
reg [15:0] counter;
reg [15:0] period;
parameter ready_shift1 = 5'b00000;
parameter shift1 = 5'b00001;
parameter r... | 7.392158 |
module tb_string2;
// string2 Parameters
parameter PERIOD = 10;
// string2 Inputs
reg clk = 0;
reg clr = 0;
reg [7:0] in = 0;
// string2 Outputs
wire out;
string2 u_string2 (
.clk(clk),
.clr(clr),
.in (in[7:0]),
.out(out)
);
always #5 clk = ~clk... | 6.90129 |
module strings();
// Declare a register variable that is 21 bytes
reg [8*21:0] string ;
initial begin
string = "This is sample string";
$display ("%s \n", string);
end
endmodule
| 7.214605 |
module stringToInt (
output [23:0] s,
input [ 3:0] a6,
input [ 3:0] a5,
input [ 3:0] a4,
input [ 3:0] a3,
input [ 3:0] a2,
input [ 3:0] a1
);
wire [23:0] a6v = a6 * 24'd100000;
wire [23:0] a5v = a5 * 24'd10000;
wire [23:0] tmp1 = a6v + a5v;
wire [23:0] a4v = a4 * 24'd1000;
wi... | 6.62016 |
module bit_generator (
input wire rst_n, // Asynchronous reset (active low)
input wire clk, // Clock (rising edge)
input wire clear_n, // Synchronous reset (active low)
input wire tick, // 50ms tick input
input wire polarity, // Polarity of output signal
input wire bit_value, /... | 7.004441 |
module string_led_controller_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [15:0] errorbits;
reg [7:0] cmd_addr;
reg [7:0] cmd_data;
assign checkbits = mprj_io[31:16];
assign errorbits = mprj_io[15:0];
... | 6.904792 |
module string_rom #(
parameter A_WIDTH = 13,
parameter D_WIDTH = 16,
parameter INIT_FILE = "2.mif"
) (
clock,
address,
q
);
input [A_WIDTH-1:0] address;
input clock;
output [D_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RES... | 6.714194 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.FRAME_BITS(16),
.DELAY(3)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module painter24 (
input clk,
input reset,
input [15:0] frame,
input [ 7:0] subframe,
input [ 5:0] x,
input [ 5:0] y,
output [23:0] rgb24
);
reg [7:0] hue1;
reg [5:0] yy1;
always @(posedge clk) begin
hue1 <= frame[2+:8] - x[5:1];
yy1 <= y + frame[0+:6] + x... | 6.846537 |
module stripes (
input clk,
input reset,
output vga_clk,
output vga_hs,
output vga_vs,
output valid,
output [3:0] vga_r,
output [3:0] vga_g,
output [3:0] vga_b
);
reg [11:0] vga_data;
wire [9:0] h_addr, v_addr;
parameter h_width = 640;
parameter v_width = 480;
clkgen #(
... | 7.220219 |
module strip_headers #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter IOQ_STAGE_NUM = `IO_QUEUE_STAGE_NUM
) ( // --- data path interface
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg ... | 7.339643 |
module dflip (
input clk,
input in,
output out
);
reg [2:0] d;
always @(posedge clk) d <= {d[1:0], in};
assign out = d[2];
endmodule
| 7.275243 |
module strobed_to_axi #(
parameter WIDTH = 32,
parameter FIFO_SIZE = 1
) (
input clk,
input reset,
input clear,
input in_stb,
input [WIDTH-1:0] in_data,
input in_last,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
axi_fifo #(
.WID... | 7.32134 |
module strober (
input clk,
input rst_n,
output reg d
);
wire [5:0] q;
shift sh (
clk,
rst_n,
d,
q
);
always @(posedge clk, negedge rst_n)
if (!rst_n) d <= 1;
else d <= q[4];
endmodule
| 7.47356 |
module strobe_ctl (
input pclk,
input clk,
input i_obj_det,
input i_obj_det_trig,
output reg o_search_mode,
output o_en_strobe,
output reg o_en_engine,
input resetn
);
parameter EN_SEQ = 1'b0;
reg [3:0] det_cnt;
reg [3:0] undet_cnt;
reg [3:0] skip_cnt;
reg r_... | 6.569343 |
module strobe_gen (
input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe
);
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge... | 7.56518 |
module strobe_gen_1K_10_5_1 #(
parameter INPUT_FREQUENCY_KHZ = 10000
) (
input CLK,
output STB_1K,
STB_10,
STB_5,
STB_1
);
reg [6:0] cnt10;
reg [2:0] cnt5;
reg [3:0] cnt1;
reg [15:0] prescaler;
reg stb_1k;
reg stb_10, stb_5, stb_1;
wire cnt10_done = (cnt10 == 99);
wire cnt5_do... | 6.923864 |
module strobe_gen_1k_50_5_1 #(
parameter INPUT_FREQUENCY_KHZ = 10000
) (
input CLK,
output STB_1K,
STB_50,
STB_5,
STB_1
);
reg [4:0] cnt50;
reg [3:0] cnt5;
reg [6:0] cnt1;
reg [15:0] prescaler;
reg stb_1k;
reg stb_50, stb_5, stb_1;
wire cnt50_done = (cnt50 == 19);
wire cnt5_do... | 7.195277 |
module strobe_gen_1k_50_5_1 #(
parameter INPUT_FREQUENCY_KHZ = 10000
) (
input wire CLK,
output wire STB_1K,
STB_50,
STB_5,
STB_1
);
localparam CNT_50_INIT = 20;
localparam CNT_5_INIT = 10;
localparam CNT_1_INIT = 50;
reg [4:0] cnt50;
reg [3:0] cnt5;
reg [6:0] cnt1;
reg [14:0] ... | 7.195277 |
module strobe_gen_tb;
parameter PERIOD = 15.6;
parameter GATE_PER = 512000;
reg clk;
reg rst;
reg gate_enable;
reg str_in;
wire str1, str2;
reg [15:0] cntr1, cntr2;
//strobe rate
reg [7:0] strobe_rate;
reg [3:0] delay;
reg d;
//initialize variables
initial begin
//divide by 10
... | 7.325635 |
module strobe_out4 (
clk_in,
clk_out,
strobe_in,
strobe_out,
strobe_out_dup1,
strobe_out_dup2,
strobe_out_dup3,
data_in,
data_out
);
parameter WIDTH = 1;
parameter DELAY = 2; // 2 for metastability, larger for testing
input clk_in;
input clk_out;
input strobe_in;
outp... | 8.187165 |
module dflip (
input clk,
input in,
output out
);
reg [2:0] d;
always @(posedge clk) d <= {d[1:0], in};
assign out = d[2];
endmodule
| 7.275243 |
module strobgen (
input clk_sys,
input ss11,
ss12,
ss13,
ss14,
ss15,
input ok$,
zw,
oken,
input mode,
step,
input strob_fp,
input strobb_fp,
output ldstate,
output got,
output strob1,
output strob1b,
output strob2,
output strob2b
);
lo... | 7.190363 |
module StrOPP (
input wire [31:0] Instr_Str,
input wire [31:0] InstrNO_Str,
//--regfile
output reg [ 4:0] AR1_Str,
output reg [ 4:0] AR2_Str,
output reg WE,
//--ALU
output reg [15:0] Out_LOPP,
output reg s_z,
input wire clk
);
always @(posedge clk) ... | 7.695437 |
module strToFloat2 (
input [47:0] buffer,
output [31:0] val
);
wire [3:0] a1, a2, a3, a4, a5, a6;
wire [7:0] i1, i2, i3, i4, i5, i6;
assign {i1, i2, i3, i4, i5, i6} = buffer;
charToInt c1 (
i1,
a1
);
charToInt c2 (
i2,
a2
);
charToInt c3 (
i3,
a3
);
char... | 7.045005 |
module charToInt (
input wire [7:0] c,
output reg [3:0] i
);
always @(c)
case (c)
8'h30: i = 0;
8'h31: i = 1;
8'h32: i = 2;
8'h33: i = 3;
8'h34: i = 4;
8'h35: i = 5;
8'h36: i = 6;
8'h37: i = 7;
8'h38: i = 8;
8'h39: i = 9;
endcase
endmodule
... | 6.821406 |
module strt_check (
input wire sampled_bit,
input wire strt_check_en,
output reg strt_err
);
always @(*) begin
if (strt_check_en)
if (!sampled_bit) strt_err = 1'b0;
else strt_err = 1'b1;
else strt_err = 1'b0;
end
endmodule
| 7.224537 |
module strt_chk (
input wire CLK,
input wire RST,
input wire sampled_bit,
input wire Enable,
output reg strt_glitch
);
// error check
always @(posedge CLK or negedge RST) begin
if (!RST) begin
strt_glitch <= 'b0;
end else if (Enable) begin
strt_glitch <= sampled_bit;
... | 7.658506 |
module divideN #(
parameter integer WIDTH = 4
) (
input [WIDTH-1:0] X,
input [1:0] in,
output [WIDTH-1:0] Z,
output [1:0] out
);
wire [WIDTH-1:0][1:0] Yin, Yout;
divide1 g1[WIDTH-1:0] (
X,
Yin,
Z,
Yout
);
assign Yin[WIDTH-1] = in;
assign Yin[WIDTH-2:0] = Yout[WIDTH... | 8.084833 |
module tb;
parameter integer WIDTH = 6;
reg [WIDTH-1:0] X = 6'b0;
reg [1:0] in = 2'b0;
wire [WIDTH-1:0] Z;
wire [1:0] out;
divideN #(
.WIDTH(WIDTH)
) g1 (
X,
in,
Z,
out
);
initial begin
repeat (63) #15 X = X + 1;
end
initial $monitor("X=%d, quotient=%d, remainde... | 6.612288 |
module StructsCombinationalModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] In_Op1,
input wire [7:0] In_Op2,
output wire [7:0] Op1,
output wire [7:0] Sum,
output wire [7:0] OutDirect_Op1,
output wire [7:0] OutDirect_Op2,
output wire [7:0] OutInternal_Op... | 6.769718 |
module mux_4to1 (
input [3:0] in, // Input Set @in: choose from 4 bits
input [1:0] sel, // Select @sel: 2^2 = 4 possible values
output o // Output @o: single bit from @in
);
assign o = (~sel[1] & ~sel[0] & in[0]) | // 2'b00 selects bit 0
(~sel[1] & sel[0] & in[1]) | // 2'b01 select... | 6.772544 |
module 'Serial'.
//
////////////////////////////////////////////////////////////////////////////////
module Serial (Rx, Tx, PT, Clk, Rst, Result, ReadEn, WriteRy, WriteEn, ReadRy,
Key, ReadyKey, ProgramSelector) ;
input Rx;
output Tx;
output [127:0]PT;
input Clk;
input Rst;
input... | 6.850012 |
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