code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sa_invg0_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.565695 |
module sa_invg2_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.991532 |
module sa_invg2_hs_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.953226 |
module sa_invg4_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.785098 |
module sa_invg4_hs_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.723796 |
module sa_invg8_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.925965 |
module sa_invg0_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.836603 |
module sa_invg1_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.679472 |
module sa_invg2_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 7.230001 |
module sa_invg2_hs_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 7.211957 |
module sa_invg4_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 7.010978 |
module sa_invg4_hs_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 6.984739 |
module sa_invg8_elvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = ~in;
endmodule
| 7.053337 |
module sa_buf00_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = in;
endmodule
| 6.637552 |
module sa_buf01_ulvt (
in,
out,
vccesa,
vssesa
);
input in;
output out;
input vssesa;
input vccesa;
assign out = in;
endmodule
| 6.589459 |
module sa_nd2g1_ulvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb);
endmodule
| 6.530992 |
module sa_nd4g1_ulvt (
out,
ina,
inb,
inc,
ind,
vccesa,
vssesa
);
output out;
input ind;
input inc;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb && inc && ind);
endmodule
| 6.978971 |
module sa_nd2g1_elvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb);
endmodule
| 6.806982 |
module sa_nd3g1_elvt (
out,
ina,
inb,
inc,
vccesa,
vssesa
);
output out;
input inc;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb && inc);
endmodule
| 6.517599 |
module sa_nd4g1_elvt (
out,
ina,
inb,
inc,
ind,
vccesa,
vssesa
);
output out;
input ind;
input inc;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb && inc && ind);
endmodule
| 7.155673 |
module sa_nr4g1_ulvt (
out,
ina,
inb,
inc,
ind,
vccesa,
vssesa
);
output out;
input ind;
input inc;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina || inb || inc || ind);
endmodule
| 6.539093 |
module sa_nr2g1_elvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina || inb);
endmodule
| 6.640782 |
module sa_nd2_hs_ulvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb);
endmodule
| 7.14809 |
module sa_nr2_hs_ulvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina || inb);
endmodule
| 6.629102 |
module sa_nd2_cl_ulvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ~(ina && inb);
endmodule
| 7.085788 |
module sa_xnr2_hs_ulvt (
out,
ina,
inb,
vccesa,
vssesa
);
output out;
input inb;
input vssesa;
input ina;
input vccesa;
assign out = ina ~^ inb;
endmodule
| 6.57474 |
module sa_xor2_hs_ulvt (
out,
outb,
ina_p,
ina_n,
inb_p,
inb_n,
vccesa,
vssesa
);
output out;
output outb;
input inb_p;
input inb_n;
input vssesa;
input ina_p;
input ina_n;
input vccesa;
// assign out = ((ina_p ~^ ~ina_n) && (inb_p ~^ ~inb_n )) ? ina_p ^ inb_p : 1'bx ;
// assign outb = ((ina_p ~^ ~ina_n) && (inb_p ~^ ~inb_n )) ? ~out : 1'bx ;
assign out = ina_p ^ inb_p;
assign outb = ~out;
endmodule
| 6.617739 |
module sa_frncnp_elvt (
q,
qn,
clk,
d,
nclr,
npre,
vccesa,
vssesa
);
output qn;
output q;
input nclr;
input npre;
input d;
input clk;
inout vssesa;
inout vccesa;
reg q;
always @(posedge clk or negedge nclr or negedge npre) begin
if (~nclr) q <= 1'b0;
else if (~npre) q <= 1'b1;
else q <= d;
end
assign qn = ~q;
endmodule
| 6.952674 |
module sa_frncnp_ulvt (
q,
qn,
clk,
d,
nclr,
npre,
vccesa,
vssesa
);
output qn;
output q;
input nclr;
input npre;
input d;
input clk;
inout vssesa;
inout vccesa;
reg q;
always @(posedge clk or negedge nclr or negedge npre) begin
if (~nclr) q <= 1'b0;
else if (~npre) q <= 1'b1;
else q <= d;
end
assign qn = ~q;
endmodule
| 6.988604 |
module sa_frnc_ulvt (
q,
clk,
d,
nclr,
vccesa,
vssesa
);
output q;
input nclr;
input d;
input clk;
inout vssesa;
inout vccesa;
reg q;
always @(posedge clk or negedge nclr) begin
if (~nclr) q <= 1'b0;
else q <= d;
end
endmodule
| 6.563189 |
module sa_frnc_ulvt_hp (
q,
clk,
d,
nclr,
vccesa,
vssesa
);
output q;
input nclr;
input d;
input clk;
inout vssesa;
inout vccesa;
reg q;
always @(posedge clk or negedge nclr) begin
if (~nclr) q <= 1'b0;
else q <= d;
end
endmodule
| 6.646194 |
module sa_sdff_1x (
out,
outb,
clk,
d,
vccesa,
vssesa
);
inout out;
inout outb;
input d;
input clk;
inout vssesa;
inout vccesa;
reg tmp;
always @(posedge clk) begin
tmp <= d;
end
assign out = (clk) ? tmp : 1'bz;
assign outb = (clk) ? ~tmp : 1'bz;
endmodule
| 6.838374 |
module sa_sdffrr_1x (
out,
outb,
clk,
d,
db,
rst_n,
vccesa,
vssesa
);
input rst_n;
output out;
output outb;
input d;
input clk;
inout vssesa;
input db;
inout vccesa;
reg out;
always @(posedge clk or negedge rst_n) begin
out <= (!rst_n) ? 1'b0 : ((db != d) ? d : 1'bx);
end
assign outb = ~out;
endmodule
| 7.151433 |
module sa_sdffrr_1x_tx (
out,
outb,
clk,
d,
db,
rst_n,
vccesa,
vssesa
);
input rst_n;
output out;
output outb;
input d;
input clk;
inout vssesa;
input db;
inout vccesa;
reg out;
always @(posedge clk or negedge rst_n) begin
out <= (!rst_n) ? 1'b0 : ((db != d) ? d : 1'bx);
end
assign outb = ~out;
endmodule
| 7.307304 |
module sa_sdffrr (
out,
outb,
clk,
d,
db,
rst_n,
vccesa,
vssesa
);
input rst_n;
output out;
output outb;
input d;
input clk;
inout vssesa;
input db;
inout vccesa;
reg out;
always @(posedge clk or negedge rst_n) begin
out <= (!rst_n) ? 1'b0 : ((db != d) ? d : 1'bx);
end
assign outb = ~out;
endmodule
| 6.857712 |
module sa_sdl_en_2x (
out,
outb,
clk,
d,
db,
en,
vccesa,
vssesa
);
inout out;
inout outb;
input d;
input en;
input clk;
inout vssesa;
input db;
inout vccesa;
reg tmp;
wire ck;
assign ck = clk & en;
always @(posedge ck) begin
tmp <= (db != d) ? d : 1'bx;
end
assign out = (ck) ? tmp : 1'bz;
assign outb = (ck) ? ~tmp : 1'bz;
endmodule
| 6.677941 |
module sa_triinv1_ulvt (
en,
in,
out,
vccesa,
vssesa
);
output out;
input in;
input en;
inout vssesa;
inout vccesa;
wire out;
assign out = (en) ? ~in : 1'bz;
endmodule
| 6.693355 |
module sa_triinv2_ulvt (
en,
in,
out,
vccesa,
vssesa
);
output out;
input in;
input en;
inout vssesa;
inout vccesa;
wire out;
assign out = (en) ? ~in : 1'bz;
endmodule
| 6.687273 |
module sa_triinv2_elvt (
en,
in,
out,
vccesa,
vssesa
);
output out;
input in;
input en;
inout vssesa;
inout vccesa;
wire out;
assign out = (en) ? ~in : 1'bz;
endmodule
| 6.767507 |
module sa_muxnd21_ulvt (
in0,
in1,
en0,
en1,
out,
vccesa,
vssesa
);
output out;
input in0;
input in1;
input en0;
input en1;
inout vssesa;
inout vccesa;
reg out;
always @(en0, en1, in0, in1)
case ({
en1, en0
})
2'b00: out = 1'b0;
2'b01: out = in0;
2'b10: out = in1;
2'b11: out = ~(~in1 && ~in0);
endcase
endmodule
| 6.535026 |
module sa_muxpas21_ulvt (
in0,
in1,
en0,
en1,
out,
vccesa,
vssesa
);
output out;
input in0;
input in1;
input en0;
input en1;
inout vssesa;
inout vccesa;
reg out;
always @(en0, en1, in0, in1)
case ({
en1, en0
})
2'b00: out = 1'bz;
2'b01: out = in0;
2'b10: out = in1;
default: out = 1'bx;
endcase
endmodule
| 7.535124 |
module sa_muxpas41_ulvt (
in0,
in1,
in2,
in3,
en0,
en1,
en2,
en3,
out,
vccesa,
vssesa
);
output out;
input in0;
input in1;
input in2;
input in3;
input en0;
input en1;
input en2;
input en3;
inout vssesa;
inout vccesa;
reg out;
always @(en0, en1, en2, en3, in0, in1, in2, in3)
case ({
en3, en2, en1, en0
})
4'b0000: out = 1'bz;
4'b0001: out = in0;
4'b0010: out = in1;
4'b0100: out = in2;
4'b1000: out = in3;
default: out = 1'bx;
endcase
endmodule
| 7.174528 |
module sa_muxtri21_ulvt (
in0,
in1,
en0,
en1,
out,
pd,
pdb,
vccesa,
vssesa
);
output out;
input in0;
input in1;
input en0;
input en1;
input pd;
input pdb;
inout vssesa;
inout vccesa;
wire out;
reg outb;
always @(en0, en1, in0, in1, pd, pdb)
case ({
pdb, pd
})
2'b00: outb = 1'b1;
2'b01: outb = 1'bx;
2'b10:
case ({
en1, en0
})
2'b00: outb = 1'bz;
2'b01: outb = ~in0;
2'b10: outb = ~in1;
2'b11: outb = 1'bx;
endcase
2'b11: outb = 1'b0;
endcase
assign out = ~outb;
endmodule
| 7.196954 |
module sa_muxtri31_ulvt (
in0,
in1,
in2,
en0,
en1,
en2,
out,
pd,
pdb,
vccesa,
vssesa
);
output out;
input in0;
input in1;
input in2;
input en0;
input en1;
input en2;
input pd;
input pdb;
inout vssesa;
inout vccesa;
wire out;
reg outb;
always @(en0, en1, en2, in0, in1, in2, pd, pdb)
case ({
pdb, pd
})
2'b00: outb = 1'b1;
2'b01: outb = 1'bx;
2'b10:
case ({
en2, en1, en0
})
3'b000: outb = 1'bz;
3'b001: outb = ~in0;
3'b010: outb = ~in1;
3'b100: outb = ~in2;
default: outb = 1'bx;
endcase
2'b11: outb = 1'b0;
endcase
assign out = ~outb;
endmodule
| 6.849143 |
module sa_muxtri41_ulvt (
in0,
in1,
in2,
in3,
en0,
en1,
en2,
en3,
out,
pd,
pdb,
vccesa,
vssesa
);
output out;
input in0;
input in1;
input in2;
input in3;
input en0;
input en1;
input en2;
input en3;
input pd;
input pdb;
inout vssesa;
inout vccesa;
wire out;
reg outb;
always @(en0, en1, en2, en3, in0, in1, in2, in3, pd, pdb)
case ({
pdb, pd
})
2'b00: outb = 1'b1;
2'b01: outb = 1'bx;
2'b10:
case ({
en3, en2, en1, en0
})
4'b0000: outb = 1'bz;
4'b0001: outb = ~in0;
4'b0010: outb = ~in1;
4'b0100: outb = ~in2;
4'b1000: outb = ~in3;
default: outb = 1'bx;
endcase
2'b11: outb = 1'b0;
endcase
assign out = ~outb;
endmodule
| 6.781912 |
module sa_txgate_ulvt (
en,
in,
out,
vccesa,
vssesa
);
output out;
input in;
input en;
inout vssesa;
inout vccesa;
wire out;
assign out = (en) ? in : 1'bz;
endmodule
| 7.033255 |
module sa_txgate_elvt (
en,
in,
out,
vccesa,
vssesa
);
output out;
input in;
input en;
inout vssesa;
inout vccesa;
wire out;
assign out = (en) ? in : 1'bz;
endmodule
| 7.112968 |
module: InstructionMemory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module struMem_TEST;
// Inputs
reg [31:0] address;
reg clock;
// Output
wire [31:0] inst;
always #10 clock <= ~clock;
always #10 address <= address + 32'b00000000000000000000000000000001;
// Instantiate the Unit Under Test (UUT)
InstructionMemory uut (
.address(address),
.clock(clock),
.inst(inst)
);
initial begin
// Initialize Inputs
address <= 32'h000000;
clock <= 0;
// Wait 100 ns for global reset to finish
#100 $finish;
// Add stimulus here
end
endmodule
| 6.522495 |
module Str_path (
input wire [31:0] Instr_Str,
input wire [31:0] InstrNO_Str,
input wire [31:0] R1_Str,
input wire [31:0] ROB_FAddr,
input wire ROB_FSAddr,
input wire [31:0] ROB_Fvalue,
input wire ROB_FSvalue,
output wire WE_AG,
output wire [ 4:0] AR1_Str,
output wire [31:0] StrAddr_AG,
output wire [ 4:0] AR2_Str,
input wire [31:0] R2_Str,
output wire [31:0] store_data_AG,
input wire clk
);
wire [15:0] Out_LOPP;
wire s_z;
wire [31:0] Add1;
wire [31:0] Add2;
StrOPP Str_OPP (
Instr_Str,
InstrNO_Str,
AR1_Str,
AR2_Str,
WE_AG,
Out_LOPP,
s_z,
clk
);
sign_zero_ext s_z_ext (
.in(Out_LOPP),
.out(Add1),
.modee(s_z)
);
mux2_1 Mux_ADDG (
.in_1(R1_Str),
.in_2(ROB_FAddr),
.sel (ROB_FSAddr),
.out (Add2)
);
mux2_1 Mux_Data (
.in_1(R2_Str),
.in_2(ROB_Fvalue),
.sel (ROB_FSvalue),
.out (store_data_AG)
);
assign StrAddr_AG = Add1 + Add2;
endmodule
| 6.82249 |
module STSystem_SR (
txclk,
ld,
st,
opn,
sp,
d,
TX
);
input wire txclk, ld, st, opn, sp; //
input wire [7:0] d;
output reg TX;
reg [0:10] loaddata;
always @(posedge txclk or negedge ld) begin
if (ld == 0) {loaddata} <= {st, d, opn, sp};
else {TX, loaddata} <= {loaddata, 1'b0};
end
endmodule
| 6.822879 |
module STSystem_DL (
pd,
d,
Q
);
input wire pd;
input wire [7:0] d;
output reg [7:0] Q;
always @(posedge pd) Q <= d;
endmodule
| 7.014565 |
module STSystem_Parity (
st,
d,
sp,
OPn
);
input wire st, sp;
input wire [7:0] d;
output wire OPn;
assign OPn = st ^ d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ sp;
endmodule
| 8.237254 |
module STSystem_TD (
clk,
send,
rst,
ack,
d,
RTS,
TX,
PD
);
input wire [0:7] d;
input wire clk, send, rst, ack;
output wire RTS, TX, PD;
wire txe, ld, clkout, opn;
wire [0:7] q;
STSystem_FSM FSM (
.clk(clk),
.send(send),
.txe(txe),
.rst(rst),
.ack(ack),
.PD(PD),
.LD(ld),
.CLKOUT(clkout),
.RTS(RTS)
);
STSystem_Counter Counter (
.clr (ld),
.txclk(clkout),
.TXE (txe)
);
STSystem_SR Shift_Register (
.txclk(clkout),
.ld(ld),
.st(0),
.opn(opn),
.sp(1),
.d(q),
.TX(TX)
);
STSystem_Parity Parity (
.st (0),
.d (d),
.sp (1),
.OPn(opn)
);
STSystem_DL DataLatch (
.pd(PD),
.d (d),
.Q (q)
);
endmodule
| 6.682609 |
module wtmiss_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = 1 + `mOp2_width;
localparam ADDR_WIDTH = 2;
localparam ADDR_COUNT = 4;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write_addr;
input [DATA_WIDTH-1:0] write_data;
input write_wen;
reg [DATA_WIDTH-1:0] ram[ADDR_COUNT-1:0];
reg [ADDR_WIDTH-1:0] read_addr_reg;
assign read_data = ram[read_addr_reg];
always @(posedge clk) begin
if (rst) read_addr_reg <= {ADDR_WIDTH{1'b0}};
else if (read_clkEn) read_addr_reg <= read_addr;
if (write_wen) ram[write_addr] <= write_data;
end
endmodule
| 8.089635 |
module ICP (
PAD,
PI,
GND5O,
GND5R,
VDD5O,
VDD5R,
CLAMPC,
PO,
Y
);
input PAD;
input PI;
input GND5O;
input GND5R;
input VDD5O;
input VDD5R;
input CLAMPC;
output PO;
output Y;
endmodule
| 7.276423 |
module BT4P (
A,
EN,
GND5O,
GND5R,
VDD5O,
VDD5R,
CLAMPC,
PAD
);
input A;
input EN;
input GND5O;
input GND5R;
input VDD5O;
input VDD5R;
input CLAMPC;
output PAD;
endmodule
| 6.953152 |
module GND5ALLPADP (
VDD5O,
VDD5R,
CLAMPC,
GND
);
input CLAMPC;
input VDD5O;
input VDD5R;
input GND;
endmodule
| 6.526082 |
module VDD5ALLPADP (
GND5O,
GND5R,
CLAMPC,
VDD
);
input CLAMPC;
input GND5O;
input GND5R;
input VDD;
endmodule
| 6.565591 |
module STypeSignExtend32b (
instruction,
signExtended
);
input wire [31:0] instruction;
output wire [31:0] signExtended;
SignExtend12To32 signExtend12To32_instance (
.from({instruction[31:25], instruction[11:7]}),
.to (signExtended)
);
endmodule
| 6.975449 |
module ST_Controler (
output reg e_ST_req,
w_ST_req,
n_ST_req,
s_ST_req,
eject_ST_req,
e_ack,
w_ack,
n_ack,
s_ack,
inject_ack,
input clk,
reset,
e_vc_alloc,
w_vc_alloc,
n_vc_alloc,
s_vc_alloc,
inject_vc_alloc,
oe_en,
ow_en,
on_en,
os_en,
Eject_en,
input [2:0] e_out,
w_out,
n_out,
s_out,
inject_out
);
always @(*) begin
if (reset) {e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
else begin
{e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
if (e_vc_alloc == 1) begin
case (e_out)
3'b000: e_ST_req = 1;
3'b001: w_ST_req = 1;
3'b010: n_ST_req = 1;
3'b011: s_ST_req = 1;
3'b100: eject_ST_req = 1;
default: {e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
endcase
end
if (w_vc_alloc == 1) begin
case (w_out)
3'b000: e_ST_req = 1;
3'b001: w_ST_req = 1;
3'b010: n_ST_req = 1;
3'b011: s_ST_req = 1;
3'b100: eject_ST_req = 1;
default: {e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
endcase
end
if (n_vc_alloc == 1) begin
case (n_out)
3'b000: e_ST_req = 1;
3'b001: w_ST_req = 1;
3'b010: n_ST_req = 1;
3'b011: s_ST_req = 1;
3'b100: eject_ST_req = 1;
default: {e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
endcase
end
if (s_vc_alloc == 1) begin
case (s_out)
3'b000: e_ST_req = 1;
3'b001: w_ST_req = 1;
3'b010: n_ST_req = 1;
3'b011: s_ST_req = 1;
3'b100: eject_ST_req = 1;
default: {e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
endcase
end
if (inject_vc_alloc == 1) begin
case (inject_out)
3'b000: e_ST_req = 1;
3'b001: w_ST_req = 1;
3'b010: n_ST_req = 1;
3'b011: s_ST_req = 1;
3'b100: eject_ST_req = 1;
default: {e_ST_req, w_ST_req, n_ST_req, s_ST_req, eject_ST_req} = 5'b0;
endcase
end
end
end
always @(posedge clk) begin
if (reset) {e_ack, w_ack, n_ack, s_ack, inject_ack} = 5'b0;
else begin
{e_ack, w_ack, n_ack, s_ack, inject_ack} = 5'b0;
if (oe_en == 1) begin
if (e_out == 3'd0 && e_vc_alloc) e_ack = 1;
else if (w_out == 3'd0 && w_vc_alloc) w_ack = 1;
else if (n_out == 3'd0 && n_vc_alloc) n_ack = 1;
else if (s_out == 3'd0 && s_vc_alloc) s_ack = 1;
else if (inject_out == 3'd0 && inject_vc_alloc) inject_ack = 1;
end
if (ow_en == 1) begin
if (e_out == 3'd1 && e_vc_alloc) e_ack = 1;
else if (w_out == 3'd1 && w_vc_alloc) w_ack = 1;
else if (n_out == 3'd1 && n_vc_alloc) n_ack = 1;
else if (s_out == 3'd1 && s_vc_alloc) s_ack = 1;
else if (inject_out == 3'd1 && inject_vc_alloc) inject_ack = 1;
end
if (on_en == 1) begin
if (e_out == 3'd2 && e_vc_alloc) e_ack = 1;
else if (w_out == 3'd2 && w_vc_alloc) w_ack = 1;
else if (n_out == 3'd2 && n_vc_alloc) n_ack = 1;
else if (s_out == 3'd2 && s_vc_alloc) s_ack = 1;
else if (inject_out == 3'd2 && inject_vc_alloc) inject_ack = 1;
end
if (os_en == 1) begin
if (e_out == 3'd3 && e_vc_alloc) e_ack = 1;
else if (w_out == 3'd3 && w_vc_alloc) w_ack = 1;
else if (n_out == 3'd3 && n_vc_alloc) n_ack = 1;
else if (s_out == 3'd3 && s_vc_alloc) s_ack = 1;
else if (inject_out == 3'd3 && inject_vc_alloc) inject_ack = 1;
end
if (Eject_en == 1) begin
if (e_out == 3'd4 && e_vc_alloc) e_ack = 1;
else if (w_out == 3'd4 && w_vc_alloc) w_ack = 1;
else if (n_out == 3'd4 && n_vc_alloc) n_ack = 1;
else if (s_out == 3'd4 && s_vc_alloc) s_ack = 1;
else if (inject_out == 3'd4 && inject_vc_alloc) inject_ack = 1;
end
end
end
endmodule
| 7.381461 |
module st_feature_addr_gen_Add2i1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2i1u8_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output [8:0] out1;
wire [8:0] asc001;
assign asc001 = +(in1) + (9'B000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u16u16u16_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_4_2 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_4_3 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add2Mul2u8u16u16_4_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3i1u8u16_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3u32u32u32_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3u32u32u32_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3u32u32u32_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add3u32u32u32_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32Mul3u16u16u16Mul2u16u16u16_1 (
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in7);
assign asc001_tmp_1 = asc001_tmp_2 + (in5 * in6);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32Mul3u16u16u16Mul2u16u16u16_4 (
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in7);
assign asc001_tmp_1 = asc001_tmp_2 + (in5 * in6);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32Mul3u16u16u16Mul2u16u16u16_4_2 (
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in7);
assign asc001_tmp_1 = asc001_tmp_2 + (in5 * in6);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32u32u32u32_1 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32u32u32u32_4 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32u32u32u32_4_0 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add4u32u32u32u32_4_1 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add_16Ux16U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add_16Ux16U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Add_16Ux16U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
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