code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module synth_arb (
clk,
reset_n,
memadrs,
memdata,
wreq,
synth_ctrl,
synth_data,
fifo_full
);
input wire clk, reset_n, wreq, fifo_full;
input wire [7:0] memadrs, memdata;
output reg [7:0] synth_ctrl, synth_data;
reg [7:0] state_reg;
reg [3:0] wait_cnt;
reg wreq_inter, w_do... | 7.050979 |
module top_small (
input clk,
resetn,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata
);
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SH... | 7.770123 |
module top_regular (
input clk,
resetn,
output trap,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output ... | 6.893677 |
module synth_dual_port_memory (
clk,
rstb,
error,
//bus 0
wr_ena0,
addr0,
din0,
dout0,
//bus 1
wr_ena1,
addr1,
din1,
dout1
);
parameter N = 32; //bus width
parameter I_LENGTH = 512;
parameter I_WIDTH = 9;
parameter D_LENGTH = 1024;
parameter D_WIDTH = 10... | 7.544256 |
module top (
input clk,
resetn,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata
);
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SHIFT(0)... | 7.233807 |
module synth_ram #(
parameter integer WORDS = 64
) (
input clk,
input ena,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] rdata;
reg [31:0] mem[0:WORDS-1];
always @(posedge clk) begin
if (ena == 1'b1) begin
rdata <= mem[addr];
... | 6.623284 |
module synth_tb ();
reg clk = 0;
always #1 clk = !clk;
reg reset = 0;
reg [1:0] shape = 1;
reg [5:0] tone = 60;
wire out;
reflet_synth_generator synth (
.clk (clk),
.reset(reset),
.shape(shape),
.tone (tone),
.out (out)
);
initial begin
$dumpfile("synth_tb.vcd"... | 7.219264 |
module synth_testbench ();
parameter SYSTEM_CLK_PERIOD = 8;
parameter SYSTEM_CLK_FREQ = 125_000_000;
reg sys_clk = 0;
reg sys_rst = 0;
always #(SYSTEM_CLK_PERIOD / 2) sys_clk <= ~sys_clk;
// UART Signals between the on-chip and off-chip UART
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
// Off-chip UART Ready... | 7.871806 |
module counter_6 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n2... | 6.768667 |
module counter_5 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n2... | 6.894743 |
module counter_4 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n2... | 6.562775 |
module counter_2 (
clk,
reset,
count_to,
count
);
input [7:0] count_to;
output [7:0] count;
input clk, reset;
wire N3, N7, N8, N9, N10, N11, N12, N13, N25, N26, N27, N28, N29, N30, N31,
N32, n1, n2, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n2... | 6.703607 |
module: synth_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module synth_top_testbench;
// Inputs
reg reset_io_p;
reg clk_io_p;
reg [15:0] data_in_io_p;
// Outputs
wire core_t... | 6.889969 |
module shift_register_v (
C,
SI,
SO
);
input C, SI;
output SO;
wire [6:0] tmp;
DFFQX1 \tmp_reg[0] (
.D (SI),
.CLK(C),
.Q (tmp[0])
);
DFFQX1 \tmp_reg[1] (
.D (tmp[0]),
.CLK(C),
.Q (tmp[1])
);
DFFQX1 \tmp_reg[2] (
.D (tmp[1]),
.CLK(C),
... | 6.854847 |
module syn_4bit_upcounter (
d_out,
d_in,
load,
reset,
clk
);
output reg [3:0] d_out;
input [3:0] d_in;
input load, reset, clk;
always @(posedge clk) begin
if (reset) d_out <= 4'b0000;
else if (load) d_out <= d_in;
else d_out <= d_out + 1'b1;
end
endmodule
| 6.508778 |
module syn_4bit_upcounter_tb ();
reg [3:0] d_in;
reg load, reset, clk;
wire [3:0] d_out;
syn_4bit_upcounter DUT (
d_out,
d_in,
load,
reset,
clk
);
always begin
clk = 1'b0;
forever #5 clk = ~clk;
end
task initialize;
begin
d_in = 4'b0000;
load = ... | 6.508778 |
module transform asynchrounous signal to a
// specific domain. We use four flip-flops in this module to do
// this work
// -----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
(*dont_touch = "yes" *)
module syn_block #(
parameter INITIALISE = 1'b0,
parameter DEPTH = ... | 7.511081 |
module name - syn_clk_judge
// Version: V3.4.0.20220420
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/100ps
module syn_clk_judge(
input ... | 7.149958 |
module syn_dff_tb ();
reg t_clk;
reg t_rst;
reg t_d;
wire t_syn_q;
//
// Synchronous DFF
//
syn_dff dut (
.clk(t_clk),
.rst(t_rst),
.d (t_d),
.q (t_syn_q)
);
//
// Produce the clock
//
initial begin
t_clk = 0;
end
always #20 t_clk = ~t_clk;
//
// Ge... | 7.077913 |
module syn_dual_16x8ram (
d_out,
d_in,
clock,
reset,
wr_en,
wr_addr,
rd_en,
rd_addr
);
parameter RAM_WIDTH = 8, RAM_DEPTH = 16, ADDR_SIZE = 4;
output reg [RAM_WIDTH-1:0] d_out;
input [RAM_WIDTH-1:0] d_in;
input clock, reset, wr_en, rd_en;
input [ADDR_SIZE-1:0] wr_addr, rd_add... | 7.717203 |
module syn_dual_16x8ram_tb ();
parameter RAM_WIDTH = 8, RAM_DEPTH = 16, ADDR_SIZE = 4;
reg [RAM_WIDTH-1:0] d_in;
reg clock, reset, wr_en, rd_en;
reg [ADDR_SIZE-1:0] wr_addr, rd_addr;
wire [RAM_WIDTH-1:0] d_out;
syn_dual_16x8ram DUT (
d_out,
d_in,
clock,
reset,
wr_en,
... | 7.717203 |
module syn_fifo (
clk,
rstn,
wr_en,
rd_en,
wr_data,
rd_data,
fifo_full,
fifo_empty
);
//
parameter width = 8;
parameter depth = 8;
parameter addr = 3;
//ź
input clk; //ʱź
input rstn; //½ظλ
input wr_en; //дʹ
input rd_en; //ȡʹ
//ź
input [width - 1 : 0] wr_data;... | 7.246965 |
module syn_fifo (
clk, // Clock input
rst, // Active high reset
wr_cs, // Write chip select
rd_cs, // Read chipe select
data_in, // Data input
rd_en, // Read enable
wr_en, // Write Enable
data_out, // Data Output
empty, // FIFO empty
full // FIFO full
);
// FIFO cons... | 7.246965 |
module syn_fifo (
clk, // Clock input
rst, // Active high reset
wr_cs, // Write chip select
rd_cs, // Read chipe select
data_in, // Data input
rd_en, // Read enable
wr_en, // Write Enable
data_out, // Data Output
empty, // FIFO empty
full // FIFO full
);
// FIFO cons... | 7.246965 |
module syn_fifo_tb;
reg clk, rstn;
reg wr_en, rd_en;
wire fifo_full, fifo_empty;
reg [7 : 0] wr_data;
wire [7 : 0] rd_data;
//ɲ
initial begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars(0, myfifo);
$fsdbDumpon();
end
//
syn_fifo myfifo (
.clk(clk),
.rstn(rstn),
.wr_e... | 6.527895 |
module syn_fifo_v1_Nb #(
parameter BUS_WIDTH = 8,
FIFO_DEPTH = 8
) (
input RSTn,
input CLK,
input [BUS_WIDTH-1:0] DATA_IN,
input WR_EN,
input RD_EN,
output FULL,
output EMPTY,
output reg [BUS_WIDTH-1:0] DATA_OUT
);
localparam COUNTER_WIDTH = $clog2(FIFO_DEPTH) + (2 ** $clog2(F... | 7.046492 |
module syn_filt_pipe (
clk,
reset,
start,
memIn,
xAddr,
aAddr,
yAddr,
fMemAddr,
updateAddr,
done,
lagMuxSel,
lagMux1Sel,
lagMux2Sel,
lagMux3Sel,
testReadRequested,
testWriteRequested,
testWriteOut,
testWriteEnable
);
// Inputs
input clk;
inp... | 6.531015 |
module Register #(
parameter WORD_WIDTH = 0,
parameter RESET_VALUE = 0
) (
input clock,
input clock_enable,
input clear,
input [WORD_WIDTH-1:0] data_in,
output reg [WORD_WIDTH-1:0] data_out
);
initial begin
data_out = RESET_VALUE;
end
always @(posedge clock) begin
if (clock_... | 6.555282 |
module Multiplexer_Binary_Behavioural #(
parameter WORD_WIDTH = 0,
parameter ADDR_WIDTH = 0,
parameter INPUT_COUNT = 0,
// Do not set at instantiation
parameter TOTAL_WIDTH = WORD_WIDTH * INPUT_COUNT
) (
input [ADDR_WIDTH-1:0] selector,
input [TOTAL_WIDTH-1:0] words_in,
output reg [WOR... | 7.156108 |
module Register_Pipeline #(
parameter WORD_WIDTH = 0,
parameter PIPE_DEPTH = 0,
// Don't set at instantiation
parameter TOTAL_WIDTH = WORD_WIDTH * PIPE_DEPTH,
// concatenation of each stage initial/reset value
parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0
) (
input clock,
input clock_enab... | 8.366929 |
module Synthesis_Harness_Input #(
parameter WORD_WIDTH = 0
) (
input clock,
input clear,
input bit_in,
input bit_in_valid,
output [WORD_WIDTH-1:0] word_out
);
localparam WORD_ZERO = {WORD_WIDTH{1'b0}};
// Vivado: don't put in I/O buffers, and keep netlists separate in synth and implementat... | 8.207706 |
module Synthesis_Harness_Output #(
parameter WORD_WIDTH = 0
) (
input clock,
input clear,
input [WORD_WIDTH-1:0] word_in,
input word_in_valid,
output reg bit_out
);
localparam WORD_ZERO = {WORD_WIDTH{1'b0}};
initial begin
bit_out = 1'b0;
end
wire [WORD_WIDTH-1:0] word_out;
// V... | 8.207706 |
module \$paramod\adder\WIDTH=32 (
operand_a,
operand_b,
result
);
(* src = "../core/common/adder.sv:12.24-12.33" *)
input [31:0] operand_a;
(* src = "../core/common/adder.sv:13.24-13.33" *)
input [31:0] operand_b;
(* src = "../core/common/adder.sv:14.24-14.30" *)
output [31:0] result;
assign r... | 7.306332 |
module \$paramod\multiplexer2\WIDTH=32 (
in0,
in1,
sel,
out
);
(* src = "../core/common/multiplexer2.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer2.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer2.sv:15.24-15.27" *)
output [31:0] out;
(... | 6.780879 |
module \$paramod\multiplexer4\WIDTH=32 (
in0,
in1,
in2,
in3,
sel,
out
);
(* src = "../core/common/multiplexer4.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer4.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer4.sv:14.24-14.27" *)
inpu... | 6.780879 |
module \$paramod\multiplexer8\WIDTH=32 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
(* src = "../core/common/multiplexer8.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer8.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/mu... | 6.780879 |
module \$paramod\multiplexer\WIDTH=32\CHANNELS=2 (
in_bus,
sel,
out
);
wire _0_;
(* src = "../core/common/multiplexer.sv:12.45-12.51" *)
input [63:0] in_bus;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[0] ;
(* src = "../core/common/multiplexer.sv:19.26-19.37"... | 6.780879 |
module \$paramod\multiplexer\WIDTH=32\CHANNELS=4 (
in_bus,
sel,
out
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
(* src = "../core/common/multiplexer.sv:12.45-12.51" *)
input [127:0] in_bus;
(* src = "../core/common/multiplexer.sv:19.26-19.37" *)
wire [31:0] \input_array[0] ;
(* src = "../co... | 6.780879 |
module \$paramod\multiplexer\WIDTH=32\CHANNELS=8 (
in_bus,
sel,
out
);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
(* src = "../core/common/multiplexer.sv:12.45-12.51" *)
input [255:0] in_bus;
(* src = "../core/common/multiplexer.sv:19.26-19.... | 6.780879 |
module control_transfer (
result_equal_zero,
inst_funct3,
take_branch
);
wire _00_;
wire _01_;
(* src = "../core/common/control_transfer.sv:17.36-17.54" *)
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
(* src = "../core/common/control_transfer.sv:11.18-11... | 6.898599 |
module \$paramod\multiplexer2\WIDTH=32 (
in0,
in1,
sel,
out
);
(* src = "../core/common/multiplexer2.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer2.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer2.sv:15.24-15.27" *)
output [31:0] out;
(... | 6.780879 |
module \$paramod\multiplexer4\WIDTH=32 (
in0,
in1,
in2,
in3,
sel,
out
);
(* src = "../core/common/multiplexer4.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer4.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/multiplexer4.sv:14.24-14.27" *)
inpu... | 6.780879 |
module \$paramod\multiplexer8\WIDTH=32 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
(* src = "../core/common/multiplexer8.sv:12.24-12.27" *)
input [31:0] in0;
(* src = "../core/common/multiplexer8.sv:13.24-13.27" *)
input [31:0] in1;
(* src = "../core/common/mu... | 6.780879 |
module SYN_RESET (
input clk,
input rst_n,
input in,
output reg out
);
always @(posedge clk)
if (rst_n == 1'b0) out <= 1'b0;
else out <= in;
endmodule
| 7.127467 |
module syn_rst (
input wire clock,
input wire rstn, //async_negedge_active_reset
output wire syn_rstn
);
reg rst_nr1, rst_nr2;
always @(posedge clock or negedge rstn) begin
if (!rstn) begin
rst_nr1 <= 1'b0;
rst_nr2 <= 1'b0; //异步复位
end else begin
rst_nr1 <= 1'b1;
r... | 7.991093 |
module_name>
-- Author : mammenx
-- Associated modules:
-- Function :
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- $Header$
-- $Log$
-------------------------------------... | 9.021353 |
module syn_XOR (
input IN,
output OUT,
input TX_CLK,
input RX_CLK,
input RST_N
);
wire Y;
wire a;
reg P;
reg Q;
always @(posedge TX_CLK or negedge RST_N) begin
if (!RST_N) P <= 0;
else P <= a;
end
always @(posedge RX_CLK or negedge RST_N) begin
if (!RST_N) Q <= 0;
... | 6.563798 |
module SyrupMemory1P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR,
input [ DAT... | 7.576154 |
module SyrupMemory2P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DA... | 7.588846 |
module SyrupMemory3P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DA... | 7.531916 |
module SyrupMemory4P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DA... | 7.809143 |
module SyrupMemory5P #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 32,
parameter WAY = 1,
parameter LINEWIDTH = 128,
parameter BYTE_ENABLE = 0
) (
input CLK,
input [ ADDR_WIDTH-1:0] ADDR0,
input [ DA... | 7.428162 |
module SyrupOutChannel #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 4
) (
input CLK,
input [DATA_WIDTH-1:0] D,
input WE
);
endmodule
| 8.06564 |
module SyrupInChannel #(
parameter DOMAIN = "undefined",
parameter ID = 0,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 4
) (
input CLK,
output [DATA_WIDTH-1:0] Q,
input RE
);
endmodule
| 6.556349 |
module sys64b_reg (
input wire clk,
input wire rst,
//д˿
input wire we,
input wire [`RegBus64] idt_i,
input wire [`RegBus64] gdt_i,
input wire [`RegBus64] ldt_i,
input wire [`RegBus64] tr_i,
//˿1
output reg [`RegBus64] idt_o,
output reg [`RegBus64] gdt_o,
o... | 7.032715 |
module sysace_top #(
parameter mpulba_top = 28'd65536 - 28'd256
) (
input CLK,
input RST,
output reg [27:0] mpulba,
output [ 7:0] nsectors,
output sysace_start,
input sysace_busy,
input [15:0] sysace_read_data,
input sysace_read_avail,
output reg wr_en,
... | 8.299039 |
module sysArr2x2 (
input clk,
input active,
input [15:0] datain, // 2 datain inputs
input [15:0] win, // 2 weight inputs
input [31:0] sumin, // 2 sumin inputs
input [1:0] wwrite, // 2 write enable inputs
output wire [15:0] maccout1, // 2 maccout outputs
output wire [15:0] maccout2,... | 7.464933 |
module sysArrRow (
clk,
active,
datain,
win,
sumin,
wwrite,
maccout,
wout,
wwriteout,
activeout,
dataout
);
parameter row_width = 2;
localparam weight_width = 8 * row_width; // Number of weight bits needed
localparam sum_width = 16 * row_width; // Number of sum bits n... | 7.472352 |
module SysClockGen (
CLKIN_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK2X_OUT,
LOCKED_OUT
);
input CLKIN_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK2X_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wi... | 6.602624 |
module SysCodeBlock (
address,
byteena,
clock,
data,
wren,
q);
input [10:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// syn... | 6.538502 |
module syscon (
output logic clk_o,
output logic rst_o
);
logic clk, rst;
initial begin
clk <= 1'b0;
rst <= 1'b1;
#20 rst <= 1'b0;
end
//------------------------------------------------------------------------------
// main clock generation
//------------------------------------------... | 7.340167 |
module syscon_top (
output reg clk_pin = 0,
output reg rst_pin = 1
);
wire clk;
wire rst;
always @(posedge clk) begin
clk_pin <= !clk_pin;
rst_pin <= rst;
end
syscon syscon_inst0 (
.clk(clk),
.rst(rst)
);
// Unit test
`ifdef SIMULATION
testAnythingProtocol #("build", "rep... | 7.986784 |
module syscon_wrapper (
input wire i_clk,
input wire i_rst,
input wire gpio_irq,
input wire ptc_irq,
output wire o_timer_irq,
// output wire o_sw_irq3,
// output wire o_sw_irq4,
input wire i_ram_init_done,
input wire ... | 6.905671 |
module sysctl_icap (
input sys_clk,
input sys_rst,
output reg ready,
input we,
input [15:0] d,
input ce,
input write
);
reg icap_clk;
reg icap_clk_r;
reg d_ce;
reg [15:0] d_r;
reg ce_r;
reg write_r;
always @(posedge sys_clk) begin
if (d_ce) begin
d_r[0] <= d[7];
... | 8.041401 |
module sysctrl_wb #(
parameter BASE_ADR = 32'h2F00_0000,
parameter PWRGOOD = 8'h00,
parameter CLK_OUT = 8'h04,
parameter TRAP_OUT = 8'h08,
parameter IRQ_SRC = 8'h0c
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_dat_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
inp... | 7.004691 |
module sysctrl #(
parameter BASE_ADR = 32'h2300_0000,
parameter PWRGOOD = 8'h00,
parameter CLK_OUT = 8'h04,
parameter TRAP_OUT = 8'h08,
parameter IRQ_SRC = 8'h0c
) (
input clk,
input resetn,
input [31:0] iomem_addr,
input iomem_valid,
input [3:0] iomem_wstrb,
input [31:0]... | 6.65308 |
module sysctrl_tb;
reg clock;
reg power1;
reg RSTB;
wire gpio;
wire [15:0] checkbits;
wire [7:0] spivalue;
wire [37:0] mprj_io;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire SDO;
integer ccount;
integer ucount;
assign checkbits = mprj_io[31:16];
assign spivalue ... | 6.899735 |
module SYSCTRL_TXFSM #(
parameter DATA_WIDTH = 32
) (
input clk,
RST,
RdData_valid,
OUT_Valid,
input [$clog2(DATA_WIDTH/8) : 0] TX_CNTR,
output reg TX_CNTR_RST,
TX_CNTR_EN,
TX_D_VLD
);
localparam SEND_IDLE = 0, RF_TX_CNTR_EN = 1, ALU_TX_CNTR_EN = 2;
reg [1:0] tx_state;
alwa... | 8.204743 |
module sysid_rom #(
parameter ROM_WIDTH = 32,
parameter ROM_ADDR_BITS = 6,
parameter PATH_TO_FILE = "path_to_mem_init_file"
) (
input clk,
input [ROM_ADDR_BITS-1:0] rom_addr,
output reg [ ROM_WIDTH-1:0] rom_data
);
reg [ROM_WIDTH-1:0] lut_rom[(2**ROM_ADDR_BIT... | 8.593528 |
module sysmem0_ipgen_lscc_ahblmem_arbiter #(
parameter PORT_TYPE_S0 = "R/W",
parameter PORT_TYPE_S1 = "R/W",
parameter ADDR_WIDTH = 32,
parameter RESET_MODE = "async",
parameter ARBITER_EN = 0
) (
// ------------------------------------------------------------------------------
// Inpu... | 6.882045 |
module sysmem0_ipgen_lscc_fifo_streamer #(
parameter ADDR_DEPTH = 16384,
parameter ADDR_WIDTH = clog2(ADDR_DEPTH),
parameter FIFO_START = 0,
parameter DATA_WIDTH = 32,
parameter BYTE_WIDTH = (DATA_WIDTH / 8),
parameter MEM_TYPE = "EBR"
) (
input fifo_clk_i,
input fifo_wr_en_i,
inpu... | 6.882045 |
module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_out,
output wire rst_out
);
// Signals
wire pll_lock;
wire pll_reset_n;
wire clk_i;
wire rst_i;
reg [3:0] rst_cnt;
// PLL instance
`ifdef SIM
assign clk_i = clk_in;
assign pll_lock = pll_reset_n;
`else
SB_PLL4... | 7.349607 |
module sysmgr_hfosc (
input wire rst_in,
output wire clk_out,
output wire rst_out
);
// Signals
wire clk_i;
reg rst_i;
reg [7:0] rst_cnt = 8'h00;
// 48 MHz source
SB_HFOSC #(
.TRIM_EN ("0b0"),
.CLKHF_DIV("0b00")
) osc_I (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF... | 8.735074 |
module sysmgr_pll (
input wire clk_in,
input wire rst_in,
output wire clk_24m,
output wire clk_48m,
output wire rst_out
);
// Signals
wire pll_lock;
wire pll_reset_n;
wire clk_1x;
wire clk_2x;
wire rst_i;
reg [3:0] rst_cnt;
// Clock frequency input depends on board
`ifdef BOARD_FOMU_HACKER
`define CLK... | 7.284812 |
module SysMon_exdes (
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable fo... | 8.414254 |
module SysMon_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20 * ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [ 6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wi... | 7.424903 |
module SystArr (
input wire clk,
input wire nrst,
input wire ena,
input wire [29:0] T,
input wire [11:0] i_tsrc,
input wire [29:0] R,
input wire [11:0] i_rsrc,
input wire [95:0] D0,
input wire [95:0] D1,
input wire [95:0] D2,
output wire [95:0] D,
output wire [11:0] o... | 6.77583 |
module IntXbar (
input auto_int_in_0,
input auto_int_in_1,
input auto_int_in_2,
input auto_int_in_3,
input auto_int_in_4,
input auto_int_in_5,
input auto_int_in_6,
input auto_int_in_7,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output aut... | 6.794458 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
input auto_in_sync_1,
input auto_in_sync_2,
input auto_in_sync_3,
input auto_in_sync_4,
input auto_in_sync_5,
input auto_in_sync_6,
input auto_in_sync_7,
output auto_out_0,
output auto_out_1,
ou... | 6.70996 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_5_clock,
output auto_out_5_reset,
output auto_out_4_clock,
output auto_out_4_reset,
output auto_out_3_clock,
output auto_out_3_reset,
output auto_out_2_clock,
output auto_out_2_reset,
out... | 6.914809 |
module FixedClockBroadcast_3 (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala ... | 6.914809 |
module SourceE (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_sink,
output io_e_valid,
output [2:0] io_e_bits_sink
);
wire io_e_q_clock; // @[Decoupled.scala 361:21]
wire io_e_q_reset; // @[Decoupled.scala ... | 6.986119 |
module SourceX (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input io_x_ready,
output io_x_valid
);
wire io_x_q_clock; // @[Decoupled.scala 361:21]
wire io_x_q_reset; // @[Decoupled.scala 361:21]
wire io_x_q_io_enq_ready; // @[Decoupled.scala 361:21]
wire io... | 6.885755 |
module SinkE (
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid; // @[SinkE.scala 44:19]
assign io_resp_bits_sink = io_e_bits_sink; // @[SinkE.scala 45:23]
endmodule
| 8.126739 |
module SinkX (
input clock,
input reset,
input io_req_ready,
output io_req_valid,
output [14:0] io_req_bits_tag,
output [ 9:0] io_req_bits_set,
output io_x_ready,
input io_x_valid,
input [31:0] io_x_bits_address
);
wire x_clock; // @[... | 6.564372 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae_ptw,
input io_x_ae_final,
input io_x_pf,
input io_x_gf,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input ... | 7.587549 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 65:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 66:33]
wire add = io_cmd == 5'h8... | 8.467919 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0... | 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[raw... | 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRec... | 6.761906 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4... | 6.992477 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module RoundRawFNToRecFN_3 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module OptimizationBarrier_42 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_43 (
input [43:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [43:0] io_y_ppn,
output io_y_d... | 7.587549 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @... | 6.820992 |
module IntSyncAsyncCrossingSink_1 (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
.... | 6.70996 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge res... | 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala ... | 6.689384 |
module PLICFanIn (
input [2:0] io_prio_0,
input [2:0] io_prio_1,
input [2:0] io_prio_2,
input [2:0] io_prio_3,
input [2:0] io_prio_4,
input [2:0] io_prio_5,
input [2:0] io_prio_6,
input [2:0] io_prio_7,
input [7:0] io_ip,
output [3:0] io_dev,
output [2:0] io_max
);
... | 8.419901 |
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