code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IntSyncCrossingSource_16 (
input auto_in_3_0,
input auto_in_2_0,
input auto_in_1_0,
input auto_in_0_0,
output auto_out_3_sync_0,
output auto_out_2_sync_0,
output auto_out_1_sync_0,
output auto_out_0_sync_0
);
assign auto_out_3_sync_0 = auto_in_3_0; // @[Nodes.scala 1210:84 ... | 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[Sy... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[Shi... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[S... | 6.605499 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_i... | 6.70336 |
module BundleBridgeNexus_42 (
output [1:0] auto_out_3,
output [1:0] auto_out_2,
output [1:0] auto_out_1,
output [1:0] auto_out_0
);
wire [1:0] outputs_0 = 2'h0; // @[HasTiles.scala 161:32]
wire [1:0] outputs_1 = 2'h1; // @[HasTiles.scala 161:32]
wire [1:0] outputs_2 = 2'h2; // @[HasTiles.scala ... | 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_17 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.... | 6.689384 |
module AsyncResetRegVec_w8_i0 (
input clock,
input reset,
input [7:0] io_d,
output [7:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_29 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
input auto_in_2,
input auto_in_3,
input auto_in_4,
input auto_in_5,
input auto_in_6,
input auto_in_7,
output auto_out_sync_0,
output auto_out_sync_1,
output auto_ou... | 6.689384 |
module IntXbar (
input auto_int_in_0,
input auto_int_in_1,
input auto_int_in_2,
input auto_int_in_3,
input auto_int_in_4,
input auto_int_in_5,
input auto_int_in_6,
input auto_int_in_7,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output aut... | 6.794458 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
input auto_in_sync_1,
input auto_in_sync_2,
input auto_in_sync_3,
input auto_in_sync_4,
input auto_in_sync_5,
input auto_in_sync_6,
input auto_in_sync_7,
output auto_out_0,
output auto_out_1,
ou... | 6.70996 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16... | 6.914809 |
module FixedClockBroadcast_3 (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala ... | 6.914809 |
module BroadcastFilter (
output io_request_ready,
input io_request_valid,
input [ 1:0] io_request_bits_mshr,
input [31:0] io_request_bits_address,
input io_request_bits_allocOH,
input io_request_bits_needT,
input io_response_ready,
output i... | 9.561359 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae_ptw,
input io_x_ae_final,
input io_x_pf,
input io_x_gf,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input ... | 7.587549 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd == 5'h8... | 8.467919 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0... | 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[raw... | 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRec... | 6.761906 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4... | 6.992477 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module RoundRawFNToRecFN_3 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module OptimizationBarrier_42 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_43 (
input [43:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [43:0] io_y_ppn,
output io_y_d... | 7.587549 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @... | 6.820992 |
module IntSyncAsyncCrossingSink_1 (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
.... | 6.70996 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge res... | 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala ... | 6.689384 |
module PLICFanIn (
input [2:0] io_prio_0,
input [2:0] io_prio_1,
input [2:0] io_prio_2,
input [2:0] io_prio_3,
input [2:0] io_prio_4,
input [2:0] io_prio_5,
input [2:0] io_prio_6,
input [2:0] io_prio_7,
input [7:0] io_ip,
output [3:0] io_dev,
output [2:0] io_max
);
... | 8.419901 |
module IntSyncCrossingSource_4 (
input auto_in_0,
output auto_out_sync_0
);
assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[Sy... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[Shi... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[S... | 6.605499 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_i... | 6.70336 |
module BundleBridgeNexus_15 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_5 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.s... | 6.689384 |
module AsyncResetRegVec_w8_i0 (
input clock,
input reset,
input [7:0] io_d,
output [7:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_8 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
input auto_in_2,
input auto_in_3,
input auto_in_4,
input auto_in_5,
input auto_in_6,
input auto_in_7,
output auto_out_sync_0,
output auto_out_sync_1,
output auto_out... | 6.689384 |
module wait_for_buffer_ready
(input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll... | 8.414605 |
module read_data_buffer (
input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [ 6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll... | 8.732224 |
module get_cf_lock (
input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [ 6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output ll_isbu... | 8.434283 |
module check_if_ready_for_command (
input CLK,
input RST,
input start,
output llread,
output llwrite,
output [15:0] llwritedata,
input [15:0] llreaddata,
output [ 6:0] lladdr,
input llavail,
input llbusy,
output llreq,
output... | 8.306368 |
module SystemClockUnit ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//--... | 7.808239 |
module SystemClockUnit_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals... | 7.808239 |
module SystemClockUnit_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER... | 7.808239 |
module SystemMonitor (
input wire clk,
input wire [6:0] DADDR_IN,
output wire DRDY_OUT,
output wire [15:0] DO_OUT
);
//wire [6:0] DADDR_IN;
wire DEN_IN, DWE_IN, VP_IN, VN_IN;
wire [15:0] DI_IN;
//assign DADDR_IN = 7'h00;
assign DEN_IN = 1'b1;
assign DWE_IN = 1'b0;
assign VP_IN = 1'b0;
... | 6.9415 |
module systemout (
clk,
RW,
WE,
result,
sysout,
notEqual
);
input [4:0] RW;
input WE, clk;
input [31:0] result;
output [31:0] sysout;
output notEqual;
reg [31:0] re2, re4;
initial begin
re2 <= 0;
re4 <= 0;
end
always @(posedge clk) begin
if (WE == 1) begin
... | 6.546045 |
module systemTasks (
input [7:0] x,
output [7:0] z
);
assign z = ~x;
endmodule
| 6.857967 |
module systemTasks_tb ();
reg [7:0] x;
wire [7:0] z;
systemTasks DUT (
x,
z
);
initial begin
#0;
x = 8'd1;
$display("THIS IS A DISPLAY TASK x=%d \t\t z=%d t=%t", x, z,
$time); //Displayed in active region as integers
$monitor("THIS IS A MONITOR TASK x=%b \t z=%b t... | 8.118296 |
module wrapper (
input CLK,
input ASYNC_RST,
input ASYNC_CLK_DIV_RST,
inout SDA,
inout SCL,
output CS,
output DATA_OUT,
output [7:0] TEST_STATE,
output [7:0] TEST_ADC_OUT
);
//synchronize the clock reset
wire CLK_DIV_RST;
synchronizer clk_div_rst (
.clk(CLK),
... | 9.12716 |
module sys_wrap_TB ();
reg ASYNC_RST;
reg ASYNC_CLK_DIV_RST;
reg CLK;
//SDA
wire SDA;
reg output_value;
reg output_valid;
//ADC out
wire SCL;
wire CS;
wire DATA_OUT;
wire [7:0] TEST_STATE;
wire [7:0] TEST_ADC_OUT;
//divide the clock
wrapper UUT (
.CLK(CLK),
.ASYNC_CLK_DIV_... | 7.617219 |
module ISP1362_avalon_slave_1_arbitrator (
// inputs:
ISP1362_avalon_slave_1_irq_n,
clk,
reset_n,
// outputs:
ISP1362_avalon_slave_1_irq_n_from_sa
)
/* synthesis auto_dissolve = "FALSE" */;
output ISP1362_avalon_slave_1_irq_n_from_sa;
input ISP1362_avalon_slave_1_irq_n;
input clk;
inpu... | 7.851613 |
module system_0_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;... | 7.04994 |
module system_0_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"... | 7.04994 |
module system_0_clock_1_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;... | 7.04994 |
module system_0_clock_1_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"... | 7.04994 |
module system_0_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "system_0_onchip_memory2_0.hex";
output [31:0] readdata;
input [15:0] address;
input [3... | 6.558597 |
module system_0_switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [17:0] in_port;
input reset_n;
wire clk_en;
wire [17:0] data_in;
wire [17:0] read_mux_out;
reg [31:0] rea... | 6.720262 |
module system_AD (
input WE,
input [31:0] A,
output WEM,
output WE1,
output WE2,
output reg [1:0] RdSel
);
assign WE1 = (A[31:30] == 2'b10 && A[28:26] == 3'b011 && A[15:8] == 8'H08 && A[15:0] < 16'H900 && WE) ? 1 : 0;
assign WE2 = (A[31:30] == 2'b10 && A[28:26] == 3'b011 && A[15:8] == 8'H09... | 6.631674 |
module system_bus_access (
//AXI4-lite master memory interface
//AXI4-lite global signal
input ACLK,
input ARESETn,
//AXI4-lite Write Address Channel
output AWVALID,
input AWREADY,
output [`AXI_ADDR_WIDTH - 1 : 0] AWADDR,
output [... | 7.996618 |
module system_clk_reset_block (
input sys_clk,
input hard_resetn,
output hard_reset_n,
output hard_reset_p,
output sys_pll_clk_calc,
output sys_pll_clk_data,
output sys_pll_nios_clk,
output sys_pll_reset_n,
output sys_pll_locked
);
wire hard_reset_in_sync;
wire sig_hard_reset_... | 6.704873 |
module System_clk_wiz_0_0 (
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
System_clk_wiz_0_0_clk_wiz inst (
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_... | 6.888088 |
module System_clk_wiz_0_0_clk_wiz ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg (
.O(clk_in1_System_clk_wiz_0_0),
... | 6.888088 |
module system_clk_wiz_0_0 (
clk_out1,
clk_out2,
resetn,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire resetn;
system_clk_wiz_0_0_system_clk_wiz_0... | 6.573608 |
module system_control (
input wb_clk_i,
output reg ram_loader_rst_o,
output reg wb_rst_o,
input ram_loader_done_i
);
reg POR = 1'b1;
reg [3:0] POR_ctr;
initial POR_ctr = 4'd0;
always @(posedge wb_clk_i)
if (POR_ctr == 4'd15) POR <= 1'b0;
else POR_ctr <= POR_ctr + 4'd1;
always @(pose... | 6.919572 |
module system_control_tb ();
reg aux_clk, clk_fpga;
wire wb_clk, dsp_clk;
wire wb_rst, dsp_rst, rl_rst, proc_rst;
reg rl_done, clock_ready;
initial aux_clk = 1'b0;
always #25 aux_clk = ~aux_clk;
initial clk_fpga = 1'b0;
initial clock_ready = 1'b0;
initial begin
@(negedge proc_rst);
#1003 ... | 6.919572 |
module system_crtl (
//clk interface
input clk,
input rst_n,
//global interface
output wire clk_24,
output wire clk_40, //90 degree
output wire clk_100,
output reg sys_rst_n
);
//--------------------------------
////Funtion : Ĵ
always @(posedge clk) begin
sys_rst_n <= ... | 6.828106 |
module system_ctrl (
//global clock
input clk,
input rst_n,
//synced signal
output clk_ref, //clock output
output sys_rst_n //system reset
);
//----------------------------------------------
//rst_n sync, only controlled by the main clk
reg rst_nr1, rst_nr2;
always @(posedge clk) b... | 7.861887 |
module system_ctrl_pll (
//globol clock
input clk,
input rst_n,
//synced signal
output sys_rst_n, //system reset
output clk_c0, //clock output
output clk_c1, //clock output
output clk_c2, //clock output
output clk_c3, //clock output
output clk_c4 //clock o... | 7.076926 |
module DE1_system (
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3,
UART_TXD,
UART_RXD,
KEY,
SW,
CLOCK_50,
GPIO_0,
CLOCK_24,
TXB,
RXB
);
// Define System Abstraction
wire txU;
wire rxU;
wire [15:0] hexD;
wire clk; // System base-clock @ 50mhz
wire rst; // S... | 7.185585 |
module system_de2_tb ();
reg CLOCK_50;
reg [2:0] KEY; //last input
wire VGA_CLK; // VGA Clock
wire VGA_HS; // VGA H_SYNC
wire VGA_VS; // VGA V_SYNC
wire VGA_BLANK; // VGA BLANK
wire VGA_SYNC; // VGA SYNC
wire [9:0] VGA_R; // VGA Red[9:0]
wire [9:0] VGA_G; ... | 7.220196 |
module System_Delay #(
parameter SYS_DELAY_TOP = 24'd2500000 //50ms system init delay
) (
input clk_50m,
input rst_n,
output delay_done
);
reg [23:0] delay_cnt = 24'd0;
always @(posedge clk_50m or negedge rst_n) begin
if (!rst_n) delay_cnt <= 0;
else if (delay_cnt < SYS_DELAY_TOP - 1'b1... | 7.154635 |
module System_Index #(
parameter SYS_DELAY_TOP = 24'd2500000 //延时50ms
) (
input clk_50m,
input rst_n,
output clk_c0,
output sys_rst_n
);
//------------------------
//延时模块例化
wire delay_done; //system init delay has done
System_Delay #(
.SYS_DELAY_TOP(SYS_DELAY_TOP)
) u_System_... | 6.694612 |
module system_init_delay #(
parameter SYS_DELAY_TOP = 24'd2500000 //50ms system init delay
) (
//global clock
input clk, //50MHz
input rst_n,
//system interface
output delay_done
);
//------------------------------------------
//Delay 50ms for steady state when power on
reg [23:0] del... | 6.721599 |
module system_m6502 (
input wire clk,
input wire reset_n,
output wire [7 : 0] leds
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter MEM_BASE_ADDR = 16'... | 8.226803 |
module system_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wir... | 6.536019 |
module system_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wir... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [16:0] cpu... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or i... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty o... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
outpu... | 6.536019 |
module system_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.536019 |
module system_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_... | 6.536019 |
module system_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input re... | 6.536019 |
module system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "system_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
... | 6.594915 |
module system_RAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "system_RAM.hex";
output [31:0] readdata;
input [9:0] address;
input [3:0] byteenable;
i... | 6.730175 |
module system_reset_controller_tb;
// Parameters
localparam SYS_CLK_SPEED = 50000000;
localparam NO_OF_CLK_CYCLES = 20;
// Ports
reg clk = 0;
wire reset;
system_reset_controller #(
.NO_OF_CLK_CYCLES(NO_OF_CLK_CYCLES)
) system_reset_controller_dut (
.clk (clk),
.reset(reset)
);
... | 6.554486 |
module system_rst_processing_system7_0_50M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) ... | 6.740538 |
module system_rst_processing_system7_0_50M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
... | 6.740538 |
module system_rst_processing_system7_0_50M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input ... | 6.740538 |
module system_rst_processing_system7_0_50M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.... | 6.740538 |
module system_rst_processing_system7_0_50M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
in... | 6.740538 |
module system_rst_processing_system7_0_50M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
... | 6.740538 |
module system_rst_ps7_0_100M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0] asr_lpf;
input aux_reset_in;
input slowest_... | 7.106127 |
module system_rst_ps7_0_100M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_1_in4_in,
p_2_in3_in,
exr_lpf,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input p_1_in4_in;
input p_2_in3_in;
input [0:0] exr_lpf... | 7.106127 |
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