code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module system_rst_ps7_0_100M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
mb_debug_sys_rst,
ext_reset_in,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input mb_debug_sys_rst;
input ext_reset_in;
input aux_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0... | 7.106127 |
module system_rst_ps7_0_100M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_... | 7.106127 |
module system_rst_ps7_0_100M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface... | 7.106127 |
module system_rst_ps7_0_100M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h... | 7.106127 |
module system_rst_ps7_0_50M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_... | 7.106127 |
module system_rst_ps7_0_50M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_s... | 7.106127 |
module system_rst_ps7_0_50M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_cl... | 7.106127 |
module system_rst_ps7_0_50M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ... | 7.106127 |
module system_rst_ps7_0_50M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_i... | 7.106127 |
module system_rst_ps7_0_50M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1... | 7.106127 |
module system_sim;
reg clk = 0;
reg reset = 1;
//----------------------------------------------------------------------------
// Memory-Tester System
//----------------------------------------------------------------------------
system dut (
.clk (clk),
.reset(reset)
);
//---------------... | 6.837305 |
module system_testbench ();
// DUT I/O
reg system_clock = 0;
reg [7:0] gpio_switches = 0;
reg [4:0] gpio_buttons = 0;
wire [7:0] gpio_leds;
reg cpu_reset_b = 0;
reg rotary_A, rotary_B, rotary_push = 0;
wire led_c, led_n, led_e, led_w, led_s;
wire piezo_out;
wire fpga_serial_rx, fpga_serial_tx;
ml... | 6.547751 |
module system_timer_tb ();
reg clk = 0, rst = 0;
wire usecond_pulse;
wire msecond_pulse;
wire second_pulse;
wire [9:0] usecond_cntr;
wire [9:0] msecond_cntr;
wire [5:0] second_cntr;
wire [5:0] minute_cntr;
wire [4:0] hour_cntr;
wire [9:0] day_cntr;
system_timer dut (
.clk,
.rst,
... | 6.702788 |
module UART_RX (
UartRx_prescale,
UartRx_RX_IN,
UartRx_PAR_EN,
UartRx_Par_Type,
UartRx_CLK,
UartRx_RST,
UartRx_PDATA,
UartRx_Data_Valid
);
input [4:0] UartRx_prescale;
output [7:0] UartRx_PDATA;
input UartRx_RX_IN, UartRx_PAR_EN, UartRx_Par_Type, UartRx_CLK, UartRx_RST;
output Ua... | 7.513316 |
module Parity_Calc (
ParityCalc_PDATA,
ParityCalc_DataValid,
ParityCalc_ParType,
ParityCalc_ParBit
);
input [7:0] ParityCalc_PDATA;
input ParityCalc_DataValid, ParityCalc_ParType;
output ParityCalc_ParBit;
wire n1, n2, n3, n4;
XNOR2X2M U1 (
.A(ParityCalc_PDATA[7]),
.B(ParityCalc_P... | 7.191657 |
module Parallel_To_Serial (
PISO_ParallelData,
PISO_Count,
PISO_SerialData
);
input [7:0] PISO_ParallelData;
input [2:0] PISO_Count;
output PISO_SerialData;
wire n1, n2;
MX2X2M U1 (
.A (n2),
.B (n1),
.S0(PISO_Count[2]),
.Y (PISO_SerialData)
);
MX4X1M U2 (
.A (PIS... | 7.018949 |
module Uart_TX_Top (
P_DATA,
CLK,
RST_ASYN,
Data_Valid,
PAR_EN,
PAR_TYP,
TX_OUT,
busy
);
input [7:0] P_DATA;
input CLK, RST_ASYN, Data_Valid, PAR_EN, PAR_TYP;
output TX_OUT, busy;
wire Parity_bit_To_Buffer, BuffEn, Parity_En, Parity_bit, Ser_Done, Ser_En, Serial_Data;
wire [7:0... | 6.543511 |
module system_toplevel (
input clk,
input reset,
input bit8,
input parity_en,
input odd_n_even,
input [3:0] baud_val,
input rx,
output tx
);
wire system_reset;
wire [7:0] data_in;
wire [7:0] data_out;
wire CSn, WE, OE, adrs;
//assign led = {bit8, parity_en, odd_n_even, baud_v... | 7.525686 |
module system_top (
output trap,
//tester uart
input uart_valid,
input [`iob_uart_swreg_ADDR_W-1:0] uart_addr,
input [ `DATA_W-1:0] uart_wdata,
input [ 3:0] uart_wstrb,
output [ `D... | 6.765998 |
module mux2X1_2 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
MX2X4M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 7.220422 |
module mux2X1_4 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
MX2X8M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 7.049355 |
module mux2X1_3 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
MX2X4M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 6.805713 |
module mux2X1_5 (
IN_0,
IN_1,
SEL,
OUT
);
input IN_0;
input IN_1;
input SEL;
output OUT;
// Internal wires
wire N0;
assign N0 = SEL;
CLKMX2X6M U1 (
.S0(N0),
.B (IN_1),
.A (IN_0),
.Y (OUT)
);
endmodule
| 6.667851 |
module BIT_SYNC_test_1 (
BitSync_ASYNC,
BitSync_CLK,
BitSync_RST,
BitSync_SYNC,
test_si,
test_se
);
input [0:0] BitSync_ASYNC;
input BitSync_CLK;
input BitSync_RST;
output [0:0] BitSync_SYNC;
input test_si;
input test_se;
// Internal wires
wire \FFSTAGES[0][0] ;
SDFFRQX2M \FF... | 6.676251 |
module Parity_Calc (
ParityCalc_PDATA,
ParityCalc_DataValid,
ParityCalc_ParType,
ParityCalc_ParBit
);
input [7:0] ParityCalc_PDATA;
input ParityCalc_DataValid;
input ParityCalc_ParType;
output ParityCalc_ParBit;
// Internal wires
wire n1;
wire n2;
wire n3;
wire n4;
XNOR2X2M U1 (
... | 7.191657 |
module Parallel_To_Serial (
PISO_ParallelData,
PISO_Count,
PISO_SerialData
);
input [7:0] PISO_ParallelData;
input [2:0] PISO_Count;
output PISO_SerialData;
// Internal wires
wire n1;
wire n2;
MX2X2M U1 (
.S0(PISO_Count[2]),
.B (n1),
.A (n2),
.Y (PISO_SerialData)
);... | 7.018949 |
module Uart_TX_Top_test_1 (
P_DATA,
CLK,
RST_ASYN,
Data_Valid,
PAR_EN,
PAR_TYP,
TX_OUT,
busy,
test_si,
test_so,
test_se,
UART_TX_CLK_m__L3_N0
);
input [7:0] P_DATA;
input CLK;
input RST_ASYN;
input Data_Valid;
input PAR_EN;
input PAR_TYP;
output TX_OUT;
ou... | 6.728658 |
module MX2X8M (
S0,
B,
A,
Y,
VSS,
VDD
);
input S0;
input B;
input A;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.643904 |
module SDFFRQX1M (
SI,
SE,
D,
CK,
RN,
Q,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input RN;
output Q;
inout VSS;
inout VDD;
endmodule
| 6.769267 |
module NAND2BX2M (
AN,
B,
Y,
VSS,
VDD
);
input AN;
input B;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.529063 |
module SDFFRHQX4M (
SI,
SE,
D,
CK,
RN,
Q,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input RN;
output Q;
inout VSS;
inout VDD;
endmodule
| 6.948256 |
module NAND2X2M (
A,
B,
Y,
VSS,
VDD
);
input A;
input B;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.598616 |
module NAND4X2M (
A,
B,
C,
D,
Y,
VSS,
VDD
);
input A;
input B;
input C;
input D;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.835375 |
module SDFFSQX1M (
SI,
SE,
D,
CK,
SN,
Q,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input SN;
output Q;
inout VSS;
inout VDD;
endmodule
| 6.530196 |
module MX4X1M (
S1,
S0,
D,
C,
B,
A,
Y,
VSS,
VDD
);
input S1;
input S0;
input D;
input C;
input B;
input A;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.507033 |
module SDFFRX1M (
SI,
SE,
D,
CK,
RN,
Q,
QN,
VSS,
VDD
);
input SI;
input SE;
input D;
input CK;
input RN;
output Q;
output QN;
inout VSS;
inout VDD;
endmodule
| 6.860177 |
module NAND4XLM (
A,
B,
C,
D,
Y,
VSS,
VDD
);
input A;
input B;
input C;
input D;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.864833 |
module NAND3XLM (
A,
B,
C,
Y,
VSS,
VDD
);
input A;
input B;
input C;
output Y;
inout VSS;
inout VDD;
endmodule
| 6.651028 |
module mux2X1_2 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
MX2X4M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
... | 7.220422 |
module mux2X1_4 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
MX2X8M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
... | 7.049355 |
module mux2X1_3 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
MX2X4M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT),
... | 6.805713 |
module mux2X1_5 (
IN_0,
IN_1,
SEL,
OUT,
VDD,
VSS
);
input IN_0;
input IN_1;
input SEL;
output OUT;
inout VDD;
inout VSS;
// Internal wires
wire N0;
assign N0 = SEL;
// Module instantiations
CLKMX2X6M U1 (
.S0 (N0),
.B (IN_1),
.A (IN_0),
.Y (OUT... | 6.667851 |
module BIT_SYNC_test_1 (
BitSync_ASYNC,
BitSync_CLK,
BitSync_RST,
BitSync_SYNC,
test_si,
test_se,
VDD,
VSS
);
input [0:0] BitSync_ASYNC;
input BitSync_CLK;
input BitSync_RST;
output [0:0] BitSync_SYNC;
input test_si;
input test_se;
inout VDD;
inout VSS;
// Internal wir... | 6.676251 |
module Parity_Calc (
ParityCalc_PDATA,
ParityCalc_DataValid,
ParityCalc_ParType,
ParityCalc_ParBit,
VDD,
VSS
);
input [7:0] ParityCalc_PDATA;
input ParityCalc_DataValid;
input ParityCalc_ParType;
output ParityCalc_ParBit;
inout VDD;
inout VSS;
// Internal wires
wire n1;
wire n... | 7.191657 |
module Parallel_To_Serial (
PISO_ParallelData,
PISO_Count,
PISO_SerialData,
VDD,
VSS
);
input [7:0] PISO_ParallelData;
input [2:0] PISO_Count;
output PISO_SerialData;
inout VDD;
inout VSS;
// Internal wires
wire n1;
wire n2;
// Module instantiations
MX2X2M U1 (
.S0 (PISO_... | 7.018949 |
module Uart_TX_Top_test_1 (
P_DATA,
CLK,
RST_ASYN,
Data_Valid,
PAR_EN,
PAR_TYP,
TX_OUT,
busy,
test_si,
test_so,
test_se,
UART_TX_CLK_m__L3_N0,
VDD,
VSS
);
input [7:0] P_DATA;
input CLK;
input RST_ASYN;
input Data_Valid;
input PAR_EN;
input PAR_TYP;
o... | 6.728658 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 15/8/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module system_top_wrapper_wrapper (
gpio_led_tri_o,
gpio_trig_tri_o,
sys_clk_clk_n,
sys_clk_clk_p,
sys_reset,
uart_rxd,
uart_txd
);
output [9:0] gpio_led_tri_o;
output [0:0] gpio_trig_tri_o;
input sys_clk_clk_n;
input sys_clk_clk_p;
input sys_reset;
input uart_rxd;
output uart_... | 7.554459 |
module system_UART_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire ... | 6.895046 |
module system_UART_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input ... | 6.895046 |
module system_UART_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] byt... | 6.895046 |
module system_UART_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_c... | 6.895046 |
module systest;
//-- parameter
parameter N_EXP = 16384;
parameter N_PAT = N_EXP;
//-- reg and wire
reg clk;
reg reset;
reg in_en;
reg [7:0] Din;
wire busy;
wire out_valid;
wire [7:0] Dout;
reg [7:0] pat_mem [0:N_PAT-1];
reg [7:0] exp_mem [0:N_EXP-1];
... | 7.032771 |
module systolic_array_tb;
reg clk, ce;
reg [31:0] ctrl;
reg [3:0] mem_addr;
reg signed [7:0] x_in;
wire signed [7:0] y_out1, x_out1, y_out2, x_out2;
integer i;
systolic_array dut1 (
clk,
ce,
ctrl,
mem_addr,
x_in,
x_out1,
y_out1
);
defparam dut1.WIDTH = 8; d... | 6.94034 |
module systolic_cell_tb;
reg clk, ce;
reg [31:0] ctrl_in;
reg [ 3:0] mem_addr_in;
reg signed [7:0] y_in, x_in;
wire signed [7:0] y_out, x_out;
wire [31:0] ctrl_out;
wire [3:0] mem_addr_out;
integer i;
systolic_cell dut (
clk,
ce,
ctrl_in,
ctrl_out,
mem_addr_in,
m... | 8.114695 |
module systolic_cell (
clk,
ce,
ctrl_in,
ctrl_out,
mem_addr_in,
mem_addr_out,
y_in,
y_out,
x_in,
x_out
);
// Parameters
parameter WIDTH = 8;
parameter MEM_ADDR_WIDTH = 4;
parameter ROM_FILE = "weights/cell-weights.mem";
localparam ACCUM_WIDTH = WIDTH * 2;
localparam ... | 8.114695 |
module SystolicArray (
output wire done_PE11,
output wire done_PE22,
output wire [15:0] result_row1,
output wire [15:0] result_row2,
// input signals for processing element PE11
input wire [15:0] a11,
input wire [15:0] b1,
input wire [15:0] previous_StageOperand,
input wire start_PE... | 7.188821 |
module SystolicMult #(
parameter INT_WIDTH,
parameter FRAC_WIDTH,
parameter SYSTOLIC_SIZE,
parameter SYSTOLIC_STEP_SIZE
) (
input logic reset,
input logic clk,
input systolic_mult_recv_msg recv_msg,
input logic recv_val,
output logic recv_rdy,
output systolic_mult_send_msg send... | 6.99911 |
module SystolicMultControl #(
// parameter for fixed point number, default is 11.5 (include sign bit)
parameter SYSTOLIC_SIZE,
parameter SYSTOLIC_STEP_SIZE
) (
input logic clk,
input logic reset,
input logic run,
input logic final_run,
output logic shift_result,
output logic fini... | 7.539809 |
module sorting_engine (
input clk,
input reset
);
wire [15:0] right[0:6];
wire [1:0] odd_L, even_L, odd_R, even_R;
wire [1:0] sp_even_R;
assign sp_even_R = (even_R == 2'b10) ? 2'b00 : even_R;
wire [1:0] sp_odd_L;
assign sp_odd_L = (odd_L == 2'b10) ? 2'b00 : odd_L;
bus_controller controller (
... | 7.158008 |
module cmp_swap (
input [15:0] a,
input [15:0] b,
output [15:0] c,
output [15:0] d
);
assign c = (a > b) ? b : a;
assign d = (a > b) ? a : b;
endmodule
| 7.478135 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module systolic_array (
inp_west0,
inp_west4,
inp_west8,
inp_west12,
inp_north0,
inp_north1,
inp_north2,
inp_north3,
clk,
rst,
done
);
input [31:0] inp_west0, inp_west4, inp_west8, inp_west12,
inp_north0, inp_north1, inp_north2, inp_north3;
output reg done;
inp... | 6.94034 |
module block (
inp_north,
inp_west,
clk,
rst,
outp_south,
outp_east,
result
);
input [31:0] inp_north, inp_west;
output reg [31:0] outp_south, outp_east;
input clk, rst;
output reg [63:0] result;
wire [63:0] multi;
always @(posedge clk) begin
if (rst) begin
result <= 0;... | 8.703735 |
module processing_element_systolic_4x4_fp (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
re... | 6.504296 |
module FPMult_PrepModule_systolic_4x4_fp (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// O... | 7.427166 |
module FPMult_NormalizeModule_systolic_4x4_fp (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0]... | 7.947312 |
module FPMult_RoundModule_systolic_4x4_fp (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized man... | 7.570448 |
module fp16_to_fp32_systolic_4x4_fp (
input [15:0] a,
output [31:0] b
);
reg [31:0] b_temp;
reg [ 3:0] j;
reg [ 3:0] k;
reg [ 3:0] k_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[31] = a[15]; //sign bit
b_temp[30:0] = 31'b0;
end else begin
i... | 6.625109 |
module fp32_to_fp16_systolic_4x4_fp (
input [31:0] a,
output [15:0] b
);
reg [15:0] b_temp;
//integer j;
//reg [3:0]k;
always @(*) begin
if (a[30:0] == 15'b0) begin //signed zero
b_temp[15] = a[30]; //sign bit
b_temp[14:0] = 15'b0;
end else begin
if (a[30 : 23] <= 8'd11... | 7.302343 |
module FPAddSub_single_systolic_4x4_fp (
clk,
rst,
a,
b,
operation,
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [31:0] a; // Input A, a 32-bit floating point number
input [31... | 6.626859 |
module FPAddSub_b_systolic_4x4_fp (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
SumS_5,
Shift,
PSgn,
Opr
);
input [22:0] Mmax; // The larger mantissa
input [23:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
inp... | 6.823794 |
module FPAddSub_c_systolic_4x4_fp (
SumS_5,
Shift,
CExp,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [32:0] SumS_5; // Smaller mantissa after 16|12|8|4 shift
input [4:0] Shift; // Shift amount
// Input ports
input [7:0] CExp;
// Output ports
... | 6.945986 |
module FPAddSub_d_systolic_4x4_fp (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
NegE,
InputExc,
P,
Flags
);
// Input ports
input ZeroSum; // Sum is zero
input [8:0] NormE; // Normalized exponent
input [22:0] NormM; // Normalized mantissa
inp... | 7.659336 |
module processing_element_systolic_8x8 (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg ... | 6.504296 |
module quantize #(
parameter ARRAY_SIZE = 8,
parameter SRAM_DATA_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter OUTPUT_DATA_WIDTH = 16
) (
input signed [ARRAY_SIZE*(DATA_WIDTH+DATA_WIDTH+5)-1:0] ori_data,
output reg signed [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] quantized_data
);
localparam max_v... | 8.510663 |
module
//==================================================================
module systolic_array_controller
#(parameter DATA_WIDTH = 32, DATA_SIZE = 8, DIM_SIZE = 4)
(clk,
rst_n,
sys_arr_ena,
clk_count,
go_bit,
done_bit); // port list
//==============================================================... | 7.574158 |
module systolic_array_pe #(
parameter input_width = 8
) (
input clk,
reset, // sync active high reset
input [0:input_width - 1] in_a,
in_b,
output [0:input_width - 1] out_a,
out_b,
output [0:2 * input_width - 1] out_c
);
reg [0:input_width - 1] a_r, b_r;
reg [0:2 * input_width - 1] ... | 6.94034 |
module systolic_array_sim_netlist ();
integer i, j;
reg clk;
reg rstn;
reg en; //协处理器启动信号
//测试使用
reg [7:0] shift_in_A;
reg [7:0] shift_in_B;
wire [7:0] shift_out;
wire ack;
systolic_array test //top封装
(
.clk_p (clk),
.rstn_p(rstn),
.en_p (en),
.p_shift_in_A(shift... | 6.94034 |
module systolic_array_sim_top ();
integer i, j, k;
reg clk;
reg rstn;
reg en; //协处理器启动信号
//测试使用
reg [7:0] shift_in;
wire [7:0] shift_out;
wire ack;
systolic_array test //top封装
(
.clk_p (clk),
.rstn_p(rstn),
.en_p (en),
.p_shift_in(shift_in),
.p_shift_out(s... | 6.94034 |
module systolic_array_sim_without_control ();
integer i, j;
reg clk;
reg rstn;
reg en; //协处理器启动信号
//测试使用
reg [7:0] shift_in_A;
reg [7:0] shift_in_B;
wire [7:0] shift_out;
systolic_array_wrapper test //脉动阵列封装
(
.clk (clk),
.rstn(rstn),
.en (en),
.shift_in_A(shift_in_... | 6.94034 |
module systolic_array_tb ();
parameter IN_WORD_SIZE = 8;
parameter OUT_WORD_SIZE = 24; //Changed this
parameter ARR_ROWS = 8;
parameter ARR_COLS = 8;
reg clk;
reg rst;
// Changed the following
reg [IN_WORD_SIZE-1:0] left_inputs[0:ARR_ROWS * ARR_COLS -1];
reg [IN_WORD_SIZE-1:0] top_inputs[0:ARR_CO... | 6.94034 |
module systolic_array_with_skew #(
parameter IFMAP_WIDTH = 16,
parameter WEIGHT_WIDTH = 16,
parameter OFMAP_WIDTH = 32,
parameter ARRAY_HEIGHT = 4,
parameter ARRAY_WIDTH = 4
) (
input clk,
input rst_n,
input en,
input weight_en,
input weight_wen[ARRAY_HEIGHT - 1 : 0],
inpu... | 6.94034 |
module systolic_array_wrapper //脉动阵列封装
(
input clk,
input rstn,
input OutputSign,
input load, //load使能信号
input shift, //shift使能信号
//测试使用
input [2:0] id_A_0,
input [2:0] id_A_1,
input [2:0] id_A_2,
input [2:0] id_A_3,
//load_B的位置
input [2:0] id_B_0,
input [2:0] id... | 6.94034 |
module systolic_array_wrapper //脉动阵列封装
(
input clk,
input rstn,
input en, //协处理器启动信号
input [7:0] shift_in,
output [7:0] shift_out,
output ack //示意结束
);
wire [7:0] row_0;
wire [7:0] row_1;
wire [7:0] row_2;
wire [7:0] row_3;
wire [7:0] col_0;
wire [7:0] col_1;
wire [7:0] co... | 6.94034 |
module systolic_ctrl #(
parameter PE_ROW_NUM = 4,
parameter PE_COL_NUM = 4,
parameter DATA_WIDTH = 32,
parameter KERNEL_SIZE = 9
) (
input clk,
input rst_n,
input start,
output reg cal_done,
// to pe matrix
output res_shift,
output [PE_ROW_NUM-1:0] res_valid
);
wire val... | 6.602816 |
module systolic_cube_without_fifo #(
parameter ARRAY_NUM = 3,
parameter BLOCK_NUM = 3,
parameter CUBE_NUM = 3, // dont change CUBE_NUM
parameter RAM_DEPTH = 2048
) (
input wire iClk,
input wire iRst,
input wire iS... | 7.265994 |
module of the N bit digital-serial systolic multiplier.
@Author: Jinyu Xie, Wenzhao Xie, Yuteng Huang, Hao Sun.
@Date: 2018/11/21
*/
`include "configuration.vh"
module systolic_multiplier(
input wire clk,
input wire rst_n,
input wire start,
input wire [`DATA_WIDTH - 1 : 0] a,
input wire [`DATA_WIDTH - 1 : 0] g,
... | 7.400944 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module Systolic_Processor (
output wire [15:0] result,
output wire [15:0] next_row_operand,
output wire delayed_done,
input wire [15:0] operand1,
input wire [15:0] operand2,
input wire [15:0] previous_StageOperand,
input wire start,
input wire reset, //to reset the state machine
i... | 7.430204 |
module
/*
Authour: Wang Lei, National University of Defense Technology, P.R.China.
This is the top module of systolic array in our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Lett... | 7.450309 |
module sys_array_basic #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //i
parameter ARRAY_L = 4
) //j
(
input clk,
input reset_n,
input param_load,
input [DATA_WIDTH*ARRAY_L-1:0] input_module,
input [DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] parameter_data,
output [2*DATA_WIDTH*ARRAY_... | 7.905776 |
module sys_array_cell #(
parameter DATA_WIDTH = 8
) (
input clock,
input reset_n,
input param_load,
input signed [DATA_WIDTH - 1:0] input_data,
input signed [2*DATA_WIDTH-1:0] prop_data,
input signed [DATA_WIDTH-1:0] param_data,
output reg signed [2*DATA_WIDTH-1:0] out_data,
output ... | 7.455479 |
module sys_array_fetcher #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //i
parameter ARRAY_L = 4
) //j
(
input clock,
input reset_n,
input load_params,
input start_comp,
input [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] input_data_a,
input [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] input_da... | 9.727713 |
module sys_array_wrapper #(
parameter DATA_WIDTH = 16,
parameter ARRAY_W = 10, //i
parameter ARRAY_L = 784, //j
parameter CLOCK_DIVIDE = 25
) (
input clk,
input reset_n,
input load_params,
input start_comp,
output [7:0] hex_connect
);
localparam MEM_SIZE = ARRAY_W * ARRAY_L;
... | 8.391784 |
module clock_divider #(
parameter DIVIDE_LEN = 23
) (
input clock,
output div_clock
);
reg [DIVIDE_LEN-1:0] cnt;
initial cnt <= {DIVIDE_LEN{1'b0}};
always @(posedge clock) begin
cnt <= cnt + 1'b1;
end
assign div_clock = cnt[DIVIDE_LEN-1];
endmodule
| 6.818038 |
module sys_bus (
input [31:0] cpu_imem_addr,
output [31:0] cpu_imem_data,
output [31:0] imem_addr, // cpu -> imem
input [31:0] imem_data, // imem -> cpu
input [31:0] cpu_dmem_addr, // device addr
input [31:0] cpu_dmem_data_in, // cpu -> device
input cpu_dmem_... | 7.303789 |
module sys_bus_model #(
parameter AXI_DW = 32, // data width (8,16,...,1024)
parameter AXI_AW = 32, // address width
parameter AXI_SW = AXI_DW >> 3 // strobe width - 1 bit for every data byte
) (
input sys_clk_i, // system clock
input sys_rst... | 8.012986 |
module sys_clk #(
parameter DIFF_CLKIN = "TRUE",
parameter CLKIN_PERIOD = 10.0, // default 100MHz
parameter MULT = 10, // 100 X 1 = 1000
parameter DIV0 = 8 // 1000 / 8 = 125
) (
input rst_i,
input sysclk_p_i,
input sysclk_n_i,
output sysclk_buf_o,
... | 7.141499 |
module sys_config (
wb_clk_i,
wb_rst_i,
wb_stb_i,
wb_cyc_i,
wb_we_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
sys_config_vector,
xtal_clk,
rtc_alarm
);
parameter BOARD_ID = 0;
parameter REV_MAJOR = 0;
parameter REV_MINOR = 0;
parameter REV_RCS = 0;
parameter RCS_... | 8.737465 |
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