code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sys_controler (
clk,
reset,
vsync,
mem_clr_finish,
mem_str_clr,
swap,
str_line_drawing,
select
);
input clk, reset, vsync, mem_clr_finish;
output reg mem_str_clr, swap, str_line_drawing, select;
always @(posedge clk or posedge reset) begin
if (reset) begin
swap <=... | 6.600462 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 15/8/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module Sys_counter (
input rst,
input proc_clk,
input freeze, //include when 1Hz timer implemented
input [3:0] count_sel,
output reg [31:0] count,
input [31:0] csr_wrdata,
input [3:0] wr_sel,
input csr_wr_en,
output tick_en
);
wire [63:0] proc_count_int;
wire [63:0] instr_c... | 7.74399 |
module counter_proc_clk (
out, // Output of the counter
clk, // clock Input
wr_en,
wr_en_h,
wr_data,
rd_cycle,
reset // reset Input
);
//----------Output Ports--------------
output [63:0] out;
//------------Input Ports--------------
input clk, reset, wr_en, wr_en_h, rd_cycle;
in... | 6.911442 |
module counter_real_clk (
out, // Output of the counter
clk, // clock Input
wr_en,
wr_en_h,
real_tick_en,
rd_time,
wr_data,
wr_tcmp_en,
timecmp,
reset // reset Input
);
//----------Output Ports--------------
output [63:0] out;
output [63:0] timecmp;
//------------Input... | 6.760345 |
module: cpu_cpld
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sys_ctrl_task(
clk,rst_n
);
output reg clk; //ʱź
output reg rst_n; //λź
parameter PERIOD = 20; //ʱڣλns... | 6.552299 |
module sys_i2c_fm (
i2c_sdat,
i2c_sclk
);
inout i2c_sdat;
input i2c_sclk;
wire akn;
reg akn_reg;
//Si sda en i2cc = 1, el bus a 1 o 0 segons akn. Si 0, 0.
assign i2c_sdat = (I_codec_avalon.I_controlador.i2cc_i.sda) ? akn : 0;
assign akn = akn_reg;
initial begin
akn_reg = 1;
end
tas... | 7.417626 |
module
module sys_io(
input clk,
input [7:0] io_addr,
output reg [7:0] io_dout,
input [7:0] io_din,
input io_we
);
reg [7:0] io_mem [255:0];
always @(posedge clk) begin
if (io_we)
io_mem[io_addr] <= io_din;
end
always @(*)
begin
io_dout = io_mem[io_addr];
end
endmo... | 6.917958 |
module sys_mmcm_clk_rst_sync (
clk_i_p,
clk_i_n,
rst_n_i,
sys_rst_n_o,
clk_100m,
clk_50m,
clk_25m,
clk_10m,
clk_5m
);
parameter RST_N_HOLD_CNT = 50;
input clk_i_p;
input clk_i_n;
input rst_n_i; // low active
output sys_rst_n_o; // low active
output clk_100m;
output ... | 9.517996 |
module sys_pll_0002 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_mu... | 6.567661 |
module sys_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
inp... | 6.97616 |
module sys_pll_sys_sdram_pll_0 (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire sys_clk_clk, // sys_clk.clk
output wire sdram_clk_clk, // sdram_clk.clk
output wire reset_source_reset // reset_source.reset
);
... | 6.588117 |
module sys_reset (
RSTn,
CLK,
DOUT
);
input RSTn;
input CLK;
output DOUT;
reg [15:0] count;
wire count_up;
always @(negedge RSTn or posedge CLK) begin
if (~RSTn) count <= 16'h0000;
else if (count_up == 1'b0) count <= count + 1;
end
// count_up <= '1' when count=X"FFFF" else '0';
... | 6.852544 |
module sys_reset_n #(
parameter N = 32, // debounce timer bitwidth
parameter MAX_TIME = 100, //us
parameter FREQ = 50 //model clock :Mhz
) (
input sys_clk,
input reset_n,
output sys_reset_n
);
localparam TIMER_MAX_VAL = 5000;
//----------------------------------------... | 8.145894 |
module sys_rst (
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localpar... | 7.896045 |
module sys_rst_fm (
Rst
);
output Rst; // Generated reset
reg Rst;
initial begin
Rst = 1;
end
// -----------------------------------------------------------------------------
// Task: sys.rstOn
// Asserts reset (Rst_n=0 & Rst=1)
// ------------------------------------------------------------... | 6.698598 |
module sys_rst_n (
input clk,
input rst_n,
output reg rst_syn
);
reg rst_syn1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rst_syn1 <= 1'b0;
else rst_syn1 <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rst_syn <= 1'b0;
else rst_syn <= ... | 7.440956 |
modules. //
// RUT will use limited SystemVerilog features which will help to develop the//
// library greatly. //
// ... | 7.062491 |
module sys_sig_gen (
masterClk,
masterRst,
sysclk,
nsysclk,
sdramclk,
sysRst
);
input masterClk;
input masterRst;
output sysclk;
output nsysclk;
output sdramclk;
output sysRst;
wire locked;
wire locked_Del;
reg [2:0] rstDel;
reg [2:0] rstDel2;
wire clk_nodelay;
wire ... | 6.9795 |
module SYS_TOP_TB ();
//parameters
parameter DATA_WIDTH = 8;
parameter REF_CLK_PER = 20;
parameter UART_RX_CLK_PER = 100;
parameter WR_NUM_OF_FRAMES = 3;
parameter RD_NUM_OF_FRAMES = 2;
parameter ALU_WP_NUM_OF_FRAMES = 4;
parameter ALU_NP_NUM_OF_FRAMES = 2;
//Testbench Signals
reg RST_N;
reg UAR... | 7.60416 |
module SyzFETFlagReg (
input clockSig,
input value,
input [3:0] sel,
input write,
input reset,
output [15:0] dOut
);
reg [15:0] data = 16'h0000;
// Delay buffer
wire wBuf;
buf #(1) (wBuf, value);
// Reset on rising reset signal, set data on falling clock signal
always @(negedge cl... | 6.528249 |
module SyzFETRegister2Out (
input [15:0] dIn,
input clockSig,
input read,
input write,
input reset,
output [15:0] dOut,
output [15:0] debugOut
);
reg [15:0] data = 16'h0000;
wire [15:0] wOutput;
wire [15:0] wBuf;
Buffer16B buf0 (
.dIn (dIn[15:0]),
.dOut(wBuf[15:0])
)... | 7.397064 |
module handles the data clock output from the ADC and provides the
// necessary signals required by the ISERDES input buffers.
//
//------------------------------------------------------------------------
// Copyright (c) 2017 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person o... | 7.227301 |
module for use with the SYZYGY DAC sample. Allows
// control of the AM depth.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associate... | 6.836922 |
module for use with the SYZYGY DAC sample. Allows
// control of the FM Deviation.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and assoc... | 6.836922 |
module syzygy_dac_phy (
input wire clk,
input wire reset,
input wire [11:0] data_i,
input wire [11:0] data_q,
output wire [11:0] dac_data,
output wire dac_clk
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT (1'b0), /... | 6.897113 |
module syzygy_dac_tb ();
reg clk, reset;
wire [11:0] dac_data;
wire dac_clk, dac_reset_pinmd, dac_sclk, dac_sdio, dac_cs_n;
`define T_Clk 8 // 8ns clock period (125 MHz)
// clock generation
initial begin
clk = 0;
forever begin
#(`T_Clk) clk = 1'b1;
#(`T_Clk) clk = 1'b0;
end
en... | 7.141031 |
module for the SYZYGY DAC Pod sample. This module
// contains the DAC DDS, PHY, and controller.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this soft... | 7.878554 |
module syzygy_dds_fp (
input wire clk,
input wire reset,
input wire dis_out,
input wire [31:0] freq,
input wire [31:0] phase,
input wire [27:0] inc_delta,
output reg [11:0] data
);
// CORDIC
reg [69:0] delta;
reg [31:0] counter;
reg [31:0] freq_r, phase_r;
reg [11:0] cordic_ou... | 7.774741 |
module will read in data from a BRAM generator module and output
// a data signal for a DAC channel. The BRAM has a 32-bit data interface
// which is split into two 16-bit interfaces each truncated to 12-bits.
// This means that the usable depth of the BRAM is essentially double the
// depth setting on the BRAM.
//
//... | 8.488121 |
module sz (
input rst,
input clk
);
parameter TYPE = 'b00; //00:float; 01:double; 10: int; 11: float
parameter WIDTH = 32;
parameter OUT_WIDTH = 2;
//parameter ERROR = 0.0001; //absolute error
//stream data in from DRAM; having a FIFO/buffer to store
wire [WIDTH-1:0] data_in, dram_in, dram_out;... | 7.221755 |
module from Digilent. Implements
// an I2S master for the PMOD-I2S2 ADC.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated doc... | 7.306128 |
module for the PMOD-I2S2 PHY from Digilent. Outputs mono audio
// data.
//
//------------------------------------------------------------------------
// Copyright (c) 2018 Opal Kelly Incorporated
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated docu... | 8.012345 |
module szznew (
LED_Hr,
LED_Min,
LED_Sec,
ALARM,
_1kHzIN,
Adj_Min_key,
Adj_Hour_key,
Set_Min_key,
Set_Hr_key,
Ctrl_Bell,
Mode,
LED_Min1,
LED_Min2,
LED_Hr1,
LED_Hr2,
YYY
);
input _1kHzIN;
input YYY;
output [7:0] LED_Hr, LED_Min, LED_Sec;
output [6:0... | 8.263203 |
module Divier_50MHz_2Hz (
input CR,
CLK_50M,
output reg CLk_1HzOut
);
reg [24:0] Count_Div;
always @(posedge CLK_50M or negedge CR) begin
if (!CR) begin
CLk_1HzOut <= 0;
Count_Div <= 0;
end else begin
// if(Count_Div<(50000000/(2*100))) //20Hz
if (Count_Div < 5) Count_... | 6.710338 |
module _2to1MUX (
OUT,
SEL,
X,
Y
);
input [7:0] X, Y;
input SEL;
output [7:0] OUT;
assign OUT = SEL ? X : Y;
endmodule
| 7.664288 |
module _4bitComparer (
EQU,
A,
B
);
input [3:0] A, B;
output EQU;
assign EQU = (A == B);
endmodule
| 7.754256 |
module Divided_Frequency (
_1HzOut,
_2HzOut,
_500HzOut,
nCR,
EN,
_1kHzIN
);
input _1kHzIN, nCR, EN;
output _1HzOut, _2HzOut, _500HzOut;
wire [11:0] Q;
wire EN1, EN2;
counter10 DU0 (
Q[3:0],
nCR,
EN,
_1kHzIN
);
counter10 DU1 (
Q[7:4],
nCR,
E... | 6.690209 |
module counter6 (
Q,
nCR,
EN,
CP
);
input CP, nCR, EN;
output [3:0] Q;
reg [3:0] Q;
always @(posedge CP or negedge nCR) begin
if (~nCR) Q <= 4'b0000;
else if (~EN) Q <= Q;
else if (Q == 4'b0101) Q <= 4'b0000;
else Q <= Q + 1'b1;
end
endmodule
| 6.765105 |
module sz_ex (
//sign or zero extended value
output reg [(`BUS_WIDTH - 1):0] sz_ex_out,
//sign or zero extend select
input sz_ex_sel,
//sign or zero extend mode
input [1:0] sz_ex_mode,
//immediate value
input [(`IMMEDIATE_WIDTH -1):0] imm
);
//combinational logic
always @(*) begin
... | 7.547605 |
module sz_ex_tb;
// Inputs
reg sz_ex_sel;
reg [1:0] sz_ex_mode;
reg [19:0] imm;
// Outputs
wire [31:0] sz_ex_out;
// Instantiate the Unit Under Test (UUT)
sz_ex uut (
.sz_ex_out(sz_ex_out),
.sz_ex_sel(sz_ex_sel),
.sz_ex_mode(sz_ex_mode),
.imm(imm)
);
initial begin
// ... | 6.915071 |
module s_acq_change (
rst_n,
clk_sys,
change,
s_load,
s_loadin1,
s_loadin2,
s_rst,
s_rstin1,
s_rstin2,
//s_start,
//s_startin1,
//s_startin2,
s_acqnum,
s_acqnumin1,
s_acqnumin2,
s_stripnum,
s_stripnumin1,
s_stripnumin2
);
input rst_n;
input cl... | 6.778593 |
module S_ADD #(
P = 8
) ( //SUMADOR EXPONENTE FORMATO PUNTO FLOTANTE EN 32 BITS
input wire [P-1:0] A, //ENTRADA A
input wire [ 4:0] B, //ENTRADA B
output wire [P-1:0] Y //SALIDA Y
);
assign Y = A + B; //SUMA DE ENTRADAS
endmodule
| 7.230735 |
module S_BOX (
clk,
addr,
out
);
input wire clk;
input wire [7:0] addr;
output reg [7:0] out;
reg [7:0] rom[0:255];
initial begin
$readmemh("S_BOX.txt", rom);
end
always @(posedge clk) begin
out <= rom[addr];
end
//assign out=out_reg;
endmodule
| 6.623843 |
module performs the function of the S-Boxes on the whole vector.
module S_Boxes(
input [47:0] i_vector,
output [31:0] o_vector
);
S_Box_1 S_Box_1_inst
(
.i_vector(i_vector[5:0]) , // input [5:0] i_vector[:]
.o_vector(o_vector[3:0]) // output [3:0] o_vector[:]
);
S_Box_2 S_Box_2_inst
(
.i_... | 7.634754 |
module performs the function of the S-Box 1.
module S_Box_1(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 14;
6'b000001 : o_vector = 0;
6'b000010 : o_vector = 4;
6'b000011 : o_vector = 15;
6'b000100 : o_vector = 13;
6'b000101 : ... | 7.634754 |
module performs the function of the S-Box 2.
module S_Box_2(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 15;
6'b000001 : o_vector = 3;
6'b000010 : o_vector = 1;
6'b000011 : o_vector = 13;
6'b000100 : o_vector = 8;
6'b000101 : o... | 7.634754 |
module performs the function of the S-Box 3.
module S_Box_3(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 10;
6'b000001 : o_vector = 13;
6'b000010 : o_vector = 0;
6'b000011 : o_vector = 7;
6'b000100 : o_vector = 9;
6'b000101 : o... | 7.634754 |
module performs the function of the S-Box 4.
module S_Box_4(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 7;
6'b000001 : o_vector = 13;
6'b000010 : o_vector = 13;
6'b000011 : o_vector = 8;
6'b000100 : o_vector = 14;
6'b000101 : ... | 7.634754 |
module performs the function of the S-Box 5.
module S_Box_5(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 2;
6'b000001 : o_vector = 14;
6'b000010 : o_vector = 12;
6'b000011 : o_vector = 11;
6'b000100 : o_vector = 4;
6'b000101 : ... | 7.634754 |
module performs the function of the S-Box 6.
module S_Box_6(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 12;
6'b000001 : o_vector = 10;
6'b000010 : o_vector = 1;
6'b000011 : o_vector = 15;
6'b000100 : o_vector = 10;
6'b000101 :... | 7.634754 |
module performs the function of the S-Box 7.
module S_Box_7(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 4;
6'b000001 : o_vector = 13;
6'b000010 : o_vector = 11;
6'b000011 : o_vector = 0;
6'b000100 : o_vector = 2;
6'b000101 : o... | 7.634754 |
module performs the function of the S-Box 8.
module S_Box_8(
input [5:0] i_vector,
output reg [3:0] o_vector
);
always @*
case (i_vector)
6'b000000 : o_vector = 13;
6'b000001 : o_vector = 1;
6'b000010 : o_vector = 2;
6'b000011 : o_vector = 15;
6'b000100 : o_vector = 8;
6'b000101 : o... | 7.634754 |
module is a test bench for the s_box. The output of test bench is
// a pass or fail results passed on the obtained values.
module s_box_tb;
reg [7:0] inputValue1;
reg [7:0] inputValue2;
reg [7:0] inputValue3;
reg [7:0] expectedValue1;
reg [7:0] expectedValue2;
reg [7:0] expectedValue3;
wire [7:0] outputValue1;
w... | 6.595812 |
module s_bsc (
in,
out,
sdi,
sdo,
shift,
update,
clock,
brk
);
input [2:0] in;
input sdi, shift, update, clock, brk;
output [2:0] out;
output sdo;
wire di0, di1;
bsc
bsc0 (
sdi,
di0,
shift,
update,
clock,
in... | 6.584125 |
module S_Buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synops... | 6.730376 |
module cpen4 (
e,
nz,
w
);
output [1:0] e;
output nz;
input [3:0] w;
assign #`da nz = |w[3:0];
assign #`da e[0] = (w[3:2] == 2'b01) || (w[3:0] == 4'b0001);
assign #`da e[1] = (w[3:2] == 2'b00);
endmodule
| 6.575312 |
module S_Const (
input nReset,
input Clk,
input [15:0] Bandwidth, // kHz
output reg [17:0] a
);
parameter fs = 18'd50_000; // f_Clk [kHz]
parameter fs_2 = 16'd25_000; // fs / 2
reg [ 1:0] state;
reg [15:0] bw;
reg [17:0] mask;
reg [17:0] x;
reg [17:0] y;
wire [35:0] z;
... | 6.817469 |
module s_core(
//input wire clk ,
//input wire rst_n,
////pc
//input wire i_stall,
//input wire i_is_branch_true,
//input wire i_writing_first_addr,
//input wire[31:0] i_instr_start_addr,
////instr_mem
//input wire re,
//input wire is_write,
//input wire[31:0] im_inst,
////regs
//input wire write_en,
//input wire... | 6.660202 |
module forwarding (
input wire [4:0] ID_EX_rs2,
input wire [4:0] ID_EX_rs1,
input wire [6:0] ex_mem_opcode,
input wire ex_mem_REG_write_en,
input wire mem_wb_REG_write_en,
input wire [4:0] EX_MEM_rd,
input wire [4:0] MEM_WB_rd,
output wire [1:0] forward_mux1,
output wire [1:0] forwar... | 6.668885 |
module branch_prediction (
input wire clk,
input wire rst_n,
input wire [1:0] br_taken,
input wire [6:0] IF_ID_op,
input wire [6:0] ID_EX_op,
output wire branch_predict
);
//wire [1:0]branch_predict; /00 01 branch 10 11 branch no taken =11 not taken =00
//assign branch_p... | 6.779337 |
module hazard_detection (
input wire [4:0] ID_EX_rd,
input wire [4:0] IF_ID_rs1,
input wire [4:0] IF_ID_rs2,
input wire ID_EX_read_enable,
output wire hazard_detection
);
assign hazard_detection=(ID_EX_read_enable==1'b1 && ( ID_EX_rd==IF_ID_rs1 || ID_EX_rd==IF_ID_rs2 ))?1'b1:1'b0;
endmodule
... | 6.869872 |
module s_counter #(
// asclk frequency
parameter CLOCK_CYCLE_MHZ = 160
) (
// AXI ports
input asclk,
input aresetn,
output reg [`OPENFLOW_LAST_SEEN_WIDTH-1:0] s_counter,
output reg [9:0] ms_counter,
output reg [9:0] us_counter
);
//------------------------ Wires/Regs ----------------... | 7.993778 |
module S_Coupling (
input nReset,
input Clk, // 45 MHz
input [23:0] Input, // 2's Compliment
output [23:0] Output, // 2's Compliment
input Coupling
); // 1 = AC (1 Hz), 0 = DC
wire [23:0] DC;
wire [23:0] AC;
ACDC #(24, 24, 8) ACDC1 (
nReset,
Clk,
Input,
AC,
... | 6.706154 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end ... | 6.615218 |
module S_Ext16 (
input [15 : 0] simem15_0,
output [31 : 0] sto_mux4
);
assign sto_mux4 = {{(16) {simem15_0[15]}}, simem15_0};
endmodule
| 6.910846 |
module S_Ext18 (
input [15:0] data_in,
output [31:0] data_out
);
assign data_out = {{14{data_in[15]}}, data_in, 2'b00};
endmodule
| 6.680344 |
module S_Ext8 (
input [ 7:0] data_in,
output [31:0] data_out
);
assign data_out = {{24{data_in[7]}}, data_in};
endmodule
| 7.829551 |
module S_EXTEND (
IF_ID_instr_immed,
signext_out
);
input [15:0] IF_ID_instr_immed;
output [31:0] signext_out;
// Repeat most significant bit to pad
assign signext_out = {{16{IF_ID_instr_immed[15]}}, IF_ID_instr_immed};
endmodule
| 7.868308 |
module S_Filter (
input nReset,
input Clk, // 45 MHz
input [23:0] Input,
output reg [23:0] Output,
input [17:0] a
); // 2^18 - a
// H(z) = --------------
// 2^18 - a*z^-1
reg [23:0] xn;
reg [43:0] yn_1;
wire [44:0] yn;
wire [17:0] b;
wire [41:0] bx;
... | 6.661484 |
module S_FlipFlop(S, B, D, T, I, CLK);
output S;
input [11:0]B, [7:0]D, [7:0]T, I, CLK;
wire j, k;
assign j = D[7] & ~I & T[3] & B[0];
assign k = 1'b0;
JK_FLipFlop jkff(S, j, k, CLK);
endmodule
| 7.050833 |
module s_p (
input wire clk,
input wire rst_n,
input wire [ 33:0] data_in_1,
output reg [135:0] data_out_1,
output reg s_p_flag_out
);
reg [33:0] R0;
reg [33:0] R1;
reg [33:0] R2;
reg [33:0] R3;
reg [33:0] R4;
reg [33:0] R5;
reg [33:0] R6;
reg [33:0] R... | 7.481532 |
modules
module s_reg (clk,
reset,
datai,
datao,
load,
up,
cnt_enb);
input clk; // we use the IEEE standard 1164 logic types. + and - operators
input reset;
input [7:0] datai; // data bus in
output [7:0] datao; // data bus out
input load; // load enable
input up; // 1=count up, 0=... | 6.749981 |
module tb ();
parameter WIDTH_KEY = 256;
parameter WIDTH_DATA = 128;
// clock generator settings:
parameter cycles_reset = 2; // rst active (clk)
parameter clk_period = 10; // clk period ns
parameter clk_delay = 0; // clk initial delay
reg clk; // clock
reg rst; // sync reset
reg [WIDTH_KEY-... | 7.147559 |
module S_SUBT #(
P = 8,
W = 5
) //RESTADOR EXPONENTE FORMATO PUNTO FLOTANTE EN 32 BITS
(
input wire [P-1:0] A, //ENTRADA A
input wire [W-1:0] B, //ENTRADA B
output wire [P-1:0] Y //SALIDA Y
);
assign Y = A - B; //RESTA DE ENTRADAS
endmodule
| 7.016327 |
module s_table_ROM (
input clk,
input rd,
input [7:0] address,
output [7:0] sub_val
);
parameter ROM_WIDTH = 8;
parameter ROM_ADDR_BITS = 8;
(* rom_style="{distributed | block}" *)
reg [ROM_WIDTH-1:0] substitution_table[(2**ROM_ADDR_BITS)-1:0];
reg [ROM_WIDTH-1:0] s_value;
wire [ROM_ADDR... | 7.092453 |
module s_to_p_tb ();
// Tak
localparam IN_WIDTH = 8;
localparam OUT_WIDTH = 4;
reg clk;
reg rst;
reg [IN_WIDTH-1:0] i_data;
reg i_valid;
wire i_ready;
wire [IWIDTH*OWIDTH-1:0] o_data;
wire o_valid;
reg o_ready;
s_to_p uut (
.clk (clk),
.rst (rst),
.i_data (i_data),
... | 7.148499 |
module converts the input, represented in sign-magnitude format, to two's complement format.
For example: input = 100110
the first bit of the input being one indicates that it is a negative number.
the output in this case will be the negative(two's complement) of 000110 (absolute value of in... | 6.747013 |
module S_transmit (
input CLOCK,
input [2:0] color,
output reg O_TX_SERIAL
);
// input [7:0]TX_BYTE removed for now may be added later
// Time period 20ns freq = 50MHz
parameter clks_per_bit = 434;
parameter IDLE = 3'b000;
parameter TX_START_BIT = 3'B001;
parameter TX_DATA_BITS = 3'b011;
para... | 7.734834 |
module S_Trigger (
input nReset,
input Clk, // 45 MHz
input [15:0] Input,
output Output,
input [15:0] Level,
input [15:0] Hyst,
input Slope
); // 1 = Positive , 0 = Negative
reg tOutput;
wire [17:0] x2;
wire [17:0] x3;
wire [18:0] x4;
wire [17:0] x5;
wire [1... | 7.275886 |
module TXctl0 ( /* in */
RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5,
SCLKg6,
SP_EN,
SP_ENg,
TFSsm,
TSack,
Twrap,
SLEN,
MWORD,
TBUF,
logTX,
MTTX_E,
DMD,
AUlaw_en,
SLEN_ex,
FSi_set,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD,
TSreq,
IST,
... | 6.623283 |
module TXctl1 ( /* in */
RST,
DSPCLK,
GO_Cx,
EX_en,
SCLKg5,
SCLKg6,
SP_EN,
SP_ENg,
TFSsm,
TSack,
Twrap,
SLEN,
MWORD,
TBUF,
SLEN_ex,
FSi_set,
/*logTX,*/ MTTX_E,
DMD,
`ifdef FD_DFT
SCAN_TEST,
`endif
TD,
TSreq,
IST,
TX,
SLOT_N... | 6.562916 |
module
module S_type(
input [31:0] instr,
input [31:0] daddr,
output reg[3:0] we
);
always@(instr or daddr)
begin
case(instr[14:12])
3'b000: we = (4'b0001)<<daddr[1:0]; //SB
3'b001: we = (4'b0011)<<daddr[1:0]; //SH
3'b010: we = 4'b1111; //... | 6.806973 |
module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2013
// The RS-232 settings are fixed
// TX: 8-bit data, 2 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX... | 6.83375 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 10000000;
parameter Baud = 500000;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log... | 7.463142 |
module s_up_counter (
L,
clk
);
input clk;
output [3:0] L;
wire qbar;
JK_FF ff1 (
1,
1,
L[0],
qbar,
clk
);
JK_FF ff2 (
L[0],
L[0],
L[1],
qbar,
clk
);
JK_FF ff3 (
L[0] & L[1],
L[0] & L[1],
L[2],
qbar,
clk
... | 6.748693 |
module JK_FF (
J,
K,
Q,
NQ,
CLK
);
input J, K, CLK;
output Q, NQ;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
if (J == 0 & K == 0) begin
Q <= Q;
NQ <= NQ;
end else if (J == 1 & K == 0) begin
Q <= 1;
NQ <= 0;
end ... | 6.615218 |
module
module main (
input wire CLOCK_50, //On Board 50 MHz
input wire [9:0] SW, // On board Switches
input wire [3:0] KEY, // On board push buttons
output wire [6:0] HEX0, // HEX displays
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wir... | 9.001229 |
module top (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
t_flipflop u1 (
SW[0],
SW[1],
SW[9],
LEDR[0]
);
endmodule
| 6.514573 |
module t (
output reg Q,
input T,
clk
);
wire DT = Q ^ T;
dff d (
T,
clk,
DT
);
endmodule
| 6.866031 |
module tbox0 (
input [7:0] index,
output [31:0] tbox
);
reg [7:0] mem[0:255];
wire [7:0] sbox;
wire [7:0] galois;
initial begin
$readmemh("T0.hex", mem);
end
assign sbox = mem[index];
assign galois = {sbox[6:0], 1'b0} ^ (sbox[7] ? 8'h1b : 8'h00);
assign tbox = {galois ^ sbox, sbox,... | 6.520176 |
module setbit (
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
);
wire LED1;
wire LED2;
wire LED3;
wire LED4;
wire LED5;
wire LED6;
wire LED7;
wire LED8;
//-- Implementacion: el pin deseado esta cableado a '1'
... | 8.044466 |
module setbit_tb;
//-- Cable para conectar al componente que pone
//-- el bit a uno
wire LED1;
//--Instanciar el componente. Conectado al cable A
setbit SB1 (.LED1(LED1));
//-- Comenzamos las pruebas
initial begin
//-- Definir el fichero donde volvar los datos
//-- para ver graficamente la sal... | 7.100034 |
module coeff_rom (
input clk,
input rstn,
input [13:0] aa,
input cena,
output reg [`W_WT1P*4-1:0] qa
);
logic [0:`TILE_WIDTH*`TILE_WIDTH-1][31:0] mem = {
256,
-896,
-4096,
-640,
832,
3200,
3328,
-1344,
576,
2624,
1600,
-2752,
4416,
-1408,
... | 7.054666 |
modules ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyr... | 8.868608 |
module t2600_bus (
address,
data_from_cpu,
cpu_rw_mem,
riot_data,
rom_data,
tia_data,
address_riot,
address_rom,
address_tia,
data_to_cpu,
enable_riot,
enable_rom,
enable_tia,
rw_mem
);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
lo... | 7.133484 |
module t2600_bus_tb ();
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
localparam [3:0] RIOT_ADDR_SIZE_ = 4'd6;
localparam [3:0] TIA_ADDR_SIZE_ = 4'd5;
// these 3 registers are kind of d... | 7.863261 |
module t2600_kb_tb ();
// all inputs are regs
reg clk;
reg reset_n;
reg kd;
reg kc;
// all outputs are wires
wire [15:0] io_lines;
always #10 clk <= ~clk;
initial begin
clk = 1'b0;
reset_n = 1'b1;
kd = 1'b0;
kc = 1'b0;
#10;
reset_n = 1'b0;
#40000;
$finish;
end
... | 7.164282 |
module T2D (
input A,
B,
input S2,
output X
);
assign X = S2 ? ~A : ~B; // tmax = 2.7ns
endmodule
| 7.372875 |
module tbox3 (
input [7:0] index,
output [31:0] tbox
);
reg [31:0] mem[0:255];
initial begin
$readmemh("T3.hex", mem);
end
assign tbox = mem[index];
endmodule
| 6.770137 |
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