code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module T34 (
input [2:0] A,
input [2:0] B,
input [2:0] C,
input [2:0] D,
output X
);
assign X = ~|{&{A}, &{B}, &{C}, &{D}}; // tmax = 3.3ns
endmodule
| 6.81509 |
module T35seg7_top (
clockIn, // 50MHz input from onboard oscillator
// n_reset, // Uncomment to have an external reset
dp, // 7 segment display decimal point
segment7
); // 7 segment display, main LEDs
input clockIn;
// input n_reset; // Uncomment to have an extern... | 7.037491 |
module T3TE8_V (
input input1,
input input2,
input input3,
input inputen,
output reg [7:0] output1
// output output2,
// output output3,
// output output4,
// output output5,
// output output6,
// output output7,
// output output8
);
always @* begin... | 7.494971 |
module simpleand (
a,
b,
c
);
input a, b;
output c;
reg c;
always @(*) c = a & b;
endmodule
| 7.04245 |
module t48_p1 (
input clk_i,
input res_i,
input en_clk_i,
input [7:0] data_i,
input write_p1_i,
input read_p1_i,
input read_reg_i,
input [7:0] p1_i,
output [7:0] data_o,
output [7:0] p1_o,
output p1_low_imp_o
);
wire [7:0] p1_q;
wire low_imp_q;
wire n4671_o;
wire n467... | 7.072742 |
module T4L4 (
A,
B,
out1,
out2
);
input [3:0] A, B;
output out1, out2;
assign out1 = (A > B) ? 1 : 0;
assign out2 = (A == B) ? 1 : 0;
endmodule
| 7.10832 |
module: T4L4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T4L4_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire out1;
wire out2;
// Instantiate the Unit Under Tes... | 6.946819 |
module T5A (
input A1,
A2,
input B1,
B2,
input S2,
S6,
output X
);
wire mux_A = S2 ? A1 : A2;
wire mux_B = S2 ? B2 : B1;
assign X = ~(S6 ? mux_A : mux_B); // tmax = 3.3ns
endmodule
| 7.869936 |
module t5_t6 (
v0,
v1,
v2,
v3,
sp0,
sp1,
sp2,
sp3,
clock_25,
clock_maior,
rst,
att_color,
data_color,
blue,
green,
red
);
// Sinais básicos de controle
input clock_25, rst;
// Vetores com as flags indicando a presenca dos sprites em cada uma das 16... | 7.632149 |
module T6507LP_ALU_TestBench (
input dummy,
output error
);
`include "T6507LP_Package.v"
reg clk_i;
reg n_rst_i;
reg alu_enable;
wire [7:0] alu_result;
wire [7:0] alu_status;
reg [7:0] alu_opcode;
reg [7:0] alu_a;
//`include "T6507LP_Package.v"
T6507LP_ALU DUT (
.clk_i(clk_i),
... | 6.651387 |
module t6507lp_alu_wrapper ();
parameter [3:0] DATA_SIZE = 4'd8;
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
// all inputs are regs
reg clk;
reg reset_n;
reg alu_enable;
reg [DATA_SIZE_:0] alu_opcode;
reg [DATA_SIZE_:0] alu_a;
// all outputs are wires
wire [DATA_SIZE_:0] alu_result;
wire ... | 6.937868 |
module t6532_tb ();
// mem_rw signals
localparam MEM_READ = 1'b0;
localparam MEM_WRITE = 1'b1;
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
reg clk... | 7.807723 |
module t7 (
input wire [7:0] FIFO_Red,
input wire [7:0] FIFO_Green,
input wire [7:0] FIFO_Blue,
input wire [7:0] Sprites_Red,
input wire [7:0] Sprites_Green,
input wire [7:0] Sprites_Blue,
output wire [7:0] VGA_R,
output wire [7:0] VGA_G,
output wire [7:0] VGA_B
);
assign VG... | 6.868072 |
module z80 (
// Outputs
m1_n,
mreq_n,
iorq_n,
rd_n,
wr_n,
rfsh_n,
halt_n,
busak_n,
A,
dout,
// Inputs
reset_n,
clk,
wait_n,
int_n,
nmi_n,
busrq_n,
di
);
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_... | 7.014568 |
module ta151_bar (
input D0, //
input D1, //
input D2, //
input D3, //
input D4, //
input D5, //
input D6, //
input D7, //
input A, //
input B, //
input C, //
input EN_BAR, //
output Y, ... | 8.179456 |
module ta161_bar (
input CLR_BAR, // CLEAR
input LD_BAR, // LOAD
input ENT, // ENABLE T
input ENP, // ENABLE P
input CLK, // CLK
input A,
B,
C,
D, // DATA IN
output QA,
QB,
QC,
QD, // DATA OUT
output RCO // RIPPLE CARRY OUTPUT
);
... | 7.474988 |
module ta181_bar (
input A3_BAR,
A2_BAR,
A1_BAR,
A0_BAR, // WORD 1
input B3_BAR,
B2_BAR,
B1_BAR,
B0_BAR, // WORD 2
input S3,
S2,
S1,
S0, // FUNCTION SELECT
input M, // MODE: 0 is arithmetic, 1 is logic
input CI, // CARRY IN
output F3_BAR,
... | 7.423474 |
module main (
input vd9b5c7,
input va55d5a,
input v006143,
output vfe8161
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign w0 = vd9b5c7;
assign w2 = va55d5a;
assign w4 = v00614... | 7.081372 |
module main_logic_gate_and (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
main_logic_gate_and_basic_code_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
| 8.037914 |
module main_logic_gate_and_basic_code_vf4938a (
input a,
input b,
output c
);
// AND logic gate
assign c = a & b;
endmodule
| 8.037914 |
module main_logic_gate_or (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
main_logic_gate_or_basic_code_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
| 8.037914 |
module main_logic_gate_or_basic_code_vf4938a (
input a,
input b,
output c
);
// OR logic gate
assign c = a | b;
endmodule
| 8.037914 |
module main_logic_gate_not (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
main_logic_gate_not_basic_code_vd54ca1 vd54ca1 (
.a(w0),
.c(w1)
);
endmodule
| 8.037914 |
module main_logic_gate_not_basic_code_vd54ca1 (
input a,
output c
);
// NOT logic gate
assign c = ~a;
endmodule
| 8.037914 |
module TableArray(ADDR1,DOUT1,ADDR2,DIN,WE,CLK);
parameter DBITS; // Number of data bits
parameter ABITS; // Number of address bits
parameter WORDS = (1<<ABITS);
parameter MFILE = "";
input [(ABITS-1):0] ADDR1, ADDR2;
input [(DBITS-1):0] DIN;
output reg [(DBITS-1):0] DOUT1;
input CLK,WE;
(* ram_init... | 6.948297 |
module TableRAM #(
parameter FILE = "inittab.list",
parameter rows = 30,
parameter cols = 40,
parameter addr_width = 11, // log2(rows*cols)
parameter nsprites = 8 // cambiar nombre por spr_width = log2(nsprites)
) (
input wire clk... | 7.038891 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module table_control #(
parameter n_words = 40
) (
input clk
, input ctrl_reset_n
, input [26:0] tdatai // dispatch intf to tables
, input [14:0] twraddr
, input [ 2:0] twren
, output [26:0] tdata_0
, output [26:0] tdata_1
, output [26:0] tdata_2
, input [1:0] command
... | 7.469282 |
module table_control_test ();
reg clk;
reg rstb;
wire [26:0] tdata_0, tdata_1, tdata_2;
reg [1:0] command;
initial begin
clk = 0;
rstb = 0;
command = 0;
#1 rstb = 1;
#8 command = 2'b01;
#8 command = 0;
#400 command = 2'b01;
#8 command = 0;
#104 command = 2'b11;
#8 ... | 7.469282 |
module Table_Generator_Test;
//Period of the clock
localparam PERIOD = 100;
//Registers given as input to the module
reg clk = 1'b0, rst = 1'b0;
reg [3:0] r_value = 4'b0;
reg [7:0] coefficient = 7'b0;
reg is_new_coefficient = 1'b0;
//Outputs of the module
wire [64*8-1:0] value;
wire valid;
//Ch... | 8.152887 |
module TABLE_READER (
EN,
STRING,
NOW_STATE_IN,
NOW_STATE_OUT,
EN_MATCH,
INITIALIZE
);
input EN;
input INITIALIZE;
input [3:0] STRING;
input [7:0] NOW_STATE_IN;
output [7:0] NOW_STATE_OUT;
output EN_MATCH;
integer i, j, k, l;
integer m, n, o, p;
reg EN_MATCH;
reg [7:0] ADDR... | 7.49324 |
module table_walk (
input wire in_clk, // from MMU
input wire in_en, // from MMU
input wire [13:0] in_mva, // from MMU
output wire [13:0] out_paddr, // to MMU
input wire [31:0] in_mcu_data, // from MCU
output wire out_mcu_ren, // to MCU
output wire [13... | 6.952107 |
module top (
input clk,
io_resetn,
output io_trap,
output io_mem_axi_awvalid,
input io_mem_axi_awready,
output [31:0] io_mem_axi_awaddr,
output [ 2:0] io_mem_axi_awprot,
output io_mem_axi_wvalid,
input io_mem_axi_wready,
output [31:0] io_mem_axi_w... | 7.233807 |
module delay4 #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
reg [WIDTH-1:0] q1, q2, q3;
always @(posedge clk) begin
q1 <= in;
q2 <= q1;
q3 <= q2;
out <= q3;
end
endmodule
| 6.625308 |
module to instantiate in a higher level file is qc16.
//
module digitalfilter(output out, input clk, input ce, input in);
reg [5:0] taps = 6'b000000;
reg result = 0;
assign out = result;
always @(posedge clk)
begin
if(ce)
begin
taps[5] <= taps[4];
taps[4] <= taps[3];
... | 7.261131 |
module qc16 (
output [7:0] counth,
output [7:0] countl,
input [1:0] tach,
input clk,
input freeze,
input invphase
);
wire [15:0] counter;
wire up;
wire down;
reg [1:0] adjtach;
// Swap tach signals if invphase is true
always @(*) begin
if (invphase) begin
adjtach[0] = ta... | 6.633667 |
module debounces push buttons switches
//The input is active low and will output high when a button is pushed
//Improvements to be made:
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
//**** This module instantiation *************************
//********************************************************
//<>... | 7.514676 |
module half_adder (
Cout,
Sum,
A,
B
);
input A, B;
output Sum, Cout;
xor xor1 (Sum, A, B);
and and1 (Cout, A, B);
endmodule
| 6.966406 |
module specialized_half_adder (
Cout,
Sum,
A,
B
);
input A, B;
output Sum, Cout;
assign Cout = A | B;
assign Sum = !(A ^ B);
endmodule
| 6.74416 |
module reduced_full_adder (
Cout,
A,
B,
Cin
);
input A, B, Cin;
output Cout;
assign Cout = (A & (B | Cin)) | (B & Cin);
endmodule
| 6.562916 |
module Tag2Len #(
parameter TAG_WIDTH = 2,
parameter LEN_WIDTH = 3
) (
input [TAG_WIDTH - 1 : 0] tag,
output reg [LEN_WIDTH - 1 : 0] len
);
always @(tag)
case (tag)
2'b00: len = 3'b000;
2'b01: len = 3'b001;
2'b10: len = 3'b010;
2'b11: len = 3'b100;
defau... | 6.937434 |
module tagArray (
input clk,
input reset,
input [7:0] we,
input [23:0] tag,
output [23:0] tagOut0,
output [23:0] tagOut1,
output [23:0] tagOut2,
output [23:0] tagOut3,
output [23:0] tagOut4,
output [23:0] tagOut5,
output [23:0] tagOut6,
output [23:0] tagOut7
);
tagBlock... | 7.079652 |
module TagCompare (
Tag1,
Tag2,
CompVal
);
input [2:1] Tag1;
input [2:1] Tag2;
output CompVal;
assign CompVal = !(Tag1[1] ^ Tag2[1]) & !(Tag1[2] ^ Tag2[2]);
endmodule
| 7.348011 |
module that is responsible for controlling the operations of the TAGE predictor, you can pipeline the operations for higher speedup
module TAGE_Controller(CLK,reset,
index_tag_enable,instruction_inc_en,table_read_en, update_enable, update_predictor_enable);
input CLK,reset;
output reg index_tag_enable; //Thi... | 7.34132 |
module TAGE_Table (
Clk,
wr,
rd,
index,
rdata_tag_bits,
rdata_u_bits,
rdata_c_bits,
wdata_tag_bits,
correct_prediction,
inc_u_bit,
dec_u_bit,
inc_c_bit,
dec_c_bit,
alloc,
update_enable
);
parameter IL = 10; //Index size ie number of addresses
parameter t... | 6.732136 |
module tagfifo (
clock,
reset,
RB_Tag,
RB_Tag_Valid,
Rd_en,
Tag_Out,
tagFifo_full,
tagFifo_empty,
increment
);
parameter DSIZE = 5;
parameter ASIZE = 6; // ASIZE = Max_number -1
output [DSIZE-1:0] Tag_Out;
output tagFifo_full;
output tagFifo_empty;
input [DSIZE-1:0] RB... | 7.328335 |
module tagMux_256x1 (
output reg [11:0] out,
input [3071:0] inp,
input [7:0] select
);
integer i;
always @(inp or select) begin
for (i = 0; i < 12; i = i + 1) out[i] <= inp[select*12+i];
end
endmodule
| 7.02925 |
module tagram_1k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [5:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // W... | 6.803194 |
module tagram_2k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Wr... | 7.235402 |
module tagram_2k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // W... | 6.847755 |
module tagram_2k3way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Wr... | 7.38594 |
module tagram_2k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [6:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Wr... | 6.87932 |
module tagram_4k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Wr... | 7.584683 |
module tagram_4k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // W... | 7.168301 |
module tagram_4k3way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Wr... | 7.543315 |
module tagram_4k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
greset,
wr_mask,
wr_data,
rd_data,
hci,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Wr... | 7.017084 |
module tagreg (
input clk,
input rst,
input [1:0] index,
output [9:0] tagbits
);
// 4 10bit tag registers
reg [9:0] tagreg[0:3];
always @(posedge clk) begin
if (rst) begin
tagreg[0] <= 0;
tagreg[1] <= 0;
tagreg[2] <= 0;
tagreg[3] <= 0;
end
end
assign tagbits ... | 7.520728 |
module tags #(
parameter num_bits = 32,
parameter num_cells = 100
) (
match_lines,
set,
select_first,
tag_wires,
some_none,
CLK
);
input wire [num_cells - 1:0] match_lines;
input wire select_first;
input wire set;
input wire [num_cells - 1:0] tag_wires;
input CLK;
output r... | 7.078633 |
module tag_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
... | 7.322604 |
module tag_denetleyici (
input wire clk_i,
input wire rst_i,
// Port 0: W
input wire wen_i,
input wire [8:0] wadr_i,
// Port 0: R
output wire [8:0] data0_o,
input wire [8:0] radr0_i,
// Port 1: R
output wire [8:0] data1_o,
input wire [8:0] radr1_i,
... | 6.735902 |
module tag_generator (
input wire clk,
input wire reset,
input wire branchvalid1,
input wire branchvalid2,
input wire prmiss,
input wire prsuccess,
input wire ... | 7.233921 |
module tag_ram (
input wire clk,
input wire rst_n,
input wire cache_en,
// from decoder
input wire [ `TAG_WIDTH - 1 : 0] tag, // from decoder
input wire [`INDEX_WIDTH - 1 : 0] index, // fro... | 6.978067 |
module Tail (
input [2:0] io_a,
output io_b
);
assign io_b = io_a[0];
endmodule
| 7.007784 |
module TailLight (
input reset,
left,
right,
clk,
output LC,
LB,
LA,
RA,
RB,
RC
);
parameter ST_IDLE = 3'b000;
parameter ST_L1 = 3'b001;
parameter ST_L2 = 3'b010;
parameter ST_L3 = 3'b011;
parameter ST_R1 = 3'b100;
parameter ST_R2 = 3'b101;
parameter ST_R3 = 3'b110... | 7.423801 |
module taming_timer (
input clk_in, // 10Mhz clk in, 100ns clk
input clk_correct, // Taming Signal
input [31:0] epoch_set_dat,
input epoch_set,
input reset,
output reg [31:0] epoch,
output reg [23:0] ns_cnt,
output reg lock
);
//reg [23:0]ns_cnt;
parameter MAX_SEC = 110;
paramet... | 8.149963 |
module taming_timer_testbench;
parameter delay = 500;
parameter second = 64'd100000;
reg clk_in;
reg tame_corection;
reg reset;
wire [31:0] epoch_out;
wire lock_out;
wire [23:0] ns_out;
taming_timer DUT (
clk_in,
tame_corection,
32'b0,
0,
reset,
epoch_out,
ns... | 7.246814 |
module tan (
input [31:0] sayi1,
input clk,
input rst,
output reg [63:0] sonuc,
output reg hazir,
output reg gecerli
);
localparam PI = 3.14159265;
reg [31:0] yenisayi1;
always @(posedge clk) begin
yenisayi1 = sayi1;
if (sayi1 < 0) begin
yenisayi1 = -sayi1;
end
... | 7.847415 |
module EXT_RAM (
input wire [31:0] d2,
addr1,
addr2,
input wire clk,
we,
reset,
output wire [31:0] q1,
q2
);
reg [31:0] md1, md2;
wire [31:0] din2;
wire we2;
wire [9:0] ad1, ad2;
reg [31:0] mem[0:1023];
assign q1 = md1;
assign q2 = md2;
assign we2 = we;
assign din... | 6.84605 |
module bus_master (
input wire [31:0] dataFp1,
dataFp2,
addrbus,
dataFromCpu,
output wire [31:0] data2cpu,
data2pri,
input wire [1:0] bw,
input wire we,
output wire cs1,
cs2
);
// addr : 32'h0000_0000 - 32'h0000_0fff as RAM
// addr : 32'h0001_0000 - 32'h0001_001f as Super_IO
... | 7.893726 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module BufferCC_10 (
input io_dataIn,
output io_dataOut,
input clk,
input reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodu... | 6.968109 |
module StreamArbiter_2 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
... | 6.929245 |
module StreamFifoLowLatency_1 (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input axiClk,
input resetCtrl_axiReset
);
wire ... | 7.046487 |
module Axi4ReadOnlyErrorSlave_1 (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 2:0] io_axi_ar_payload_size,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
ou... | 7.858199 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
... | 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
out... | 7.858199 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input axiClk,
... | 7.790686 |
module InterruptCtrl (
input [3:0] io_inputs,
input [3:0] io_clears,
input [3:0] io_masks,
output [3:0] io_pendings,
input axiClk,
input resetCtrl_axiReset
);
reg [3:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge axiClk or posedge resetCtrl_axi... | 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [31:0] io_limit,
output io_full,
output [31:0] io_value,
input axiClk,
input resetCtrl_axiReset
);
wire [31:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [31:0] counter;
wire limitHi... | 6.729771 |
module BufferCC_8 (
input io_dataIn,
output io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_... | 6.740109 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiRe... | 6.82712 |
module BufferCC_4 (
input io_dataIn,
output io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk or posedge resetCtrl_vgaReset) begin
if (resetCtrl_vgaRe... | 6.634474 |
module BufferCC_3 (
input [6:0] io_dataIn,
output [6:0] io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg [6:0] buffers_0;
(* async_reg = "true" *)reg [6:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk) begin
buffers_0 <= ... | 6.792516 |
module BufferCC (
input [9:0] io_dataIn,
output [9:0] io_dataOut,
input vgaClk,
input resetCtrl_vgaReset
);
(* async_reg = "true" *)reg [9:0] buffers_0;
(* async_reg = "true" *)reg [9:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge vgaClk or posedge resetCtrl_vgaRe... | 6.712921 |
module tang_nano_top (
input wire XTAL_IN,
input wire USER_BTN_A,
input wire USER_BTN_B,
//output reg LCD_BL,
output reg LCD_CLK,
output reg LCD_DE,
output reg LCD_HSYNC,
output reg LCD_VSYNC,
output reg [4:0] LCD_R,
output... | 7.3391 |
module tang_system (
input extclk,
input rst_n,
output ser_tx,
input ser_rx,
output [2:0] leds,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
output debug_flash_csb,
output debug_flash_clk,
output ... | 6.732695 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module tanh_layer (
clk,
rst,
inputs,
outputs
);
// DESCRIPTION: takes array of inputs, weights & biases them,
// and applies tanh per output value
// NOTE: This is using systemverilog 2005 for compilation in Quartus.
// This was done so you could use 2d array inputs and output ports ins... | 6.770634 |
module Tan_multiplier (
clock,
a,
b,
product
);
parameter awidth = 10;
parameter bwidth = 10;
parameter pwidth = 20;
input clock;
input [awidth-1:0] a;
input [bwidth-1:0] b;
output wire [16:0] product;
wire [pwidth-1:0] product_internal;
assign product = product_internal[18:2];
D... | 6.86148 |
module tanh_result (
input clock
, input start_interpolation
, input [16:0] product
, output wire [15:0] tanh_result
);
reg [16:0] interpolation;
reg [16:0] interpolation_internal;
reg [16:0] mux_out;
always @(posedge clock) begin
interpolation <= interpolation_internal;
end
always @(... | 6.896771 |
module tanh_tb ();
reg clk;
reg [17:0] tanh_in;
wire [17:0] tanh_out;
reg [7:0] cnt = 0;
reg [15:0] test_num = 16'hffff;
initial begin
tanh_in = 0;
clk = 0;
end
always @(posedge clk) begin
cnt <= cnt + 1;
if (cnt == 3) begin
tanh_in <= 18'b0000_0010_0000_0000_00; //0.5 (1,5,12)
... | 6.705764 |
module tanh (
input clock
, input [16:0] a_mod
, input [15:0] y
, output wire [11:0] y_address
, input start_tanh
, input start_interpolation
, output wire [15:0] tanh_result
);
wire [ 9:0] x1;
wire [ 9:0] x_difference;
wire [16:0] product;
Yunit U1 (
.address(a_mod[16:9]),
... | 6.502063 |
module Yunit (
input [7:0] address
, input start_tanh
, output reg [11:0] y_address
);
always @(*) begin
case (start_tanh)
1'b0: y_address = {3'b0, address, 1'b0};
1'b1: y_address = {3'b0, address + 1, 1'b0};
endcase
end
endmodule
| 6.714156 |
module playfield (
hpos,
vpos,
playfield_gfx
);
input [8:0] hpos;
input [8:0] vpos;
output playfield_gfx;
reg [31:0] maze[0:27];
wire [4:0] x = hpos[7:3];
wire [4:0] y = vpos[7:3] - 2;
assign playfield_gfx = maze[y][x];
initial begin
maze[0] = 32'b11111111111111111111111111111111;
... | 7.313035 |
module tank_game_top (
input clk,
input reset,
input [7:0] switches_p1,
input [7:0] switches_p2,
output hsync,
output vsync,
output [2:0] rgb
);
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
wire mine_gfx;
wire playfield_gfx;
wire tank1_gfx;
wire tank2_gfx;
// video s... | 6.722855 |
module tankb__cputest_top;
//wire & reg setup
reg PUR = 1'b1;
reg clk = 1'b0;
reg nRESET = 1'b1;
wire Phi2, cpu_clken;
//start simulation specific
initial begin
#10 nRESET = 1'b0;
#1 PUR = 1'b0;
#50 PUR = 1'b1;
#70 nRESET = 1'b1;
end
always #1 clk <= ~clk;
//end simulation specifi... | 7.159422 |
module tank_decoder2 (
output wire rack_loc_t0_in,
output wire rack_loc_t1_in,
output wire rack_loc_t2_in,
output wire rack_loc_t3_in,
output wire rack_loc_t0_out,
output wire rack_loc_t1_out,
output wire rack_loc_t2_out,
output wire rack_loc_t3_out,
input wire rack_loc_f7_pos, // ... | 6.721101 |
module
(Similar to physical layer)
(convert the x/y relative coordinate to VGA data)
Modification History:
Date By Version Description
----------------------------------------------------------
180505 ctlvie 0.5 Module interface definition
180507 ctlvie 1.0 Initial coding completed (unver... | 6.562175 |
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