code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module of four enemy's tanks
Modification History:
Date By Version Description
----------------------------------------------------------
180505 ctlvie 0.5 Module interface definition
180507 ctlvie 0.6 Add tank_state interfaces
180508 ctlvie 1.0 Initial coding completed(unverified)
180508 ctlvie 1.1 ... | 6.72321 |
module tank_graphic (
x,
y,
flush_x,
flush_y,
direction,
colour,
enable
);
input [7:0] x;
input [7:0] y;
input [7:0] flush_x;
input [7:0] flush_y;
input [1:0] direction;
output [5:0] colour;
output enable;
wire [6:0] lut_out;
tank_graphic_lut(
flush_x - x, flush_y ... | 6.526884 |
module selector_drawer_fsm (
x_out,
y_out,
colour_out,
done,
colour1,
x,
y,
load,
clk,
reset
);
endmodule
| 6.778432 |
module game_controller_fsm (
load_p,
load_s,
x_out,
y_out,
colour1_out,
colour2_out,
done_p,
done_s,
selector,
direction,
clk,
reset
);
input [3:0] selector; // Changes the cell the selector is on
input [3:0] direction; // Tries to move the selected peice up, down,... | 7.681663 |
module tap (
// Inputs
tck, // External Clock Source
tms, // State Machine Control
// Outputs
reset, // Register Reset signal
select, // Selects between IR and DR TDO signals
enable, // Enables TDO output (in Shift_Ir or Shift_Dr state)
// Instruction Register Signals
clock_ir,... | 6.779865 |
module tap_controller (
input tck,
tms,
trst,
output cdr1,
sdr1,
udr1,
cir1,
sir1,
uir1
);
/*where -
c= capture
u= update
s= shift
dr= data register
ir= instruction register
tck = input clock
tms = state mode signal
trst= reset signal
*/
localparam TEST_LOGIC_RESET = 4'h0;
l... | 6.775217 |
module tape (
input reset,
input clk,
input ce_1m,
input ioctl_download,
input tape_pause,
output reg tape_audio,
output tape_active,
output reg tape_rd,
output reg [24:0] tape_addr,
input [ 7:0] tape_data
);
reg [23:0] cnt;
assign tape_active = ... | 6.742839 |
module used to instantiate I/O pads and connect them with the block-level design
//----------------------------------------------------------------------
// Pads
//----------------------------------------------------------------------
// EN : If 1, DOUT writes to PAD, if 0, short from PAD to DIN
// DOUT ... | 8.144031 |
module TappedDelayRegister (
input wire iClock,
input wire iEnable,
input wire [3:0] iM,
input wire [15:0] iData,
output wire [15:0] oData
);
parameter LENGTH = 32;
integer i;
reg [15:0] delay[0:LENGTH - 1];
reg [15:0] delay_tap;
assign oData = delay_tap;
always @(posedge iClock) be... | 6.744653 |
module tapped_fifo #(
parameter WIDTH = 1,
parameter DEPTH = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] inp,
output wire [WIDTH*DEPTH-1:0] taps,
output wire [WIDTH-1:0] outp
);
reg [WIDTH-1:0] regs[DEPTH];
assign outp = regs[DEPTH-1];
dff #(WIDTH) sr0 (
clk,... | 7.41901 |
module tapped_fifo_test1 (
input clk,
input rst,
input wire inp,
output wire [9:0] taps,
output wire outp
);
tapped_fifo #(
.WIDTH(1),
.DEPTH(10)
) f_1_10 (
clk,
rst,
inp,
taps,
outp
);
endmodule
| 6.789807 |
module tapped_fifo_test2 (
input clk,
input rst,
input wire [31:0] inp,
output wire [(32*10-1):0] taps,
output wire [31:0] outp
);
tapped_fifo #(
.WIDTH(32),
.DEPTH(10)
) f_1_10 (
clk,
rst,
inp,
taps,
outp
);
endmodule
| 6.789807 |
module taps (
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
clk,
reset,
sel,
newt,
d,
x
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input clk;
input reset;
input [1:0] sel;
input newt;
input [7:0... | 7.378744 |
module taptempo #(
parameter CLK_PER_NS = 40, // 25Mhz clock
parameter TP_CYCLE = 5120, // Number of cycles per timepulse
parameter BPM_MAX = 250
) (
input clk_i,
input btn_i,
output pwm_o
);
/* generate reset internally */
wire rst;
rstgen inst_rstgen (
.clk_i(clk_i),
.... | 7.012471 |
module draw_target_k #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, WIDTH=40,HEIGHT=30, MEMFILE="") (
// input wire clk,
// input wire w_write,
// input wire [10:0] w_current_x,
// input wire [10:0] w_current_y,
// input wire [10:0] w_pos_x,
// input wire [10:0] w_pos_y,
// output reg [DATA_WIDTH-1:0] r_out_data
// );... | 6.569762 |
module target_graphic_lut (
x,
y,
out
);
input [7:0] x;
input [7:0] y;
output reg [6:0] out;
always @(*) begin
out[6] <= 1'b1;
case ({
x, y
})
16'h0200: out[5:0] <= 6'b111111;
16'h0800: out[5:0] <= 6'b111111;
16'h0301: out[5:0] <= 6'b111111;
16'h0701: out[5... | 6.565971 |
module target_graphic (
x,
y,
flush_x,
flush_y,
colour,
enable
);
input [7:0] x;
input [7:0] y;
input [7:0] flush_x;
input [7:0] flush_y;
output [5:0] colour;
output enable;
wire [6:0] lut_out;
target_graphic_lut(
flush_x - x, flush_y - y, lut_out
);
assign colour =... | 6.565971 |
module target_ppn_generate_unit (
input [ 1:0] count,
input [49:0] pte_addr,
input [27:0] r_req_addr,
output [37:0] resp_ppn
);
assign resp_ppn = count >= 2 ? pte_addr[49:12] : ((count & 2'h1) >= 2'h1 ? {pte_addr[49:21], r_req_addr[8:0]} : {pte_addr[49:30], r_req_addr[17:0]});
endmodule
| 6.756571 |
module target_selector (
target_number,
encode_selector
);
input [3:0] target_number; //change to 32 bit
output [3:0] encode_selector;
assign encode_selector = target_number;
endmodule
| 7.085182 |
module target_sim;
// Inputs
reg clk_100Hz;
reg rst;
reg start;
reg [2:0] din;
reg shot;
// Outputs
wire [9:0] x;
wire [8:0] y;
wire [1:0] state;
wire [1:0] animation_state;
// Instantiate the Unit Under Test (UUT)
target uut (
.clk_100Hz(clk_100Hz),
.rst(rst),
.start(star... | 6.844138 |
module iobs #(
parameter WIDTH = 24,
parameter MSB = WIDTH - 1,
parameter DELAY = `DELAY
) (
input clk,
input rst,
input en,
input [ 3:0] dly,
input [MSB:0] raw,
output [MSB:0] sig
);
wire [MSB:0] ddr, neg, pos;
assign ddr = dly[0] ? neg : pos;
... | 7.305033 |
module dff_tb;
parameter PERIOD = 4;
reg clk, d_in;
wire d_out;
dff dff_inst1 (
.clk (clk),
.d_in (d_in),
.d_out(d_out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
d_in = 0;
@(negedge clk) d_in = 1;
repeat (20) begin
@(ne... | 6.528672 |
module dff (
clk,
d_in,
d_out
);
input clk, d_in;
output reg d_out;
always @(posedge clk) begin
d_out <= d_in;
end
endmodule
| 6.824043 |
module circular_shifter_tb;
parameter PERIOD = 4;
parameter WIDTH = 4;
reg clk, n_rst;
wire [WIDTH-1:0] out;
circular_shifter #(
.WIDTH(WIDTH)
) reg_inst1 (
.clk (clk),
.n_rst(n_rst),
.out (out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
ini... | 6.652056 |
module circular_shifter (
clk,
n_rst,
out
);
parameter WIDTH = 4;
input clk;
input n_rst;
output reg [WIDTH - 1 : 0] out;
always @(posedge clk, negedge n_rst)
if (!n_rst) begin
out[WIDTH-1] <= 1'b1;
out[WIDTH-2:0] <= 1'b0;
end else begin
out[WIDTH-1] <= out[0];
... | 6.652056 |
module jsn_counter_tb;
parameter PERIOD = 4;
parameter WIDTH = 4;
reg clk, n_rst;
wire [WIDTH-1:0] out;
jsn_counter #(
.WIDTH(WIDTH)
) reg_inst1 (
.clk (clk),
.n_rst(n_rst),
.out (out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
initial begin... | 6.997089 |
module jsn_counter (
clk,
n_rst,
out
);
parameter WIDTH = 4;
input clk;
input n_rst;
output reg [WIDTH - 1 : 0] out;
always @(posedge clk, negedge n_rst)
if (!n_rst) begin
out <= {WIDTH{1'b0}};
end else begin
out <= out >> 1;
out[WIDTH-1] <= ~out[0];
end
endmodule
... | 7.472176 |
module complex_latch_tb;
parameter PERIOD = 4;
reg clk, n_rst;
reg [3:0] data_in;
wire [3:0] jcnt_out, data_out;
complex_latch complex_latch (
.clk(clk),
.n_rst(n_rst),
.data_in(data_in),
.jcnt_out(jcnt_out),
.data_out(data_out)
);
initial begin
clk = 1'b0;
foreve... | 7.539083 |
module complex_latch (
clk,
n_rst,
data_in,
jcnt_out,
data_out
);
input clk;
input n_rst;
input [3:0] data_in;
output reg [3:0] jcnt_out;
output reg [3:0] data_out;
wire we;
assign we = (n_rst ^ (^jcnt_out ^ (^jcnt_out[2:1])));
always @(posedge clk, negedge n_rst) begin
if (!... | 7.539083 |
module pipeline (
clk,
n_rst,
A,
B,
C,
Q,
Q_pipe
);
parameter WIDTH = 4;
input clk;
input n_rst;
input [WIDTH-1:0] A;
input [WIDTH-1:0] B;
input [WIDTH-1:0] C;
output reg [WIDTH-1:0] Q;
output reg [WIDTH-1:0] Q_pipe;
reg [WIDTH-1:0] q_a;
reg [WIDTH-1:0] q_b;
reg [WIDT... | 7.698493 |
module dff_complex_tb;
parameter PERIOD = 4;
reg clk, rst_n, set_n, we, d_in;
wire d_out;
dff_complex dff_inst1 (
.clk(clk),
.rst_n(rst_n),
.set_n(set_n),
.we(we),
.d_in(d_in),
.d_out(d_out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
i... | 6.757942 |
module dff_complex (
clk,
rst_n,
set_n,
we,
d_in,
d_out
);
input clk, rst_n, set_n, we, d_in;
output reg d_out;
always @(posedge clk, negedge rst_n, negedge set_n) begin
if (!rst_n) begin
d_out <= 1'b0;
end else if (!set_n) begin
d_out <= 1'b1;
end else if (we) be... | 7.279003 |
module dff_complex_tb;
parameter PERIOD = 4;
reg clk, rst_n, set_n, we, d_in;
wire d_out;
dff_complex dff_inst1 (
.clk(clk),
.rst_n(rst_n),
.set_n(set_n),
.we(we),
.d_in(d_in),
.d_out(d_out)
);
initial begin
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
i... | 6.757942 |
module dff_complex (
clk,
rst_n,
set_n,
we,
d_in,
d_out
);
input clk, rst_n, set_n, we, d_in;
output reg d_out;
always @(posedge clk, negedge rst_n, negedge set_n) begin
if (!rst_n) begin
d_out <= 1'b0;
end else if (!set_n) begin
d_out <= 1'b1;
end else if (we) begi... | 7.279003 |
module reg_8bit (
clk,
rst_n,
data_in,
data_out
);
input clk, rst_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
data_out <= data_in;
end
end
endmodule
| 7.417492 |
module reg_8bit_we (
clk,
rst_n,
data_in,
data_out,
we_n
);
input clk, rst_n, we_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else if (!we_n) begin
data_out <= data_in;
end
end
e... | 7.706799 |
module param_shift_reg (
clk,
rst_n,
data_in,
data_out
);
parameter WIDTH = 8;
input clk, rst_n;
input data_in; //serial loading
output reg [WIDTH - 1 : 0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
data_out <= {... | 8.752063 |
module param_shift_direct_parallel_reg_tb;
parameter PERIOD = 4;
parameter WIDTH = 4;
reg clk, rst_n, we_n, direction;
reg [WIDTH - 1:0] par_in;
wire [ WIDTH-1:0] data_out;
param_shift_direct_parallel_reg #(
.WIDTH(WIDTH)
) reg_inst1 (
.clk(clk),
.rst_n(rst_n),
.we_n(we_n),
... | 8.50231 |
module param_shift_direct_parallel_reg (
par_in,
direction,
clk,
rst_n,
we_n,
data_out
);
parameter WIDTH = 4;
input clk, rst_n, we_n, direction;
input [WIDTH - 1:0] par_in;
output reg [WIDTH - 1 : 0] data_out;
always @(posedge clk, negedge rst_n)
if (!rst_n) data_out <= 0;
... | 8.50231 |
module cyc_shift (
clk,
rst_n,
out
);
parameter width = 4;
input clk, rst_n;
output [width-1:0] out;
reg [width-1:0] tmp;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tmp <= 4'b1000;
end else begin
tmp <= tmp >> 1;
tmp[width-1] <= tmp[0];
end
end
... | 7.780546 |
module cyc_shift_tb;
parameter period = 4;
parameter width = 4;
reg clk, rst_n;
wire [width-1:0] out;
cyc_shift #(
.width(width)
) inst1 (
.clk (clk),
.rst_n(rst_n),
.out (out)
);
initial begin
clk = 0;
forever #(period / 2) clk = ~clk;
end
initial begin
rst_n =... | 7.044076 |
module johnson (
clk,
rst_n,
out
);
parameter width = 4;
input clk, rst_n;
output [width-1:0] out;
reg [width-1:0] tmp;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tmp <= 0;
end else begin
tmp <= tmp >> 1;
tmp[width-1] <= ~tmp[0];
end
end
assign... | 8.187334 |
module johnson_tb;
parameter period = 4;
parameter width = 4;
reg clk, rst_n;
wire [width-1:0] out;
johnson #(
.width(width)
) inst1 (
.clk (clk),
.rst_n(rst_n),
.out (out)
);
initial begin
clk = 0;
forever #(period / 2) clk = ~clk;
end
initial begin
rst_n = 0;
... | 7.153325 |
module jcnt (
clk,
rst_n,
out
);
parameter width = 4;
input clk, rst_n;
output [width-1:0] out;
reg [width-1:0] tmp;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tmp <= 0;
end else begin
tmp <= tmp >> 1;
tmp[width-1] <= ~tmp[0];
end
end
assign ou... | 7.886297 |
module complex_latch (
rst_n,
data_in,
jcnt_in,
data_out
);
parameter width = 4;
input rst_n;
input [width-1:0] data_in;
input [width-1:0] jcnt_in;
output reg [width-1:0] data_out;
always @(rst_n, data_in, jcnt_in) begin
if (!rst_n) begin
data_out <= 0;
end else begin
i... | 7.539083 |
module dev1 (
i_clk,
i_rst_n,
i_A,
i_B,
i_C,
o_Q
);
parameter width = 4;
input i_clk, i_rst_n;
input [width-1:0] i_A, i_B, i_C;
output reg [width-1:0] o_Q;
reg [width-1:0] A_t, B_t, C_t;
always @(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
o_Q <= 0;
A_... | 7.077559 |
module dev2 (
i_clk,
i_rst_n,
i_A,
i_B,
i_C,
o_Q_pipe
);
parameter width = 4;
input i_clk, i_rst_n;
input [width-1:0] i_A, i_B, i_C;
output reg [width-1:0] o_Q_pipe;
reg [width-1:0] A_t, B_t, C_t;
reg [width-1:0] AB_sum_st2, C_st2;
always @(posedge i_clk or negedge i_rst_n) begin
... | 7.517024 |
modules reg_8bit_we_mod and reg_8bit_we_mod_tb
Last one is the test bench of first module*/
`timescale 1 ns / 1 ps
module reg_8bit_we_mod(clk, rst_n, we_n, data_in, data_out);
input clk, rst_n, we_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begi... | 7.858398 |
module paral_shift (
clk,
rst_n,
dir,
par_seq,
data_in,
data_parallel_load,
data_out
);
parameter WIDTH = 8;
input clk, rst_n;
input dir, par_seq, data_in;
input [WIDTH-1:0] data_parallel_load;
output reg [WIDTH-1:0] data_out;
always @(posedge clk or negedge rst_n) begin
i... | 8.344387 |
module paral_shift_tb;
parameter period = 4;
reg clk, rst_n, dir, data_in, par_seq;
reg [7:0] data_parallel_load;
wire [7:0] data_out;
paral_shift inst1 (
.clk(clk),
.rst_n(rst_n),
.dir(dir),
.par_seq(par_seq),
.data_in(data_in),
.data_parallel_load(data_parallel_load),
... | 7.423766 |
module bitwise_nor (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NOR
nor nor_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.325548 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
assign o_sum = i_a ^ i_b;
assign o_carry = i_a & i_b;
endmodule
| 6.966406 |
module adder_4bit (
i_a,
i_b,
i_carry,
o_sum,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_sum;
output o_carry;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADDER
if (i == 0)
... | 9.041993 |
module decoder (
i_data,
o_data
);
parameter WIDTH = 2;
input [WIDTH-1:0] i_data;
output [2**WIDTH-1:0] o_data;
genvar i;
generate
for (i = 0; i < 2 ** WIDTH; i = i + 1) begin : DC
assign o_data[i] = (i_data == i) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
| 7.018254 |
module mux4 (
i_sel,
i_d0,
i_d1,
i_d2,
i_d3,
o_data
);
parameter WIDTH = 4;
input [1:0] i_sel;
input [WIDTH-1:0] i_d0, i_d1, i_d2, i_d3;
output [WIDTH-1:0] o_data;
wire [3:0] one_hot;
genvar i;
decoder #(
.WIDTH(2)
) decoder_inst (
.i_data(i_sel),
.o_data(on... | 7.382717 |
module bitwise_nand (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NAND
nand nand_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.116582 |
module bitwise_nor (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NOR
nor nor_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.325548 |
module ALU_gate (
i_var1,
i_var2,
i_sel,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
input [2:0] i_sel;
output [2*WIDTH-1:0] o_res;
wire [WIDTH-1:0] sum, nor_res, nand_res;
wire [2*WIDTH-1:0] mult;
wire carry, borr;
wire [WIDTH-1:0] adder;
genvar i;
generat... | 8.473477 |
module ALU_behavior (
i_var1,
i_var2,
i_sel,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
input [2:0] i_sel;
output reg [2*WIDTH-1:0] o_res;
reg [2*WIDTH-1:0] res;
reg [WIDTH-1:0] sum, sub, nand_res, nor_res;
reg [2*WIDTH-1:0] mult;
always @* begin
sum = i_var... | 9.07293 |
module ALU_tb ();
parameter WIDTH = 4;
wire [2*WIDTH-1:0] o_res_b, o_res_g;
reg [WIDTH-1:0] i_var1, i_var2;
reg [2:0] i_sel;
integer i, j, k;
integer error_count;
event stop;
ALU_behavior #(
.WIDTH(WIDTH)
) ALU_behavior_inst (
.i_var1(i_var1),
.i_var2(i_var2),
.i_sel (i_... | 7.60053 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
assign o_sum = i_a ^ i_b;
assign o_carry = i_a & i_b;
endmodule
| 6.966406 |
module adder_4bit (
i_a,
i_b,
i_carry,
o_sum,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_sum;
output o_carry;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADDER
if (i == 0)
... | 9.041993 |
module add_sub (
i_var1,
i_var2,
o_res,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
output o_carry;
wire [WIDTH-1:0] adder;
wire carry_in;
`ifdef SUB
assign adder = ~i_var2;
assign carry_in = 1'b1;
`else
assign adder = i_va... | 7.314322 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
assign o_sum = i_a ^ i_b;
assign o_carry = i_a & i_b;
endmodule
| 6.966406 |
module adder_4bit (
i_a,
i_b,
i_carry,
o_sum,
o_carry
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_sum;
output o_carry;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADDER
if (i == 0)
... | 9.041993 |
module add_sub (
i_var1,
i_var2,
o_res,
o_carry
);
parameter MODE = 1;
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
output o_carry;
wire [WIDTH-1:0] adder;
wire carry_in;
generate
if (MODE) begin
assign adder = i_var2;
as... | 7.314322 |
module task1_module (
clk,
rst_n,
a,
b,
i1_o,
i2_o
);
input clk;
input rst_n;
input [7:0] a;
input [7:0] b;
output [8:0] i1_o;
output [8:0] i2_o;
/***********************/
reg [8:0] rData1;
reg [8:0] rData2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) b... | 6.583957 |
module vga_display_sim ();
reg clk, rst_n;
wire [3:0] out_r;
wire [3:0] out_g;
wire [3:0] out_b;
wire h_sync, v_sync;
top sim (
clk,
rst_n,
out_r,
out_g,
out_b,
h_sync,
v_sync
);
initial begin
clk = 0;
rst_n = 0;
#10 rst_n = 1;
end
always #5 c... | 6.776332 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module bitwise_nor (
i_op1,
i_op2,
o_nor
);
input [3:0] i_op1, i_op2;
output [3:0] o_nor;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : not_or
nor n (o_nor[i], i_op1[i], i_op2[i]);
end //nor
endgenerate
endmodule
| 7.325548 |
module subtractor_without_borrow_in (
i_op1,
i_op2,
o_subtract,
o_borrow_out
);
input [3:0] i_op1, i_op2;
output [3:0] o_subtract;
output o_borrow_out;
wire [3:0] borrow;
assign o_borrow_out = borrow[3];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : adder_iteration
... | 7.030396 |
module behavioral_alu (
i_op1,
i_op2,
i_ctrl,
o_data
);
input [3:0] i_op1, i_op2;
input [2:0] i_ctrl;
output reg [7:0] o_data;
always @* begin
case (i_ctrl)
0: o_data <= i_op1 + i_op2;
1: o_data <= i_op1 - i_op2;
2: o_data <= i_op1 * i_op2;
3: o_data <= ~(i_op1 & i... | 9.669933 |
module adder_or_subtractor (
i_op1,
i_op2,
i_carry_borrow_in,
o_res,
o_carry_borrow_out
);
input [3:0] i_op1, i_op2;
input i_carry_borrow_in;
output [3:0] o_res;
output o_carry_borrow_out;
`ifdef ADD
four_bit_adder adder (
.i_op1(i_op1),
.i_op2(i_op2),
.i_carry_in(i_carr... | 6.716334 |
module adder_or_subtractor (
i_op1,
i_op2,
i_carry_borrow_in,
o_res,
o_carry_borrow_out
);
parameter mode = 1;
input [3:0] i_op1, i_op2;
input i_carry_borrow_in;
output [3:0] o_res;
output o_carry_borrow_out;
generate
if (mode == 1)
four_bit_adder adder (
.i_op1(i... | 6.716334 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module param_adder (
i_op1,
i_op2,
i_carry_in,
o_sum,
o_carry_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
input i_carry_in;
output [WIDTH-1:0] o_sum;
output o_carry_out;
wire [WIDTH-1:0] carry;
assign o_carry_out = carry[WIDTH-1];
genvar i;
generate
for (i... | 8.614904 |
module adder_tb;
parameter WIDTH = 8;
reg [WIDTH-1:0] op1, op2;
reg carry_in;
wire [WIDTH-1:0] sum;
wire carry_out;
reg [ WIDTH:0] carry_concat_sum;
param_adder #(
.WIDTH(WIDTH)
) add (
.i_op1(op1),
.i_op2(op2),
.i_carry_in(carry_in),
.o_sum(sum... | 7.121349 |
module adder_without_carry_in (
i_op1,
i_op2,
o_sum,
o_carry_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_sum;
output o_carry_out;
wire [WIDTH-1:0] carry;
assign o_carry_out = carry[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + ... | 8.878618 |
module subtractor_without_borrow_in (
i_op1,
i_op2,
o_subtract,
o_borrow_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_subtract;
output o_borrow_out;
wire [WIDTH-1:0] borrow;
assign o_borrow_out = borrow[WIDTH-1];
genvar i;
generate
for (i = 0... | 7.030396 |
module behavioral_alu (
i_op1,
i_op2,
i_ctrl,
o_data
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
input [2:0] i_ctrl;
output reg [2*WIDTH-1:0] o_data;
always @* begin
case (i_ctrl)
0: o_data <= i_op1 + i_op2;
1: o_data <= i_op1 - i_op2;
2: o_data <= i_op1 *... | 9.669933 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module stage (
i_prev_stage,
i_op,
i_bit,
i_carry,
o_carry,
o_result
);
parameter WIDTH = 4;
input [WIDTH-2:0] i_prev_stage;
input [WIDTH-1:0] i_op;
input i_bit, i_carry;
output [WIDTH-1:0] o_result;
output o_carry;
wire [WIDTH-1:0] carry_bit;
wire [WIDTH-1:0] o_and;
genvar i... | 8.328539 |
module bitwise_nand (
i_op1,
i_op2,
o_nand
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_nand;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : not_and
nand n (o_nand[i], i_op1[i], i_op2[i]);
end //nand
endgenerate
endmodule
| 7.116582 |
module bitwise_nor (
i_op1,
i_op2,
o_nor
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_nor;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : not_or
nor n (o_nor[i], i_op1[i], i_op2[i]);
end //nor
endgenerate
endmodule
| 7.325548 |
module half_subtractor (
i_op1,
i_op2,
o_subtract,
o_borrow
);
input i_op1, i_op2;
output o_subtract, o_borrow;
xor (o_subtract, i_op1, i_op2);
and (o_borrow, ~i_op1, i_op2);
endmodule
| 6.878143 |
module full_subtractor (
i_op1,
i_op2,
i_borrow_in,
o_subtract,
o_borrow
);
input i_op1, i_op2, i_borrow_in;
output o_subtract, o_borrow;
wire sub1, bor1, bor2;
or or1 (o_borrow, bor1, bor2);
half_subtractor first_half_subtractor (
.i_op1(i_op1),
.i_op2(i_op2),
.o_sub... | 8.333169 |
module half_subtractor (
i_op1,
i_op2,
o_subtract,
o_borrow
);
input i_op1, i_op2;
output o_subtract, o_borrow;
xor (o_subtract, i_op1, i_op2);
and (o_borrow, ~i_op1, i_op2);
endmodule
| 6.878143 |
module full_subtractor (
i_op1,
i_op2,
i_borrow_in,
o_subtract,
o_borrow
);
input i_op1, i_op2, i_borrow_in;
output o_subtract, o_borrow;
wire sub1, bor1, bor2;
or or1 (o_borrow, bor1, bor2);
half_subtractor first_half_subtractor (
.i_op1(i_op1),
.i_op2(i_op2),
.o_sub... | 8.333169 |
module half_adder (
i_op1,
i_op2,
o_sum,
o_carry
);
input i_op1, i_op2;
output o_sum, o_carry;
xor (o_sum, i_op1, i_op2);
and (o_carry, i_op1, i_op2);
endmodule
| 6.966406 |
module adder_without_carry_in (
i_op1,
i_op2,
o_sum,
o_carry_out
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_op1, i_op2;
output [WIDTH-1:0] o_sum;
output o_carry_out;
wire [WIDTH-1:0] carry;
assign o_carry_out = carry[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + ... | 8.878618 |
module four_in_and (
o_out,
i_in0,
i_in1,
i_in2,
i_in3
);
output o_out;
input i_in0, i_in1, i_in2, i_in3;
wire c1, c2;
and (c1, i_in0, i_in1);
and (c2, i_in3, i_in2);
and (o_out, c1, c2);
endmodule
| 7.065281 |
module five_in_or (
o_out,
i_in
);
output o_out;
input [4:0] i_in;
wire c1, c2, c3;
or (c1, i_in[0], i_in[1]);
or (c2, i_in[2], i_in[3]);
or (c3, c1, c2);
or (o_out, i_in[4], c3);
endmodule
| 7.252666 |
module one_bit_mux (
i_in0,
i_in1,
i_in2,
i_in3,
i_in4,
i_ctrl,
o_out
);
input i_in0, i_in1, i_in2, i_in3, i_in4;
input [2:0] i_ctrl;
output o_out;
wire [4:0] select;
wire [2:0] not_ctrl;
not n1 (not_ctrl[0], i_ctrl[0]);
not n2 (not_ctrl[1], i_ctrl[1]);
not n3 (not_ctrl[2... | 6.639519 |
module mux (
i_data0,
i_data1,
i_data2,
i_data3,
i_data4,
i_ctrl,
o_data
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_data0, i_data1, i_data2, i_data3, i_data4;
input [2:0] i_ctrl;
output [WIDTH-1:0] o_data;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : mux... | 7.052968 |
module bitwise_nand (
i_op1,
i_op2,
o_nand
);
input [3:0] i_op1, i_op2;
output [3:0] o_nand;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : not_and
nand n (o_nand[i], i_op1[i], i_op2[i]);
end //nand
endgenerate
endmodule
| 7.116582 |
module task2a (
input wire clk,
output wire uart_tx
);
reg bclk_en = 1;
wire baud_clk;
reg send_enable = 1;
reg [7:0] send_data = 42; //Data value to send
wire uart_busy;
// Instanciate Baud Clock Generator
baud_clk_generator bclk (
clk,
bclk_en,
baud_clk
);
// Insta... | 7.272731 |
module task2b_continuous (
input wire clk,
output wire uart_tx,
input wire switch1,
input wire switch2,
input wire switch3,
input wire switch4
);
reg bclk_en = 1;
wire baud_clk;
reg send_enable = 1;
// Data contains the current state of the switches
wire [7:0] send_data = {4'b0... | 8.64224 |
module task2b_onlywhenchanged (
input wire clk,
output wire uart_tx,
input wire switch1,
input wire switch2,
input wire switch3,
input wire switch4
);
reg bclk_en = 1;
wire baud_clk;
reg send_enable = 1;
// Data contains the current state of the switches
wire [7:0] switch_data ... | 8.379801 |
module bit1_nor (
i_a,
i_b,
o_data
);
input i_a, i_b;
output o_data;
nor (o_data, i_a, i_b);
endmodule
| 7.135021 |
module bit4_nor (
i_a,
i_b,
i_a_g,
i_b_g,
o_data,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
output [WIDTH-1:0] o_data, o_data_g;
bit1_nor br0 (
.i_a(i_a[0]),
.i_b(i_b[0]),
.o_data(o_data[0])
);
bit1_nor br1 (
.i_a(i_a[1]),... | 7.092375 |
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