code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ALU (
i_a,
i_b,
i_sel,
o_data
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input [WIDTH-2:0] i_sel;
output [2*WIDTH-1:0] o_data;
wire [2*WIDTH-1:0] o_data_mult;
wire [WIDTH-1:0] o_data_sub_0;
wire [WIDTH-1:0] o_data_add_0;
wire [WIDTH-1:0] o_data_nand_0;
wire [WIDTH... | 6.985879 |
module ALU_behav (
i_sel_g,
i_a_g,
i_b_g,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a_g, i_b_g;
input [WIDTH-2:0] i_sel_g;
output reg [2*WIDTH-1:0] o_data_g;
wire [ WIDTH-1:0] i_a_add_g;
wire [ WIDTH-1:0] i_b_add_g;
wire [ WIDTH-1:0] i_a_sub_g;
wire [ WIDTH-1:0] i_b_... | 7.545058 |
module add_sub (
i_a,
i_b,
i_a_g,
i_b_g,
o_res,
o_res_g,
o_c
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input [WIDTH-1:0] i_a_g;
input [WIDTH-1:0] i_b_g;
output [WIDTH:0] o_res_g;
output [WIDTH-1:0] o_res;
output o_c;
wire [WIDTH-1:0] i_b_in;
wire carry_i,... | 7.314322 |
module param_adder (
i_a,
i_b,
i_c,
o_si,
o_pi
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_c;
output [WIDTH-1:0] o_si;
output o_pi;
wire [WIDTH-1:0] carry;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : ADD
if (i == 0) begin
fu... | 8.614904 |
module gen_add_sub (
i_a,
i_b,
i_a_g,
i_b_g,
o_res,
o_c,
o_res_g
);
parameter ADDSUB = 1'b1;
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
output [WIDTH-1:0] o_res;
output [WIDTH:0] o_res_g;
output o_c;
wire o_carry;
generate
begin
if (ADDSU... | 7.113416 |
module full_adder_4bit (
i_a,
i_b,
i_c,
o_pi,
o_s
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input i_c;
output o_pi;
output [WIDTH-1:0] o_s;
wire fa0_ci;
wire fa1_ci;
wire fa2_ci;
wire fa3_ci;
full_adder fa0 (
.i_a (i_a[0]),
.i_b (i_b[0]),
.i_c (i_... | 6.62292 |
module full_adder_4bit_tb;
parameter WIDTH = 4;
reg [WIDTH-1:0] i_a, i_b;
reg i_c;
wire o_pi;
wire [WIDTH-1:0] o_s;
full_adder_4bit fa_tb (
.i_a (i_a),
.i_b (i_b),
.i_c (i_c),
.o_pi(o_pi),
.o_s (o_s)
);
initial begin
i_a = 4'b0000;
i_b = 4'b0000;
i_c = 1'... | 6.62292 |
module half_adder (
i_a,
i_b,
o_si,
o_pi
);
input i_a, i_b;
output o_si, o_pi;
assign o_si = i_a ^ i_b;
assign o_pi = i_a & i_b;
endmodule
| 6.966406 |
module full_adder_4bit2 (
i_a,
i_b,
i_c,
i_a_g,
i_b_g,
o_pi,
o_s,
o_sum_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b;
input [WIDTH-1:0] i_a_g, i_b_g;
input i_c;
output o_pi;
output [WIDTH-1:0] o_s;
output [WIDTH:0] o_sum_g;
wire fa0_ci;
wire fa1_ci;
wire f... | 6.62292 |
module full_adder_4bit_tb2;
parameter WIDTH = 4;
reg [WIDTH-1:0] i_a, i_b;
reg [WIDTH-1:0] i_a_g, i_b_g;
reg i_c;
wire o_pi;
wire [WIDTH-1:0] o_s;
wire [WIDTH:0] o_sum_g;
integer i = 0, j = 0, k;
full_adder_4bit2 fa_tb (
.i_a(i_a),
.i_b(i_b),
.i_c(i_c),
.i_a_g(i_a_g),
... | 6.62292 |
module full_adder2 (
i_a,
i_b,
i_c,
o_si,
o_pi
);
input i_a, i_b, i_c;
output o_si, o_pi;
wire ha1_sum;
wire ha2_sum;
wire ha1_carry;
wire ha2_carry;
half_adder ha1 (
.i_a (i_a),
.i_b (i_b),
.o_si(ha1_sum),
.o_pi(ha1_carry)
);
half_adder ha2 (
.... | 7.985516 |
module bit4_sub (
i_a,
i_b,
i_a_g,
i_b_g,
i_bor,
o_sub,
o_sub_g,
o_b
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
input i_bor;
output [WIDTH-1:0] o_sub;
output signed [WIDTH:0] o_sub_g;
output o_b;
wire fs0_bor;
wire fs1_bor;
wire fs2_bor;
wire... | 7.148356 |
module h_sub (
i_a,
i_b,
o_sub,
o_b
);
input i_a, i_b;
output o_sub, o_b;
assign o_sub = i_a ^ i_b;
assign o_b = !i_a & i_b;
endmodule
| 7.262048 |
module bit1_mux (
i_ctrl,
i_data0,
i_data1,
i_data2,
i_data3,
i_data4,
o_data
);
input [2:0] i_ctrl;
input i_data0, i_data1, i_data2, i_data3, i_data4;
output o_data;
wire o_data0;
wire o_data1;
wire o_data2;
wire o_data3;
wire o_data4;
wire inv_i_ctrl0;
wire inv_i_ct... | 6.564483 |
module bit4_mux(
i_ctrl,
i_data0,
i_data1,
i_data2,
i_data3,
i_data4,
o_data,
);
parameter WIDTH = 4;
input [WIDTH-2:0] i_ctrl;
input [WIDTH-1:0] i_data0, i_data1, i_data2, i_data3, i_data4;
output [WIDTH-1:0] o_data;
bit1_mux mx0(
.i_data0(i_data0[0]),
.i_data1(i_data1[0]),
.i_data2(i_data2[0]),
.i_data3(i_data3[... | 7.917164 |
module bit4_mux_gm (
i_ctrl_g,
i_data0_g,
i_data1_g,
i_data2_g,
i_data3_g,
i_data4_g,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-2:0] i_ctrl_g;
input [WIDTH-1:0] i_data0_g, i_data1_g, i_data2_g, i_data3_g, i_data4_g;
output reg [WIDTH-1:0] o_data_g;
always @* begin
case (... | 6.788316 |
module bit1_nand (
i_a,
i_b,
o_data
);
input i_a, i_b;
output o_data;
nand (o_data, i_a, i_b);
endmodule
| 7.470001 |
module bit4_nand (
i_a,
i_b,
i_a_g,
i_b_g,
o_data,
o_data_g
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_a, i_b, i_a_g, i_b_g;
output [WIDTH-1:0] o_data, o_data_g;
bit1_nand bn0 (
.i_a(i_a[0]),
.i_b(i_b[0]),
.o_data(o_data[0])
);
bit1_nand bn1 (
.i_a(i_a... | 7.314856 |
module task2_module (
clk,
rst_n,
i1_a,
i2_b,
i1,
i2
);
input clk;
input rst_n;
input [8:0] i1_a;
input [8:0] i2_b;
output [7:0] i1;
output [7:0] i2;
/***********************/
reg [8:0] rData1;
reg [8:0] rData2;
always @(posedge clk or negedge rst_n) begin
if (!rst_... | 6.678459 |
module task3_module (
input clk,
input rst_n,
input [2:0] index_in,
output reg [2:0] index_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) index_out <= 3'd0;
else index_out <= index_in;
end
endmodule
| 7.268131 |
module task4_module (
input clk,
input rst_n,
input [7:0] rom_data,
input data_valid,
input [2:0] index,
output reg [2:0] rgb
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) rgb <= 3'b000;
else rgb <= data_valid ? {rom_data[index], rom_data[index], rom_data[index]} : 3'b00... | 7.644375 |
module decoder (
i_data,
o_data
);
parameter WIDTH = 2;
input [WIDTH-1:0] i_data;
output [2**WIDTH-1:0] o_data;
genvar i;
generate
for (i = 0; i < 2 ** WIDTH; i = i + 1) begin : DC
assign o_data[i] = (i_data == i) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
| 7.018254 |
module mux (
i_sel,
i_d0,
i_d1,
i_d2,
i_d3,
i_d4,
o_data
);
parameter WIDTH = 4;
input [2:0] i_sel;
input [WIDTH-1:0] i_d0, i_d1, i_d2, i_d3, i_d4;
output [WIDTH-1:0] o_data;
wire [7:0] one_hot;
genvar i;
decoder #(
.WIDTH(3)
) decoder_inst (
.i_data(i_sel),
... | 7.162551 |
module bitwise_nand (
i_var1,
i_var2,
o_res
);
parameter WIDTH = 4;
input [WIDTH-1:0] i_var1, i_var2;
output [WIDTH-1:0] o_res;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : NAND
nand nand_inst (o_res[i], i_var1[i], i_var2[i]);
end
endgenerate
endmodule
| 7.116582 |
module taskAndFunction (
input [7:0] x,
output [7:0] z
);
assign z = ~x;
endmodule
| 6.561671 |
module taskAndFunction_tb ();
reg [7:0] x;
wire [7:0] z;
reg [7:0] w;
taskAndFunction DUT (
x,
z
);
task sum(input [3:0] a, b, output [7:0] c);
begin
c = a + b;
end
endtask
function [7:0] sub(input [3:0] a, b);
begin
sub = a - b;
end
endfunction
initial ... | 6.561671 |
module TaskFrequencyMeter (
input clk_50M, //标准信号，50M
input rst, //复位信号
input [7:0] sw, //拨码开关输入
input signal_in, //输入待测信号1~10M
output signal_out, //输出待测信号，1~10M
output [31:0] M, //标准信号计数值
output [31:0] N, //待测信号计数值
output gate_out //实际阀门输出（也就是精确门）
);
reg [31:0] M_reg;
reg ... | 7.601453 |
module: Task
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TaskTest;
// Inputs
reg CLK;
reg RST;
reg WRN;
reg REN;
reg [7:0] IN;
reg LIFO;
reg FIFO;
// Outputs
wire [7:... | 6.912134 |
module task_axilm (
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] AXI_AWADDR,
output reg [ 3:0] AXI_AWCACHE,
output reg [ 2:0] AXI_AWPROT,
output reg AXI_AWVALID,
input AXI_AWREADY,
// Write Data Channel
outp... | 6.645389 |
module task_axism (
input RST_N,
input CLK,
output AXIS_TCLK,
output reg [31:0] AXIS_TDATA,
output reg AXIS_TKEEP,
output reg AXIS_TLAST,
input AXIS_TREADY,
output reg [ 3:0] AXIS_TSTRB,
output reg AXIS_TVALID
);
initial begin
#0;
... | 7.731861 |
module test;
task foo;
begin
$display("PASSED");
end
endtask
task bar;
begin
test.foo;
end
endtask
initial begin
test.bar;
end
endmodule
| 7.273034 |
module task_calling (
temp_a,
temp_b,
temp_c,
temp_d
);
input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v"
always @(temp_a) begin
convert(temp_a, temp_b);
end
always @(temp_c) begin
convert(temp_c, temp_d);
end
endmodule
| 6.886644 |
module task_tb ();
reg [3:0] a, b;
wire [3:0] sum;
wire cout;
integer i;
adder a1 (
a,
b,
sum,
cout
);
initial begin
$dumpfile("output.vcd");
$dumpvars(0);
end
initial begin
#30 $finish;
end
always dealy;
task dealy;
begin
#5 a = $random;
... | 6.935819 |
modules
An example for the book
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Variables:
clk: clock for processing
RD: read flag
EN: module counter input
CLR: module coun... | 7.059705 |
module task_total (
input CLK,
input RST,
input [7:0] width,
output reg [16:0] area
);
//Load other module(s)
//Definition for Variables in the module
//Functions for area calculation
function [15:0] circle(input [7:0] diameter);
begin
circle = (24'd201 * {16'h0, diameter} * {16'h0,... | 8.097842 |
module tau640 (
//X1 (Bt.656 from Tau640)
input raw_in_vclk,
input raw_in_scl,
input raw_in_sda,
input [7:0] raw_in_data,
//XS1 (Bt.656 to display)
output raw_out_vclk,
output raw_out_scl,
output raw_out_sda,
output [7:0] raw_out_data,
//XS2 (YVYU to Banan... | 7.615987 |
module tauConfig (
clk,
rst_n,
din,
sin,
dout,
sout
);
input clk;
input rst_n;
input [7:0] din;
input sin;
output reg [7:0] dout;
output reg sout;
reg [2:0] cnt;
reg [7:0] sum;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
cnt <= 3'd0;
sum <= 8'd... | 6.617546 |
module tb ();
reg reset, clk;
initial begin
clk = 0;
reset = 1;
#60;
reset = 0;
#1000;
$finish;
end
always #10 clk = !clk;
wire valid;
wire [15:0] X0, X1;
AWGN a1 (
clk,
reset,
valid,
X0,
X1
);
endmodule
| 7.195167 |
module tawas_rcn (
input clk,
input rst,
input [ 4:0] thread_decode,
output [31:0] rcn_stall,
input rcn_cs,
input rcn_xch,
input rcn_wr,
input [31:0] rcn_addr,
input [2:0] rcn_wbreg,
input [3:0] rcn_mask,
input [31:0] rcn_wdata,
output reg rcn_load_en,
output reg ... | 6.786753 |
module tawas_rcn_master (
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [4:0] rsp_seq,
output ... | 7.623436 |
module tawas_rcn_master_buf (
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output full,
output rdone,
output wdone,
output [4:0] rsp_seq,
ou... | 7.623436 |
module taxicab_distance #(parameter N = 32)(
input [N-1:0] x1, y1, x2, y2,
output [N+1:0] dist
);
wire signed [N:0] dist_x12, dist_x21, dist_xabs, dist_y12, dist_y21, dist_yabs;
/*SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .S(dist_x12[N-1:0]), .CO(dist_x12[N]));
SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .S(dist_x21[N-... | 6.692693 |
module SUB_1 #(
parameter N = 32
) (
input [N-1:0] A,
B,
output [ N:0] D
);
wire CO;
assign D[N] = ~CO;
ADD #(
.N(N)
) ADD_ (
.A (A),
.B (~B),
.CI(1'b1),
.S (D[N-1:0]),
.CO(CO)
);
endmodule
| 6.563989 |
module Taximeter (
clk,
motor_cycle,
rst,
tube_11bit
);
input clk, motor_cycle, rst;
wire [3:0] distan_count_thous,
distan_count_hundr,
distan_count_tens,
distan_count_units,
price_count_hundr,
price_count_tens,
price_count_units;
wire [13:0] distan_count;
output [10:0] t... | 7.228361 |
module taxi_fare (
input wire clk,
input wire rst_n,
input wire wait_en,
input wire en,
input wire [11:0] distance_fare_per_pulse,
input wire [11:0] s_fare,
input wire ten_meter_pulse,
input wire [11:0] wait_fare_per_unit,
output wire [7:0] fare_a,
output wire [7:0] fare_b,
... | 8.86996 |
module taxi_fare_tb ();
reg clk;
reg rst_n;
reg en;
reg wait_en;
reg [11:0] distance_fare_per_pulse;
reg [11:0] s_fare;
reg ten_meter_pulse;
reg [11:0] wait_fare_per_unit;
wire [ 7:0] fare_a;
wire [ 7:0] fare_b;
wire [ 7:0] fare_c;
wire [ 7:0] fare_d;
... | 7.908547 |
module taylor_cos (
clk_80,
rst_80,
factorial2_80,
factorial4_80,
radian_80,
cos_value_80,
add_n4_value,
n2value_80,
n4value_80,
sub_n2_value_80,
radian2_pow4_80,
radian1_pow2_80
);
input clk_80, rst_80;
input [7:0] factorial2_80, factorial4_80, radian_80;
output [7... | 7.127344 |
module tb_TC3to3;
reg setn, resetn;
reg clock, sensor;
wire NS_G, NS_Y, NS_R, EW_G, EW_Y, EW_R;
wire [3:0] Q; // counter Q
tc_mealy_TC3to3 TC (
Q,
NS_G,
NS_Y,
NS_R,
EW_G,
EW_Y,
EW_R,
setn,
resetn,
clock,
sensor
); // TC
initial begin
... | 6.879433 |
module tb;
parameter INPUT_WIDTH = 16;
parameter INPUT_LENGTH = 18;
parameter INPUTS_NUMBER = 115200;
parameter OUTPUT_WIDTH = 38;
parameter OUTPUT_LENGTH = 18;
parameter FIR_WIDTH = 64;
parameter COEFF_LENGTH = 7;
reg clk, rst;
reg [ INPUT_WIDTH - 1:0] DATA_IN [0:INPUTS_NUMBER - 1];
r... | 6.746419 |
module tb_ban_reg_micro;
reg [5:0] Sel_reg;
reg W;
reg [7:0] DW;
wire [7:0] Rx;
wire [7:0] Ry;
reg rst;
reg clk;
ban_reg_micro uut (
.Sel_reg(Sel_reg),
.W(W),
.DW(DW),
.Rx(Rx),
.Ry(Ry),
.rst(rst),
.clk(clk)
);
initial begin
rst = 1;
clk = 0;
Se... | 6.680054 |
module tb_Bus_micro;
reg [1:0] Sel_outbus;
reg [7:0] Rx;
reg [7:0] Ry;
reg [7:0] Num;
wire [7:0] o_salida_datos;
wire [7:0] o_direccion_datos;
wire RW;
reg rst;
reg clk;
Bus_micro uut (
.Sel_outbus(Sel_outbus),
.Rx(Rx),
.Ry(Ry),
.Num(Num),
.o_salida_datos(o_salida_dato... | 6.563347 |
module tb_qint ();
// QBUS signals
reg RINIT, RDIN, RIAKI;
reg [4:7] RIRQ;
wire TIAKO;
wire [4:7] TIRQ;
// internal controls
reg interrupt_request;
wire assert_vector;
reg qclk = 1;
always @(*) #25 qclk <= ~qclk; // 20 MHz clock (50ns cycle time)
// simulate an int... | 6.930521 |
module tsense_read_tb ();
wire CS, SCK, SIO;
reg RSTN, SYSCLK;
wire [7:0] dbugout;
wire [7:0] dataSeg;
wire [1:0] disp;
//Task for simple test
task testRead;
begin
#15 RSTN = 1'b1;
end
endtask
//Instiate LM07
LM07 tsense (
.CS (CS),
.SCK(SCK),
.SIO(SIO)
);
//I... | 7.252947 |
module position simulation top module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
localparam K_W = 3;
reg clk;
reg rst_n;
reg next_pos;
reg [3:0] row;
reg [3:0] col;
reg [(EXP+MAN+1)*K_W-1:0] data0;
reg [(EXP+MAN+1)*K_W-1:0] data1;
initial begin
... | 6.711652 |
module position simulation top module
`timescale 1ns/1ps
module top;
reg clk;
reg rst_n;
reg next_pos;
reg [3:0] row;
reg [3:0] col;
reg end_pos;
localparam EXP = 8;
localparam MAN = 23;
initial begin
clk = 1'b1;
rst_n = 1'b0;
next_pos = 1'b0;
#10
rst_... | 6.711652 |
module tb ();
reg clk;
reg a;
reg b;
reg bin;
wire d;
wire borrow_out;
initial begin
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
initial begin
#100;
a = 1'b0;
b = 1'b0;
bin = 1'b0;
#20;
a = 1'b0;
b = 1'b0;
bin = 1'b1;
#20 a = 1'... | 7.195167 |
module testbench;
reg clk500;
initial clk500 = 1'b0;
always #1 clk500 = ~clk500;
wire nclk;
reg nreset;
divider div (
.clk(clk500),
.nreset(nreset),
.in_factor(3),
.nclk(nclk)
);
initial begin
$dumpfile("out.vcd");
$dumpvars(0, testbench);
nreset = 0;
#10;
... | 7.015571 |
module tb19 ();
reg [ 7:0] i_a;
reg [ 7:0] i_b;
wire [15:0] o_y;
initial begin
i_a = 8'd0;
#20 i_a = 8'd10;
#20 i_a = 8'd128;
#20 i_a = 8'd255;
end
initial begin
i_b = 8'd255;
#20 i_b = 8'd128;
#20 i_b = 8'd128;
#20 i_b = 8'd255;
end
test19 unsigned_mul (
.i_a(... | 6.59628 |
module tb19 ();
reg signed [ 7:0] i_a;
reg signed [ 7:0] i_b;
wire signed [14:0] o_y;
initial begin
i_a = 8'sd0;
#20 i_a = -8'sd10;
#20 i_a = -8'sd128;
#20 i_a = 8'sd127;
end
initial begin
i_b = 8'sd127;
#20 i_b = +8'sd100;
#20 i_b = -8'sd128;
#20 i_b = 8'sd127;
end
... | 6.59628 |
module tb19 ();
reg signed [ 7:0] i_a;
reg [ 7:0] i_b;
wire signed [15:0] o_y;
initial begin
i_a = 8'sd0;
#20 i_a = -8'sd10;
#20 i_a = -8'sd128;
#20 i_a = 8'sd127;
end
initial begin
i_b = 8'd127;
#20 i_b = 8'd100;
#20 i_b = 8'd255;
#20 i_b = 8'd255;
end
test19... | 6.59628 |
module TB1;
reg clk;
reg rst, clk_en;
wire [3:0] leds;
integer EndOfSimulation;
integer i;
parameter ONE = 1'b1;
// Initial statement for signal initialization (reset, clk, EndOfSimulation)
initial begin
clk = 0;
rst = 0;
#(10) rst = 1;
#2000 $finish;
end
// Always statement to d... | 6.883055 |
module top_module ();
reg clk, in, out;
reg [2:0] s;
initial begin
#0 clk = 0;
in = 0;
s = 3'd2;
#10 s = 3'd6;
#10 s = 3'd2;
in = 1;
#10 s = 3'd7;
in = 0;
#10 s = 3'd0;
in = 1;
#30 in = 0;
end
always begin
#5 clk = ~clk;
end
q7 q (
clk,
in,
... | 6.627149 |
module tb20;
reg [7:0] i_data;
wire [3:0] o_count;
initial begin
i_data = 8'b1111_1111;
#100 repeat (51) #20 i_data = i_data - 'd5;
end
count1s count1s (
.i_data (i_data),
.o_count(o_count)
);
endmodule
| 6.685379 |
module tb_edge_det;
reg clk, rst_n, data;
wire rise_edge;
wire fall_edge;
wire data_edge;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
initial begin
repeat (100) begin
@(posedge clk) data = {$random};
end
$fin... | 6.661764 |
module tb28 ();
reg clk, rst_n, data_i;
wire [7:0] data_o;
initial
fork
clk = 1'b0;
rst_n = 1'b0;
#20 rst_n = 1'b1;
#10 data_i = 1'b1;
join
always #10 clk = ~clk;
always #15 data_i = ~data_i;
test28 test28 (
.clk (clk),
.rst_n (rst_n),
.data_i(data_i),
.dat... | 6.693302 |
module tb29 ();
reg clk, rst_n, data;
wire flag_101;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
initial begin
repeat (100) begin
@(negedge clk) data = {$random};
end
$finish;
end
/* initial begin
$dum... | 6.704709 |
module TB2;
parameter N = 4;
reg clk, rst, clk_en;
wire [3:0] leds;
integer EndOfSimulation;
integer i;
parameter ONE = 1'b1;
// Initial statement for signal initialization (reset, clk, EndOfSimulation)
initial begin
clk = 0;
rst = 0;
#20 rst = 1;
#30 rst = 0;
#20 rst = 1;
#200... | 7.42332 |
module tb ();
reg cin;
wire cout;
wire good;
reg c;
reg [31:0] Operand1;
reg [31:0] Operand2;
wire [31:0] Result;
reg [31:0] sum;
m_adder m_adder (
.i_cIn_1 (cin),
.i_adderOperand1_32(Operand1),
.i_adderOperand2_32(Operand2),
.o_adderSum_32 (Result),
.o_cOu... | 7.002324 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_... | 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_... | 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [1:0] state;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
... | 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_... | 6.893211 |
module tb_lab ();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [64:0] out;
wire out_valid;
reg [5:0] count;
reg signed [64:0] correct_ans;
reg error;
reg signed [63:0] temp_a;
reg signed [63:0] temp_b;
lab m1 (
CLK,
reset,
in_a,
in_b,
out,
out_... | 6.893211 |
module tb32reg;
reg [31:0] d;
reg clk, reset;
wire [31:0] q;
reg_32bit R (
q,
d,
clk,
reset
);
initial begin
$monitor($time, " output :%b", q);
end
always @(clk) #5 clk <= ~clk;
initial begin
clk = 1'b1;
reset = 1'b0; //reset the register
#20 reset = 1'b... | 7.21149 |
module TB3;
parameter N = 4;
parameter cycle = 10;
parameter distance = 100000000; //
reg clk, rst, clk_en;
wire [N-1:0] leds;
integer EndOfSimulation;
// Drive the reset and the EndOfSimulation signal
initial begin
// Your code goes here
clk = 0;
rst = 0;
#20 rst = 1;
#distance $... | 6.735825 |
module tb43 ();
reg clk;
reg rst_n;
reg [ 7:0] i_data;
wire [10:0] o_y;
initial begin
clk = 1;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
#3000 $finish;
end
always @(posedge clk) i_data = {$random};
test43 #(8, 8) test43 (
... | 6.819205 |
module tb44 ();
reg clk;
reg rst_n;
reg [7:0] i_data;
wire [7:0] o_y;
initial begin
clk = 1;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
// #1000 $finish;
end
always @(negedge clk) i_data = {$random};
test44 test44 (
.clk... | 7.028711 |
module TB3;
parameter N = 4;
parameter cycle = 10;
parameter distance = 100000000; //
reg clk, rst, clk_en;
wire [N-1:0] leds;
integer EndOfSimulation;
// Drive the reset and the EndOfSimulation signal
initial begin
// Your code goes here
clk = 0;
rst = 1;
#20 rst = 0;
#distance $... | 6.735825 |
module tb_cnt( );
reg clk,rst_n;
wire [3:0] o_cnt;
initial fork
clk = 1'b0;
rst_n = 1'b0;
#20 rst_n = 1'b1;
#455 rst_n = 1'b0;
#475 rst_n = 1'b1;
#600 $finish;
join
always #10 clk = ~ clk;
cnt** cnt4(
.clk (clk ),
.rst_n (rst_n),
.o_cnt (o_cnt)
);
endmodule
| 6.857027 |
module tb ();
reg cin;
wire cout;
wire good;
reg c;
reg [63:0] Operand1;
reg [63:0] Operand2;
wire [63:0] Result;
reg [63:0] sum;
m_adder m_adder (
.i_cIn_1 (cin),
.i_adderOperand1_64(Operand1),
.i_adderOperand2_64(Operand2),
.o_adderSum_64 (Result),
.o_cOu... | 7.002324 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bloodAbnormalityDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////... | 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bloodPHAnalyzer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module... | 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: BloodTypeclassification
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////... | 8.163945 |
module tbBRL ();
reg clk, rst_n, en;
initial begin
en = `ON;
clk = `HIGH;
rst_n = `HIGH;
#44 rst_n = `LOW;
#15 rst_n = `HIGH;
end
always #1 clk = ~clk;
reg [31:0] tmp;
always #4 tmp = $random;
//reg en;
//wire wave;
//wire end_tick;
//reg [7:0] mem[99:0];
//reg [9:0] cyc_du... | 7.131318 |
module tbDoodle ();
localparam SCR_W = 30;
localparam SCR_H = 30;
localparam COUNT_PIXELS = SCR_W * SCR_H;
wire [23:0][COUNT_PIXELS - 1:0] screen; // r,g,b (8bit, 8bit, 8bit)
reg left, right, clk, reset;
GameBox _gameBox (
screen,
left,
right,
clk,
reset
);
initial begin... | 6.685467 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: EightBitRippleCarryAdder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////... | 8.163945 |
module tben (
output _this,
output inho,
input _bit,
input inhi
);
wire bit_n;
// ARITH.NET (504) - inho : or2
assign inho = _bit | inhi;
// ARITH.NET (505) - bit\ : iv
assign bit_n = ~_bit;
// ARITH.NET (506) - this : nr2
assign _this = ~(bit_n | inhi);
endmodule
| 6.69306 |
module tbenw (
output _this,
input _bit,
input inhi
);
wire bit_n;
// ARITH.NET (516) - bit\ : iv
assign bit_n = ~_bit;
// ARITH.NET (517) - this : nr2
assign _this = ~(bit_n | inhi);
endmodule
| 6.784942 |
module tbfifosemaphore;
parameter initialCount = 1;
integer semaphore_count;
integer first_waiting_pid;
integer last_waiting_pid;
integer resume_pid;
initial begin
semaphore_count = initialCount;
first_waiting_pid = 1;
last_waiting_pid = 0;
resume_pid = 0;
end
function integer GetNum... | 6.940023 |
module TBGlycemiclndexCalculator;
reg [7:0] bloodSensor;
wire [3:0] glycemicIndex;
GlycemiclndexCalculator q (
.bloodSensor,
.glycemicIndex
);
initial begin
bloodSensor = 8'b10101010;
#10 bloodSensor = 8'b00010010;
#10 bloodSensor = 8'b10011111;
#10 bloodSensor = 8'b01110001... | 7.230468 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: HealthcareSystemPhase1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
... | 8.163945 |
module i2c_controller_tb ();
// Inputs
reg clk;
reg rst;
reg [6:0] addr;
reg [7:0] data_in;
reg enable;
reg rw;
// Outputs
wire [7:0] data_out;
wire ready;
// Bidirs_ios
wire i2c_sda;
wire i2c_scl;
// Instantiate the Unit Under Test (UUT)
i2cmaster master (
.clk(clk),
.rst(rst... | 7.808223 |
module tbird_fsm (
input clk,
reset,
left,
right,
haz,
output reg [5:0] light
);
//------------------------------------------------------------------
// Registry States
//------------------------------------------------------------------
reg [2:0] state, nextstate;
//---------------... | 8.768871 |
module TBLC #(
parameter M = 11
) (
input wire [15:0] o,
input wire [15:0] x,
output wire [16+3-1-M+1:0] tlog /* truncated logarithm, M=11, tlog[8:0] */
);
reg [3:0] k;
reg [16-1-M-1+1:0] y;
assign tlog = {k, y};
always @(*) begin
case (o)
/*1.*/
16'b1000_0000_0000_0000: begin... | 6.986891 |
module TBLC_11 #(
parameter M = 11
) (
input wire [15:0] o,
input wire [15:0] x,
output wire [16+3-1-M+1:0] tlog /* truncated logarithm, M=11, tlog[8:0] */
);
reg [3:0] k;
reg [16-1-M-1+1:0] y; /* M=11, y[4:0] */
assign tlog = {k, y};
always @(*) begin
case (o)
/*1.*/
16'b100... | 6.779167 |
module TBLC_5 #(
parameter M = 5
) (
input wire [15:0] o,
input wire [15:0] x,
output wire [16+3-1-M+1:0] tlog /* truncated logarithm, M=5 , tlog[14:0] */
);
reg [3:0] k;
reg [16-1-M-1+1:0] y; /* M=5 , y[10:0] */
assign tlog = {k, y};
always @(*) begin
case (o)
/*1.*/
16'b100... | 6.783806 |
module tbman (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslverr
... | 6.938784 |
module tbman_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_psl... | 7.760792 |
module tbmast;
// Inputs
reg [6:0] address;
reg [7:0] register;
reg [7:0] data;
reg [7:0] data_wr;
reg clk;
reg rw;
// Outputs
wire sda;
wire scl;
// Instantiate the Unit Under Test (UUT)
master uut (
.address(address),
.register(register),
.clk(clk),
.rw(rw),
.s... | 6.791259 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Multiplier4x4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T... | 8.163945 |
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