code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TbNeokeonGammafun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [127:0] inDataState = 128'b0;
wire [127:0] outDa... | 6.525215 |
module TbNeokeonROTL32by1fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.587286 |
module TbNeokeonROTL32by2fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.587286 |
module TbNeokeonROTL32by5fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.587286 |
module TbNeokeonROTL32by8fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.587286 |
module TbNeokeonROTR32by1fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.758934 |
module TbNeokeonROTR32by2fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.758934 |
module TbNeokeonROTR32by5fun;
/////////////////////////////////////////
parameter inClkp = 10;
/////////////////////////////////////////
reg inClk = 1'b0;
always begin
#(inClkp / 2) inClk = !inClk;
end
////////////////////////////////////////
reg [31:0] inDataWord = 32'b0;
wire [31:0] outp... | 6.758934 |
module TBreg ();
reg [31:0] A, B;
reg clk, rst = 1, en = 1;
wire [31:0] AA;
genvar j;
generate
for (j = 0; j <= 31; j = j + 8) begin : row
regmaster Num1 (
A[j+7:j],
clk,
rst,
en,
AA[j+7:j]
);
end
endgenerate
initial begin
#800 clk ... | 6.756139 |
module tbriscv;
reg rst_n;
reg clk;
riscv_top DUT (
.rst_n(rst_n),
.clk (clk)
);
initial begin
clk = 1'b0;
#50;
repeat (79) begin
clk = 1'b1;
#50 clk = 1'b0;
#50;
end
clk = 1'b1;
#50;
// dumped values till 2 us
end
// "Constant Pattern"
... | 6.813861 |
module TBT (
clk,
rst,
start,
data,
en,
addr,
fin,
result
);
input clk, rst, start;
input [4 : 0] data;
output en, fin;
output [4 : 0] addr, result;
endmodule
| 6.843925 |
module Top(
clk,
rst_n,
);
input clk , rst_n;
wire clk_out;
time_change u1(clk,rst_n,clk_out);
endmodule
| 7.232326 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: temperatureAbnormalityDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/////////////////////////////////////////////////////////////////////////... | 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: temperatureAnalyzer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
mo... | 8.163945 |
module2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: temperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
... | 8.163945 |
module TBT_tb;
//Clock period
parameter cyc = 30;
parameter dataWidth = 5;
parameter memWidth = 5;
parameter SEQ = 33;
reg [dataWidth - 1 : 0] dataROM [0 : SEQ - 1];
reg [ memWidth - 1 : 0] maxSize;
reg clk, rst, start;
reg [dataWidth - 1 : 0] data;
wire fin, en;
wire [dataWidth - 1 : 0] resul... | 8.294132 |
module tbuart (
input ser_rx
);
reg [3:0] recv_state;
reg [2:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [8*50-1:0] recv_buf_data; // 50 characters. Increase as needed for tests.
reg clk;
initial begin
clk <= 1'b0;
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_da... | 8.711715 |
module TbUartRx();
localparam clockRate = 76_800_000;
localparam uartRate = 12_000_000;
localparam real clockDt = 1_000_000_000.0 / clockRate;
localparam real uartDt = 1_000_000_000.0 / uartRate;
reg clk = 0;
reg uartClk = 0;
reg uart = 1;
wire ... | 6.918471 |
module TbUartRxTest();
localparam clockRate = 60_000_000;
localparam baudRate = 12_000_000;
localparam cycleBits = 12;
localparam real clkDt = 1_000_000_000.0 / clockRate;
localparam real uartDt = 1_000_000_000.0 / baudRate;
reg clk = 0;
reg uartClk = 0;
reg uart = 1;
... | 7.101164 |
module tbuart_microwatt #(
parameter baud_rate = 115200
) (
input ser_rx
);
reg [3:0] recv_state;
reg [2:0] recv_divcnt;
reg [7:0] recv_pattern;
reg clk;
initial begin
clk <= 1'b0;
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
end
// Our simulation is in nanosecond steps... | 7.536785 |
module tbufcam_buf (
clk,
rst,
except,
except_thread,
new_addr,
new_thread,
new_en,
chk_addr0,
chk_match0,
chk_addr1,
chk_match1,
free
);
localparam WIDTH = 11;
input clk;
input rst;
input except;
input except_thread;
input [WIDTH-1:0] new_addr;
input new_... | 6.574546 |
module tbufcam (
clk,
rst,
except,
except_thread,
new_addr,
new_thread,
new_en,
chk_addr0,
chk_match0,
chk_addr1,
chk_match1,
free
);
localparam WIDTH = 11;
localparam BUF_COUNT = 4;
input clk;
input rst;
input except;
input except_thread;
input [WIDTH-1:0... | 6.974965 |
module tb_seg_595_static;
// parameter CNT_MAX = 25'd24;
reg sys_clk;
reg sys_rst_n;
wire ds;
wire shcp;
wire stcp;
wire oe;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
seg_595_static seg_595_static_inst (
.s... | 8.260895 |
module tb_034();
//
// 1801VP1-034 pins, register mode
//
wire [15:0] lat_nAD;
reg [15:0] lat_nD;
reg lat_C;
reg lat_nDME;
integer lat_i;
//
// 1801VP1-034 pins, pio mode
//
wire [7:0] pio_D;
wire [7:0] pio_nC;
wire pio_nCOM;
reg [7:0] pio_A;
reg [7:0] pio_B;
reg pio_nR;
reg ... | 6.732185 |
module: miniRISC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_1;
// Inputs
reg clk;
reg rst;
// Outputs
wire [31:0] out1;
wire [31:0] out2;
// Instantiate the Unit Un... | 6.91385 |
module tb_1553;
reg tb_data_clk = 0;
reg tb_rst = 0;
wire [ 1:0] tb_dout;
wire tb_en_dout;
reg [15:0] tb_tdata;
reg tb_tvalid;
reg [ 7:0] tb_tuser;
wire tb_tready;
//1ns
localparam CLK_PERIOD = 50;
localparam RST_PERIOD = 100;
//device under test
util... | 6.751604 |
module tb_1bit_full_adder;
// Inputs
reg a, b, c;
// Outputs
wire sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
fa_1bit uut (
.a(a),
.b(b),
.cin(c),
.sum(sum),
.cout(cout)
);
initial begin
$dumpfile("tb_1bit_full_adder.vcd");
$dumpvars(0, tb_1bit_full... | 6.879291 |
module: miniRISC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_2;
// Inputs
reg clk;
reg rst;
// Outputs
wire [31:0] out1;
wire [31:0] out2;
// Instantiate the Unit Un... | 6.91385 |
module tb_2_input_nand_gate;
// Inputs
reg A, B;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
nand2 uut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
$dumpfile("tb_2_input_nand_gate.vcd");
$dumpvars(0, tb_2_input_nand_gate);
// Initialize Inputs
A = 0;
B =... | 7.127038 |
module tb_32bit_carry_ripple_adder;
parameter N = 32;
// Inputs
reg [N-1:0] input_a = 0;
reg [N-1:0] input_b = 0;
reg carry_in = 0;
// Outputs
wire [N-1:0] final_sum;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
ripple_carry_adder #(
.WIDTH(N)
) uut (
.input_a (input_a),
... | 8.043136 |
module tbRegFile32;
reg Clock, Reset, RegWrite;
reg [4:0] ReadReg1, ReadReg2, WriteRegNo;
reg [31:0] WriteData;
wire [31:0] ReadData1, ReadData2;
RegFile_32 rgf (
ReadData1,
ReadData2,
Clock,
Reset,
RegWrite,
ReadReg1,
ReadReg2,
WriteRegNo,
WriteData
);
... | 6.672416 |
module tb_3_input_and_gate (); // Test bench fortb_ and_gate.v
reg a, b, c; // a reg, to allow us to assign the input, and a wire to receive the output
wire out;
three_input_and_gate uut (
out,
a,
b,
c
); // this instantiates a and gate, uut is a label
initial begin
a = 1'b0; /... | 6.993267 |
module tb_3_input_or_gate (); // Test bench fortb_ and_gate.v
reg a, b, c; // a reg, to allow us to assign the input, and a wire to receive the output
wire out;
three_input_or_gate uut (
out,
a,
b,
c
); // this instantiates a and gate, uut is a label
initial begin
a = 1'b0; // ... | 6.920155 |
module dmaer (
input wire clk,
input wire rst_n,
input wire start,
input wire rnw_in,
output reg inprogress,
output reg req,
output reg rnw,
input wire ack,
input wire done
);
initial begin
inprogress = 1'b0;
req = 1'b0;
rnw = 1'b1;
end
alw... | 7.059175 |
module tb_RTL ();
reg A, B, C, D;
reg [1:0] Sin;
wire out;
m4to1_MUX_RTL test_RTLMUX (
out,
Sin,
A,
B,
C,
D
);
initial begin
A = 0;
B = 0;
C = 0;
D = 1;
Sin = 2'b11;
#250 A = 0;
B = 0;
C = 0;
D = 1;
Sin = 2'b11;
... | 6.587275 |
module tb_comparator8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire et;
wire gt;
comparator8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(et),
.gt(gt)
);
initial begin
A = 8'b00000001;
B = 8'b... | 6.843472 |
module: abc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_abc;
// Inputs
reg clk;
reg ce;
reg signed [11:0] a;
reg signed [11:0] b;
reg signed [11:0] c;... | 6.61642 |
module tb_adv_fsm;
reg clk, reset, a, b;
wire z;
parameter IDLE = 0, SA = 1, SB = 2, SAB = 3;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
abro UUT (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.z(z)
);
initial // Clock generation
... | 7.116394 |
module tb_accumCol;
parameter DATA_WIDTH = 8; // number of bits for one piece of data
parameter MAX_OUT_ROWS = 128; // output height of largest matrix
parameter MAX_OUT_COLS = 128; // output width of largest possible matrix
parameter SYS_ARR_COLS = 16; // height of the systolic array
localparam NUM_ACCU... | 6.709093 |
module tb_aclk_timegen ();
reg clk, reset, reset_count, fast_watch;
wire one_minute, one_second;
aclk_timegen dut (
clk,
reset,
reset_count,
fast_watch,
one_minute,
one_second
);
initial begin
clk = 1;
forever #5 clk = !clk;
end
initial begin
#15;
reset ... | 7.465918 |
module TB_acm_controller ();
wire clk;
reg reset;
wire [7:0] ACM_rdata;
wire [7:0] ACM_wdata;
wire [7:0] ACM_addr;
wire ACM_wen;
wire ACM_reset;
wire ACM_clk;
reg wb_cyc_i, wb_stb_i, wb_we_i;
reg [15:0] wb_adr_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
wire wb_ack_o;
acm_controller ac... | 7.588986 |
module tb ();
reg clk, reset;
wire [31:0] porta, portb;
ACog cog0 (
.clk_in (clk),
.reset_in(reset)
);
always #6.25 clk = ~clk;
initial begin
$dumpfile("acog.vcd");
$dumpvars(0, tb);
clk = 0;
reset = 1;
#61 reset = 0;
#160000 $finish;
end
endmodule
| 7.195167 |
module tb_action_engine #(
parameter STAGE = 0,
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter ACT_LEN = 25
) ();
reg clk;
reg rst_n;
//signals from lookup to ALUs
reg [ PHV_LEN-1:0] phv_in;
reg phv_valid_in;
reg... | 8.348227 |
module TB_adc_config_mux();
wire sys_rst;
wire sys_clk;
/***************** DUT ***************/
adc_config_mux #(
.INTERLEAVED (0)
) adc_config_mux_inst (
.clk (sys_clk),
.rst (sys_rst),
.request (1'b0),
.ddrb_i (1'b0),
.mode_i (1'b0),
.config_start_i (1'b0),
.config_busy_... | 7.801573 |
module tb_adc_diff;
reg tb_data_clk = 0;
reg tb_rst = 0;
//slave
reg [7:0] tb_data;
reg tb_valid;
reg tb_valid_off;
reg tb_valid_toggle = 0;
reg tb_enable;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
// util_adc_diff
util_adc_diff #(
... | 8.588449 |
module tb;
initial begin $$dumpfile("build/prefix_adder.vcd"); $$dumpvars(0,tb); end
reg [$n:0] term0,term1;
reg cin;
wire [$n:0] sum;
wire cout;
prefix_adder p0(term0,term1,cin,sum,cout);
initial begin
$test
end
endmodule
| 7.280203 |
module.
`timescale 1ns/1ns
`include "add1bit.v"
module tb_add1bit;
reg a, b, c_in;
wire sum, c_out;
add1bit test_add1bit(a, b, c_in, sum, c_out);
initial begin
assign c_in = 1'b0;
$dumpfile("tb_add1bit.vcd");
$dumpvars(0, tb_add1bit);
$monitor("0x%0h + 0x%0h = 0x%0h (carry = %d... | 6.603418 |
module.
`timescale 1ns/1ns
`include "add2bit.v"
module tb_add1bit;
reg [1:0] a, b;
reg c_in;
wire [1:0] sum;
wire c_out;
add2bit test_add2bit(a, b, c_in, sum, c_out);
initial begin
assign c_in = 1'b0;
$dumpfile("tb_add2bit.vcd");
$dumpvars(0, tb_add1bit);
$mon... | 6.603418 |
module.
`timescale 1ns/1ns
`include "add4bit.v"
module tb_add1bit;
reg [3:0] a, b;
reg c_in;
wire [3:0] sum;
wire c_out;
integer i;
add4bit test_add4bit(a, b, c_in, sum, c_out);
initial begin
assign c_in = 1'b0;
$dumpfile("tb_add4bit.vcd");
$dumpvars(0, tb_ad... | 6.603418 |
module AdderTestbench;
reg [7:0] in;
wire [7:0] out;
Adder dut (
in,
out
);
initial begin
in = 0;
$display("Teste 1: Entrada = 1");
in = 1;
#1 $display("Saida = %d", out);
$display("Teste 2: Entrada = 2");
in = 2;
end
initial begin
$monitor("Tempo: %0d\tEntra... | 7.444627 |
module tb_adder_chains ();
parameter MIN_WIDTH = 8;
parameter ADDER_NUM = 4;
reg clk; // Clock
reg rst_n; // Asynchronous reset active low
reg [MIN_WIDTH * ADDER_NUM - 1:0] adder_din;
wire [MIN_WIDTH + ADDER_NUM - 1:0] adder_dout;
adder_chains #(
.MIN_WIDTH(MIN_WIDTH),
.ADDER_NUM(ADDER_NU... | 7.097643 |
module tb_top;
// TB_SIGNALS
reg clk, reset_b;
reg [15:0] a_in;
reg [15:0] b_in;
reg carry_in;
reg CG;
wire [15:0] sum_out;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
adder_clk_gating uut (
.clk(clk),
.reset_b(reset_b),
.a_in(a_in),
.b_in(b_in),
.carry_in... | 6.630961 |
module tb_adder_subtractor_4bit ();
reg [3:0] A;
reg [3:0] B;
reg sel;
wire [3:0] sum;
wire [3:0] sum_delay;
wire cout;
wire cout_delay;
adder_subtractor_4bit test_adder_subtractor_4bit (
.A(A),
.B(B),
.sel(sel),
.S(sum),
.cout(cout)
);
adder_subtractor_4bit_delay te... | 6.53318 |
module tb_adder_subtractor_4bit_delay ();
reg [3:0] A;
reg [3:0] B;
reg sel;
wire [3:0] sum;
wire [3:0] sum_delay;
wire cout;
wire cout_delay;
adder_subtractor_4bit_delay test_adder_subtractor_4bit_delay (
.A(A),
.B(B),
.sel(sel),
.S(sum_delay),
.cout(cout_delay)
);
... | 6.53318 |
module tb_adder_tree;
parameter WORD_SIZE = 8;
parameter BANK_SIZE = 4;
reg clk;
reg rst_n;
reg [ WORD_SIZE*BANK_SIZE-1:0] in;
wire [(WORD_SIZE+1)*(BANK_SIZE/2)-1:0] out;
adder_tree #(
.WORD_SIZE(WORD_SIZE),
.BANK... | 6.562762 |
module tb_adder_tree_var ();
localparam NUM = 18;
localparam LEN = 16;
localparam LEVEL = 5;
localparam LEN_LAST = LEN + LEVEL;
reg clk;
reg signed [LEN-1:0] in_inner[NUM-1:0];
reg [NUM*LEN-1:0] in;
wire [LEN_LAST-1:0] sum;
adder_tree_var_bit #(
.NUM(NUM),
.LEN(LEN)
) dut (
.clk(c... | 6.562762 |
module TB_addressGen;
/// when enabled, will generate address values from 0 to 1023, essentially a counter
/// then will raise done to high
reg clk, rst, gen_en, sobel_en;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGen(clk, rst, gen_en, sobel_en, addr, done);
addressGen UUT (... | 6.65016 |
module tb_address_generator ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_address_generator.vcd");
$dumpvars(0, tb_address_generator);
// #100000;
// $finish;
end
parameter RAND_BUSY = 1;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'... | 8.348644 |
module tb_address_generator_range ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_address_generator_range.vcd");
$dumpvars(0, tb_address_generator_range);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initi... | 8.348644 |
module tb_address_generator_step ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_address_generator_step.vcd");
$dumpvars(0, tb_address_generator_step);
#10000;
$finish;
end
parameter RAND_BUSY = 0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
... | 8.348644 |
module tb_addSub_4bit ();
wire [3:0] sum;
wire cout;
reg [3:0] a, b;
reg cin;
reg sel;
addSub_4bit addsub (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin),
.sel(sel)
);
initial begin
$dumpfile("tb_addSub_4bit.vcd");
$dumpvars;
end
initial begin
a ... | 7.67804 |
module tb_add_sub ();
reg [3:0] A, B; // Declaration of two four-bit inputs
reg sel; // and the one-bit input carry
wire [3:0] s; // Declaration of the five-bit outputs
wire v; // internal carry wires
add_sub DUT (
V,
s,
cout,
sel,
A,
B
);
initial begin
#10 A =... | 6.721562 |
module Tb_Administrador_de_Salidas ();
reg [2:0] RY;
reg [7:0] RX;
reg [2:0] Num;
reg [1:0] Sel_Salidas;
wire [7:0] o_Dataout;
wire [7:0] o_Addressdata;
wire ReadWrite;
Administrador_de_salidas uut (
.RY(RY),
.RX(RX),
.Num(Num),
.Sel_Salidas(Sel_Salidas),
.o_Dataout(o_Data... | 7.372853 |
module tb_adr #(
parameter ADR_WIDTH = 5
) ();
reg clk;
reg rst;
reg [ADR_WIDTH-1:0] adr_i;
reg [`CTR_MARMUX_WIDTH-1:0] ctr_marmux_i;
reg ctr_mar_reg_en_i;
reg ctr_pc_reg_en_i;
wire [ADR_WIDTH-1:0] adr_o;
integer j;
adr #(
.ADR_WIDTH(ADR_WIDTH)
) i_adr (
.clk_i(clk),
.rst_i(... | 6.636031 |
module: adt_term
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_adt_term;
// Inputs
reg clk;
reg reset_n;
reg rx;
reg tx_frame_start;
reg [7:0] data_ram;
reg [15:0] addr_... | 6.723427 |
module: canny_advanced
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_advanced;
// Inputs
reg clk;
reg reset;
// Instantiate the Unit Under Test (UUT)
canny_advanced canny... | 7.656574 |
module tb_adv_fsm;
reg clk, reset, x;
wire z;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
adv_fsm UUT (
.clk(clk),
.reset(reset),
.x(x),
.z(z)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period ... | 7.116394 |
module tb_adv_shifter;
reg clk, load, ena;
reg [ 1:0] amount;
reg [63:0] data;
wire [63:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
advshift UUT (
.clk(clk),
.load(load),
.amount(amount),
.data(data),
.ena(ena),
.q(q)
... | 7.101369 |
module tb_aes_control_unit ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
reg clk; // Clock
reg rst_n; // Asynchronous reset active low
reg i_en;
reg i_flag;
/****************... | 6.854026 |
module tb_aes_core_top ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
localparam RND_SIZE = 128;
localparam WRD_SIZE = 32;
localparam NUM_BLK = 4;
localparam MAX_CNT = 12;
localpara... | 7.132956 |
module tb_aes_data_path ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
localparam RND_SIZE = 128;
localparam WRD_SIZE = 32;
localparam NUM_BLK = 4;
localparam MAX_CNT = 11;
localpara... | 6.814903 |
module tb_aes_cipher ();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg tb_clk; //tb时钟信号
reg tb_reset; //tb重置信号
reg tb_init;
wire [127:0] tb_key; //对应轮数的密钥
reg [127:0] tb_plaintext;
wire [127:0] tb_ciphertext;
wire [ 31:0] tb_sboxw;... | 7.638538 |
module tb_aes_cipher ();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg tb_clk; //tb时钟信号
reg tb_reset; //tb重置信号
reg tb_init;
wire [127:0] tb_key; //对应轮数的密钥
reg [127:0] tb_plaintext;
wire [127:0] tb_ciphertext;
wire [ 31:0] tb_sboxw;... | 7.638538 |
module tb_aes_round ();
/**********************************************************************
* parameter Declaration
**********************************************************************/
parameter RND_SIZE = 128;
parameter WRD_SIZE = 32;
parameter CNT_SIZE = 4;
parameter NUM_BLK = 4;
/***************... | 6.85432 |
module AESL_automem_RoundKey (
Q,
CPU_RESETN,
E,
D,
CLK100M_IBUF_BUFG
);
output [7:0] Q;
input CPU_RESETN;
input [0:0] E;
input [7:0] D;
input CLK100M_IBUF_BUFG;
wire CLK100M_IBUF_BUFG;
wire CPU_RESETN;
wire [7:0] D;
wire [0:0] E;
wire [7:0] Q;
FDRE #(
.INIT(1'b0)
) \... | 6.546446 |
module tb_aes_wrapper ();
reg clk, rst;
wire bitti;
aes_wrapper aw (
clk,
rst,
bitti
);
always begin
clk = ~clk;
#5;
end
initial begin
clk = 0;
rst = 1;
#100;
rst = 0;
end
endmodule
| 6.552137 |
module tb_ahb2apb ();
parameter AHB_DATA_WIDTH = 32;
parameter AHB_ADDR_WIDTH = 32;
parameter APB_DATA_WIDTH = 32;
parameter APB_ADDR_WIDTH = 32;
reg ahb_hclk;
reg ahb_hrstn;
reg ahb_hsel;
reg [ 1:0] ahb_htrans;
reg [A... | 6.83351 |
module of Alarm clock
which is used to generate stimulus patterns for the DUT .
Date: 01/05/2018
Author: Maven Silicon
Email: online@maven-silicon.com
Version: 1.0
*********************************************************************************************/
module tb_alarm_clock();
reg clk,
... | 7.569403 |
module
//-------------------------------------------------------------------
module tb_alaw_coder();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_... | 8.13663 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module tb_alram1x;
////////////////////////////////////////////////////////////////////////////////
// Parameter declarations
parameter WID = 10; // 10-bit long data
parameter AWID = 2; // 2-bit long address (4 addresses)
parameter DEP = 1 << AWID; // DEP = 2**AWID
////////////////////////////////////... | 6.643206 |
module tb_alu ();
// Inputs
reg clk;
reg reset;
reg [15:0] a;
reg [15:0] b;
wire [15:0] c;
reg [7:0] cond;
wire en;
// Instantiate the Unit Under Test (UUT)
vmicro16_alu uut (
.op(5'h19),
.a (a),
.b (b),
.c (c)
);
// Instantiate the Unit Under Test (UUT)
branch bran... | 7.098069 |
module tb_alu_1 #(
parameter STAGE = 0,
parameter ACTION_LEN = 25,
parameter DATA_WIDTH = 48
) ();
localparam STAGE_P = 0;
reg clk;
reg rst_n;
//input from sub_action
reg [ACTION_LEN-1:0] action_in;
reg action_valid;
reg [DATA_WIDTH-1:... | 8.144164 |
module tb_alu_2 #(
parameter STAGE = 0,
parameter ACTION_LEN = 25,
parameter DATA_WIDTH = 32
) ();
reg clk;
reg rst_n;
//input from sub_action
reg [ACTION_LEN-1:0] action_in;
reg action_valid;
reg [DATA_WIDTH-1:0] operand_1_in;
reg [DA... | 8.279935 |
module tb_alu_3 #(
parameter ACTION_LEN = 25,
parameter META_LEN = 256,
parameter COMP_LEN = 100
) ();
localparam STAGE = 0;
reg clk;
reg rst_n;
//the input data shall be metadata & com_ins
reg [META_LEN+COMP_LEN-1:0] comp_meta_data_in;
re... | 8.172113 |
module for the processor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ALU_microprocessor;
// Inputs
reg alu_clk;
reg [ 5:0] alu_ctrl ;
reg [31:0] in_1 ;
reg [31:0] in_... | 7.413583 |
module tb_alu_setc ();
// Inputs
reg clk;
reg reset;
reg [15:0] a;
reg [15:0] b;
reg [3:0] flags;
wire [15:0] c;
// Instantiate the Unit Under Test (UUT)
vmicro16_alu uut (
.op(`VMICRO16_ALU_SETC),
.a(a),
.b(b),
.flags(flags),
.c(c)
);
always #10 clk = ~clk;
//... | 7.892946 |
module: ALU_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ALU_toplevel;
// Inputs
reg [2:0] FS;
reg [15:0] A;
reg [15:0] B;
// Outputs
wire [15:0] out;
wire ze... | 8.602857 |
module tb_AM ();
//---------接口设置----------//
reg sclk;
reg rst_n;
wire signed [13:0] AM_mod;
//--------------------------//
initial sclk = 1;
always #5 sclk = ~sclk; //100M时钟
initial begin
rst_n = 0;
#500 rst_n = 1;
end
//--------------------------//
AM_create modulate_inst0 (
.cl... | 7.179422 |
module AndTestbench;
reg in1;
reg in2;
wire out;
And dut (
.out(out),
.in1(in1),
.in2(in2)
);
initial begin
$display("Teste 1: in1=0, in2=0");
in1 = 0;
in2 = 0;
#1 $display("Teste 2: in1=0, in2=1");
in1 = 0;
in2 = 1;
#1 $display("Teste 3: in1=1, in2=0");
... | 6.967934 |
module tb_and_gate;
reg a, b;
wire out;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
and_gate UUT (
.a (a),
.b (b),
.out(out)
);
initial // initial block executes only once
begin
// values for inputs
a = 0;
b = 0;
#p... | 7.252918 |
module tb_apple_out ();
`define simulation
//
// GMII Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
//
//TMDS clock 74.25MHz
//
reg tmds_clk;
initial tmds_clk = 1'b0;
always #13.468 tmds_clk = ~tmds_clk;
//
// Test Bench
//
reg sys_rst;
reg rx... | 7.463188 |
module tb ();
reg clk, reset;
wire [31:0] porta, portb;
AProp prop (
.clk_in (clk),
.reset_in(reset),
.port_a (porta)
); //, .port_b(portb));
//ACog cog0(.clk_in(clk), .reset_in(reset));
always #6.25 clk = ~clk;
initial begin
$dumpfile("aprop.vcd");
$dumpvars(0, tb);
... | 7.195167 |
module tb_aq_axi_ssm2603;
localparam CLK100M = 10000;
localparam CLK12M = 81380; // 12.288MHz
reg ARESETN, ACLK;
// Write Address Channel
wire [31:0] S_AXI_AWADDR;
wire [ 3:0] S_AXI_AWCACHE;
wire [ 2:0] S_AXI_AWPROT;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
// Write Data Channel
... | 6.61578 |
module tb_i2c_master;
// Inputs
reg rst_n;
reg clk;
reg [3:0] cmd_wr;
reg [31:0] cmd_din;
reg [9:0] adrs;
reg [3:0] wena;
reg [31:0] wdata;
reg isda;
// Outputs
wire [31:0] cmd_dout;
wire [31:0] rdata;
wire osda;
wire osck;
tri1 sda;
// Instantiate the Unit Under Test (UUT)
aq_i2c_m... | 7.069776 |
module tb_aq_sg;
reg RST_N1;
reg RST_N2;
reg CLK;
wire VSYNC;
wire HSYNC;
wire FSYNC;
wire ACTIVE;
reg ERROR;
aq_sg u_aq_sg (
.RST_N(RST_N2),
.CLK (CLK),
.VSYNC (VSYNC),
.HSYNC (HSYNC),
.FSYNC (FSYNC),
.ACTIVE(ACTIVE),
.DEBUG()
);
wire active_v... | 6.573099 |
module tb_arithmetic_circuits (); // Signed RCA
reg [3:0] x;
reg [3:0] y;
reg ci;
wire cout;
wire [3:0] s;
wire signed [4:0] carry_with_sum;
assign carry_with_sum = {cout, s};
SRCA UUT (
x,
y,
ci,
cout,
s
);
integer i, j;
initial begin
ci = 0;
for (i = -8; i... | 7.083368 |
module tb_arithmetic_circuits (); // UNTILL RCA ADDER + CLA
reg [3:0] x;
reg [3:0] y;
reg ci;
wire cout;
wire [3:0] s;
RCA UUT (
x,
y,
ci,
cout,
s
);
integer i;
initial begin
for (i = 0; i < 512; i = i + 1) begin
{x, y, ci} = i;
#20;
end
$finish;
... | 7.083368 |
module tb_arithmetic_circuits (); // - FOR PARAM RCA
parameter SIZE = 8;
reg [SIZE-1:0] x;
reg [SIZE-1:0] y;
reg cin;
wire cout;
wire [SIZE-1:0] s;
parametric_RCA UUT (
x,
y,
cin,
cout,
s
);
integer i;
initial begin
x = 199;
y = 121;
cin = 1;
#20 x ... | 7.083368 |
module tb_arithmetic_circuits(); -- UNTILL RCA ADDER
reg [3:0]x;
reg [3:0]y;
reg ci;
wire cout;
wire [3:0]s;
RCA UUT(x,y,ci,cout,s);
integer i;
initial
begin
for(i =0; i<512;i = i + 1) begin
{x,y,ci} = i;
#20;
end
$finish;
end
endmodule
| 7.083368 |
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