code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_ArtyA7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
/*
`ifdef MOD_OSRAM
force u_ArtyA7.u... | 6.574589 |
module tb_ascon_vanilla ();
reg [319:0] in;
wire [319:0] out;
reg clk;
reg reset, start_dut;
wire done;
localparam Tclk = 10;
localparam Tclkd = (Tclk / 2.0);
always @(*) #(Tclk / 2.0) clk <= ~clk;
Ascon_FSM #(d) dut (
start_dut,
clk,
reset,
in,
done,
out
);
... | 7.102892 |
module: asic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_asic;
// Inputs
reg clk;
reg rst;
// Outputs
wire [1:0] r;
wire [1:0] g;
wire [1:0] b;
wire bright;
wire cs... | 6.618777 |
module tb_async_micron_controller (
input clk50MHz,
output mwe_L,
output moe_L,
output madv_L,
output mclk,
output mub_L,
output mlb_L,
output mce_L,
output mcre,
input mwait,
output [22:0] maddr,
output [7:0] debug_out,
inout [15:0] mem_data,
input rx,
output... | 7.725085 |
module tb_asyn_bridge;
localparam ADDR_WD = 8, DATA_WD = 6, STRB_WD = 2, PROT_WD = 4;
reg a_pclk;
reg a_prst_n;
reg b_pclk;
reg b_prst_n;
reg a_psel;
reg a_penable;
reg a_pwrite;
re... | 6.989125 |
module tb;
parameter DEPTH = 16;
parameter WIDTH = 8;
parameter PTR_WDITH = 4;
parameter WR_DELAY = 13;
parameter RD_DELAY = 12;
parameter WR_TP = 15;
parameter RD_TP = 15;
reg wr_en_i, rd_en_i;
reg [WIDTH-1:0] wdata_i;
wire full_o;
wire [WIDTH-1:0] rdata_o;
wire empty_o;
reg wr_clk_i, rd_clk... | 6.612288 |
module tb_asyn_fifo_v2;
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 4 ;
reg reset_l;
reg wr_clk;
reg wr_en;
wire full;
reg [15:0] write_data;
reg ... | 6.997609 |
module tb_avg_inst (
output wire [63:0] avmm_0_rw_address, // avmm_0_rw.address
output wire [ 7:0] avmm_0_rw_byteenable, // .byteenable
output wire avmm_0_rw_read, // .read
input wire [63:0] avmm_0_rw_readdata, // .readdata
output wire avmm_0_... | 6.843297 |
module tb_axi ();
parameter DATA_WIDTH_SLAVE = 32;
parameter STROBE_WIDTH_SLAVE = DATA_WIDTH_SLAVE / 8;
parameter ADDRESS_WIDTH_SLAVE = 8;
parameter DATA_WIDTH_MASTER = 32;
parameter STROBE_WIDTH_MASTER = DATA_WIDTH_MASTER / 8;
parameter ADDRESS_WIDTH_MASTER = 8;
reg clk_tb;
reg rst_tb;
reg read_tb;... | 6.998862 |
module tb_axi4s_add_control_signal ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_axi4s_add_control_signal.vcd");
$dumpvars(0, tb_axi4s_add_control_signal);
#10000000;
$finish;
end
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
reg clk = 1'b1;
always #(RATE... | 7.743347 |
module tb_AXI4_Lite_Slave_FSM;
// Interface Signals
reg clk;
reg rst; // reset on high
// AXI4-Lite Interface Signals
// Read address channel
reg ARVALID;
wire ARREADY;
// Read data channel
wire RVALID;
reg RREADY;
// Write address channel
reg AWVALID;
wire AWREADY;
// Write data chan... | 6.611181 |
module tb_axil_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [31:0] M_AXI_AWADDR,
input [ 3:0] M_AXI_AWCACHE,
input [ 2:0] M_AXI_AWPROT,
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Dat... | 8.453533 |
module tb_axi_addr_range ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_axi_addr_range.vcd");
$dumpvars(0, tb_axi_addr_range);
#1000000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
parameter ... | 8.14275 |
module tb_axi_lite ();
reg M_AXI_ACLK;
reg M_AXI_ARESETN;
wire [31:0] M_AXI_AWADDR;
wire [ 2:0] M_AXI_AWPROT;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
// Master Interface Write Data
wire [31:0] M_AXI_WDATA;
wire [ 3:0] M_AXI_WSTRB;
wire M_AXI_WVALID;
wire ... | 6.690306 |
module tb_axi_ls_master_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] S_AXI_AWADDR,
output reg [ 3:0] S_AXI_AWCACHE,
output reg [ 2:0] S_AXI_AWPROT,
output reg S_AXI_AWVALID,
input S_AXI_AWREADY,
// Write Data C... | 7.834581 |
module tb_axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN, // Burst Length: 0-255
input [ 2:0] M_AXI_AWSIZE, // Burst Size: Fixed 2'b011
input ... | 7.908944 |
module axis_master_model (
input W_AXIS_TCLK,
output reg [63:0] W_AXIS_TDATA,
output reg W_AXIS_TVALID,
input W_AXIS_TREADY,
output reg [ 7:0] W_AXIS_TSTRB,
output reg W_AXIS_TKEEP,
output reg W_AXIS_TLAST
);
initial begin
W_AXIS_TDATA = 6... | 7.491749 |
module axis_slave_model (
input R_AXIS_TCLK,
input [63:0] R_AXIS_TDATA,
input R_AXIS_TVALID,
output reg R_AXIS_TREADY,
input [ 7:0] R_AXIS_TSTRB,
input R_AXIS_TKEEP,
input R_AXIS_TLAST
);
initial begin
R_AXIS_TREADY = 1'... | 7.490526 |
module tb_axi_ls_master_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Write Address Channel
output reg [31:0] S_AXI_AWADDR,
output reg [ 3:0] S_AXI_AWCACHE,
output reg [ 2:0] S_AXI_AWPROT,
output reg S_AXI_AWVALID,
input S_AXI_AWREADY,
// Write Data C... | 7.834581 |
module tb_axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN, // Burst Length: 0-255
input [ 2:0] M_AXI_AWSIZE, // Burst Size: Fixed 2'b011
input ... | 7.908944 |
module axis_master_model (
input W_AXIS_TCLK,
output reg [63:0] W_AXIS_TDATA,
output reg W_AXIS_TVALID,
input W_AXIS_TREADY,
output reg [ 7:0] W_AXIS_TSTRB,
output reg W_AXIS_TKEEP,
output reg W_AXIS_TLAST
);
initial begin
W_AXIS_TDATA = 6... | 7.491749 |
module axis_slave_model (
input R_AXIS_TCLK,
input [63:0] R_AXIS_TDATA,
input R_AXIS_TVALID,
output reg R_AXIS_TREADY,
input [ 7:0] R_AXIS_TSTRB,
input R_AXIS_TKEEP,
input R_AXIS_TLAST
);
initial begin
R_AXIS_TREADY = 1'... | 7.490526 |
module tb_axi_slave_model (
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [ 0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [ 7:0] M_AXI_AWLEN,
input [ 2:0] M_AXI_AWSIZE,
input [ 1:0] M_AXI_AWBURST,
input M_AXI_AW... | 7.908944 |
module tb_axi_vip ();
// SIZE value for WRITE/READ_BURST transaction
xil_axi_size_t mtestDataSize;
// Burst Type value for WRITE/READ_BURST transaction
xil_axi_burst_t mtestBurstType;
// LOCK value for WRITE/READ_BURST transaction
xil_axi_lock_t mtestL... | 7.92703 |
module tb_b213.v
Test bench for (2,1,3) backward label Viterbi Decoder.
===========================================================================*/
`timescale 1 ns/1 ns
module tb_b213;
`include "params_b213.inc.v"
reg [`n-1:0] Rx_data [0:22];
reg [`n-1:0] Rx;
reg seq_ready;
r... | 6.764531 |
module tb_barrel;
reg [15:0] op;
reg [ 3:0] shift_mag;
wire [15:0] result;
BarrelShifter shifter_instance (
op,
shift_mag,
result
);
initial begin
shift_mag = 4'b0001;
op = 16'b0000000000000001;
#10;
shift_mag = 4'b0101;
op = 16'b0000000000000101;
#10;
$sto... | 6.923881 |
module tb_barrel_shift_16bit;
reg [15:0] in;
reg [ 3:0] ctrl;
wire [15:0] out;
initial begin
$dumpfile("tb_barrel_shifter.vcd");
$dumpvars(0, tb_barrel_shift_16bit);
end
barrel_shift_16bit bs (
.in (in),
.ctrl(ctrl),
.out (out)
);
initial begin
in = 16'd16385;
ctr... | 8.352919 |
module tb_barrel_shift_16bit;
reg [15:0] in;
reg [ 3:0] ctrl;
wire [15:0] out;
initial begin
$dumpfile("tb_project.vcd");
$dumpvars(0, tb_barrel_shift_16bit);
end
barrel_shift_16bit bs (
.in (in),
.ctrl(ctrl),
.out (out)
);
initial begin
$display($time, " << Starting th... | 8.352919 |
module tb_basic ();
parameter CLOCK_FREQ = 100_000_000;
parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
// setup clock and reset
reg clk, rst;
initial clk = 'b0;
always #(CLOCK_PERIOD / 2) clk = ~clk;
z1top #(
.IMEM_HEX("firmware.hex")
) DUT (
.CLK100MHZ(clk),
.ck_rst(rst),
... | 7.381782 |
module tb_BasicHalfDuplexUart;
// Inputs
reg [7:0] txData;
reg [12:0] clocksPerBit;
reg stopBit2;
reg startTx;
reg ackFlags;
reg clk;
reg nReset;
// Outputs
wire [7:0] rxData;
wire overrunErrorFlag;
wire dataOutReadyFlag;
wire frameErrorFlag;
wire run;
wire rxStartBit;
wire txFull;
w... | 6.8835 |
module tb_basic_gates; // Defining a module
reg A, B; // Defining input ports
wire o_and, o_or, o_nand; // Defining output ports
wire o_nor, o_xor, o_xnor; // Defining output ports
basic_gates basic_gates (
A,
B
); // Calling the main function
initial begin
$dumpfile("basic_gates.v... | 6.908519 |
module tb_basis ();
genvar i;
generate
for (i = 2; i <= `MAX_M; i = i + 1) begin : FOO
tb_basis_m #(i) test ();
end
endgenerate
endmodule
| 7.49876 |
module tb_baudrate_gen ();
reg clk;
reg rst_n;
reg bps_tx_clk_en;
reg bps_rx_clk_en;
wire bps_tx_clk;
wire bps_rx_clk;
initial begin
clk = 0;
rst_n = 0;
bps_tx_clk_en = 0;
bps_rx_clk_en = 0;
#10 rst_n = 1;
bps_tx_clk_en = 1;
#900 bps_tx_clk_en = 0;
bps_rx_clk_en = 1;
... | 6.769593 |
module tb_baud_controller;
reg clk, reset;
reg [2:0] reg_baud_select;
wire sample_ENABLE;
initial begin
clk = 1'b1;
#200 reset = 1'b1;
#100 reset = 1'b0;
#1200 reset = 1'b1;
#100 reset = 1'b0;
reg_baud_select = 3'b111;
#5000 reg_baud_select = 3'b110;
#5000 reg_baud_select =... | 6.663799 |
module tb_bcdToGray_gate;
reg [3:0] In;
wire [3:0] Out;
bcdToGray_df mod (
Out,
In
);
initial begin
$monitor($time, " In=%4b, Out=%4b.", In, Out);
#0 In = 4'b0000;
repeat (9) #10 In = In + 4'b0001;
end
endmodule
| 6.927902 |
module tb_beep ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk; //时钟
reg sys_rst_n; //复位
//********... | 7.32315 |
module pass (
input grant_in,
output grant_out
);
assign grant_out = grant_in;
endmodule
| 9.16988 |
module block (
input grant_in,
output grant_out
);
assign grant_out = 0;
endmodule
| 8.703735 |
module tb_bip_calc_alone;
localparam LEN_CODED_BLOCK = 66;
reg tb_clock;
reg tb_reset;
reg tb_enable;
reg [LEN_CODED_BLOCK-1 : 0] tb_data;
initial begin
tb_clock = 0;
tb_reset = 1;
tb_enable = 0;
#6 tb_reset = 0;
tb_enable = 1;
#1000000 $finish;
end
always #1 tb_clock = ~tb_... | 6.758818 |
module tb_bit8_2to1mux;
wire [31:0] out;
reg [31:0] in1, in2;
reg sel;
bit32_2to1mux m1 (
out,
sel,
in1,
in2
);
initial $monitor($time, " in1=%b in2=%b sel=%b out=%b", in1, in2, sel, out);
initial begin
in1 = 32'b10101010_10101010_10101010_10101010;
in2 = 32'b01010101_01... | 6.834395 |
module tb_bit32_4to1mux;
wire [31:0] out;
reg [31:0] in1, in2, in3, in4;
reg [1:0] sel;
bit32_4to1mux m1 (
out,
in1,
in2,
in3,
in4,
sel
);
initial
$monitor($time, " in1=%h in2=%h in3=%h in4=%h sel=%b out=%h", in1, in2, in3, in4, sel, out);
initial begin
in1 = ... | 7.162276 |
module tb_bit32_reg;
reg [31:0] d;
reg clk, reset;
wire [31:0] q;
bit32_reg R (
q,
d,
clk,
reset
);
always @(clk) #5 clk <= ~clk;
initial begin
clk = 1'b1;
reset = 1'b0; //reset the register
#20 reset = 1'b1;
#20 d = 32'hAFAFAFAF;
#200 $finish;
end
ini... | 6.907715 |
module tb_bit8_2to1mux;
wire [7:0] out;
reg [7:0] in1, in2;
reg sel;
bit8_2to1mux m1 (
out,
sel,
in1,
in2
);
initial $monitor($time, " in1=%b in2=%b sel=%b out=%b", in1, in2, sel, out);
initial begin
in1 = 8'b10101010;
in2 = 8'b01010101;
sel = 1'b0;
#100 sel = 1'... | 6.834395 |
module TB_BitonicNetwork #(
parameter NUM = 16,
W = 16
);
// Inputs
reg [NUM*W-1:0] IN;
// Output
wire [NUM*W-1:0] OUT;
// Instantiate the Bitonic Network
BitonicNetwork #(NUM, W) BN (
.direction(1'b0),
.IN(IN),
.OUT(OUT)
);
// 500MHz frequency
//initial begin
// clk <=... | 6.589523 |
module tb_bitserial ();
reg [7:0] A, W;
reg clk, rstn, en;
reg [ 1:0] Precision;
wire [ 2:0] count;
wire [15:0] PRODUCT;
wire [19:0] ACCUM;
wire [15:4] PRODUCT4b = PRODUCT[15:4];
wire [19:4] ACC4b = ACCUM[19:4];
wire [15:6] PRODUCT2b = PRODUCT[15:6];
wire [19:6] ACC2b = ACCUM[19:6];
MAC_Unit MAC... | 6.6439 |
module tb_bit_encoder ();
localparam RATE = 1000.0 / 100.0;
initial begin
$dumpfile("tb_bit_encoder.vcd");
$dumpvars(1, tb_bit_encoder);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
parameter DATA_WIDTH... | 6.766054 |
module tb_blink ();
reg clk, reset;
reg en;
wire blink;
blink #(
.DVSR(5)
) tb_blink (
.clk(clk),
.reset(reset),
.en(en),
.blink(blink)
);
parameter T = 4;
always begin
clk = 1'b1;
#(T / 2);
clk = 1'b0;
#(T / 2);
end
initial begin
reset = 1'b1;
... | 6.517853 |
module tb_blocking ();
wire [1:0] out;
reg sys_clk;
reg sys_rst_n;
reg [1:0] in;
//初始化系统时钟、全局复位和输入信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
in <= 2'b0;
#20;
sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk =... | 7.795335 |
module tb_blocking_caveat;
// Inputs
reg a, b, c;
// Output
wire d;
// Instantiate the Unit Under Test (UUT)
blocking_caveat uut (
.a(a),
.b(b),
.c(c),
.d(d)
);
initial begin
$dumpfile("tb_blocking_caveat.vcd");
$dumpvars(0, tb_blocking_caveat);
// Initialize Inputs... | 6.934426 |
module tb_blocking_caveat_net;
// Inputs
reg a, b, c;
// Output
wire d;
// Instantiate the Unit Under Test (UUT)
blocking_caveat uut (
.a(a),
.b(b),
.c(c),
.d(d)
);
initial begin
$dumpfile("tb_blocking_caveat_net.vcd");
$dumpvars(0, tb_blocking_caveat_net);
// Initi... | 6.934426 |
module tb_block_value ();
reg sys_clock;
reg sys_rst_n;
reg [1:0] in;
wire [1:0] out;
initial begin
sys_clock <= 1'b1;
sys_rst_n <= 1'b0;
in <= 2'b0;
#20;
sys_rst_n <= 1'b1;
end
always #10 sys_clock = ~sys_clock;
always #20 in <= {$random} % 4;
block_value ... | 6.631346 |
module tb_BMPTST_3FRM ();
reg clk, rst;
wire VSYNC, HSYNC;
reg SYNC_HLD;
wire [31:0] READ_DATA;
reg FRM1, FRM2, FRM3;
parameter STEP = 10;
parameter DLY = 0.1;
COMM_VH #(
.FRM(3),
.H_WIDTH(2448),
.V_WIDTH(2048)
) COMM_VH (
.clk(clk),
.rst(rst),
.enable(~r... | 6.854431 |
module tb_booth8x8;
reg clk, start;
reg [7:0] a, b;
wire [15:0] ab;
wire busy;
booth_8x8 multiplier1 (
ab,
busy,
a,
b,
clk,
start
);
initial begin
clk = 0;
$display("first example: a = 3 b = 17");
a = 3;
b = 17;
start = 1;
#50 start = 0;
#80 ... | 6.591773 |
module vp_tty (
input PIN_nIN,
input PIN_nOUT,
input PIN_nSET,
output PIN_ERR,
output PIN_DONE,
output PIN_TR,
output PIN_nAO_A,
output PIN_nAC_A,
output PIN_nSC_S,
output PIN_nSO_S,
input PIN_nAC_S,
input PIN_nSC_A
);
wire nIN, nOUT, nSET;
reg ERR, DONE, TR;
... | 6.598851 |
module tb_bram;
parameter RAM_WIDTH = 32;
parameter RAM_ADDR_BITS = 9;
reg clk;
reg ram_enable;
reg write_enable;
reg [RAM_ADDR_BITS-1:0] address;
reg [ RAM_WIDTH-1:0] input_data;
wire [ RAM_WIDTH-1:0] output_data;
bram #(
... | 6.894833 |
module tb_breath_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led_out;
//reg define
reg sys_clk;
... | 6.872678 |
module : tb_BSRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Softwa... | 7.084562 |
module : tb_BSRAM_byte_en
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in th... | 7.336435 |
module bubble4_tb ();
// Signal Declarations
reg [3:0] in0, in1, in2, in3; // Inputs
wire [3:0] out0, out1, out2, out3; // Outputs
// Unit Under Test Instantiation
bubble4 UUT (
.in0 (in0),
.in1 (in1),
.in2 (in2),
.in3 (in3),
.out0(out0),
.out1(out1),
.out2(out2),... | 6.767651 |
module tb_bus;
reg clk, reset_n, tb_M0_req, tb_M1_req, tb_M0_wr, tb_M1_wr; // 6 reg
reg [7:0] tb_M0_address, tb_M1_address; // 8bits 2 reg
reg [31:0] tb_M0_dout, tb_M1_dout, tb_S0_dout, tb_S1_dout; // 32bits 4 reg
wire tb_M0_grant, tb_M1_grant, tb_S0_sel, tb_S1_sel, tb_S_wr; // 5 wire
wire [7:0] tb_S_ad... | 6.699324 |
module tb_busAddressTranslator ();
reg [31:0] virtual_addr;
wire [31:0] phys_addr;
wire [ 7:0] device_en;
BusAddressTranslator bat (
.virtual_addr(virtual_addr),
.phys_addr(phys_addr),
.device_en(device_en)
);
always begin
virtual_addr <= 32'h00000020;
#5 virtual_addr <= 32'h00... | 7.143223 |
module tb_busmux (
sel,
din,
dout
);
parameter BUS_COUNT = 2; // Number of input buses.
parameter MUX_WIDTH = 3; // Bit width of data buses.
parameter SEL_WIDTH = 1; // Width of select line.
input [SEL_WIDTH-1:0] sel; // Select signal.
input [MUX_WIDTH*BUS_COUNT-1:0] din; // Concatenated i... | 7.97646 |
module would be able to mux three 12-bit buses, or
// seven 5-bit buses, or any other combination,
// depending on the parameter values used when the
// module is instantiated.
//
*/
module tb_busmux_ohsel ( sel, din, dout );
parameter bus_count = 2; // numbe... | 8.634706 |
module tb_button_debounce;
parameter CLK_FREQ = 1_000;
parameter DEBOUNCE_HZ = 40;
reg clk;
reg rst_n;
reg btn_in;
wire btn_out;
button_debounce #(
.CLK_FREQ(CLK_FREQ),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
) _button_debounce (
.clk (clk),
.rst_n (rst_n),
.btn_in (btn_in),
... | 7.63017 |
module
`timescale 1ns/1ns
module tb_button_shaper();
reg clk,rst,Btt_in;
wire Btt_out;
button_shaper DUT_button_shaper_1(clk,rst,Btt_in,Btt_out);
initial begin
clk=0;
rst=1;
Btt_in=0;
end
always begin
#10 clk=1;
#10 clk=0;
end
initial begin
//Begins in Initial State
#15 Btt_in=1;//Pushes to the P... | 6.608387 |
module tb_bu_ndiag ();
reg [31:0] data_b_accum;
reg [31:0] dataa_mul;
reg clk, clk_en, aclr;
reg data_in_flag;
wire data_available;
wire zero, overflow, underflow;
wire [31:0] result;
localparam dly = 20000;
bu_ndiag a0 (
.data_available(data_available),
.zero(zero),
.overflow(over... | 6.520445 |
module tb_b_reg;
reg Rst;
reg Clk;
reg [5:0] b_sel;
reg LE_sel;
reg [7:0] Selector;
wire [7:0] Rx;
wire [7:0] Ry;
b_reg uut (
.Rst(Rst),
.Clk(Clk),
.b_sel(b_sel),
.LE_sel(LE_sel),
.Selector(Selector),
.Rx(Rx),
.Ry(Ry)
);
initial begin
Rst = 1;
Clk =... | 6.53187 |
module tb_cache_tag_full ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_cache_tag_full.vcd");
$dumpvars(0, tb_cache_tag_full);
#1000000;
$display("!!!!TIME OUT!!!!");
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE *... | 7.962894 |
module tb_capacity_async ();
localparam S_RATE = 1000.0 / 200.0;
// localparam M_RATE = 1000.0/150.1;
localparam M_RATE = 1000.0 / 1500.1;
initial begin
$dumpfile("tb_capacity_async.vcd");
$dumpvars(0, tb_capacity_async);
// #100000;
// $finish;
end
reg s_clk = 1'b1;
alwa... | 7.989831 |
module tb_capacity_buffer ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_capacity_buffer.vcd");
$dumpvars(0, tb_capacity_buffer);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset =... | 6.873313 |
module tb_capacity_size_limitter ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_capacity_size_limitter.vcd");
$dumpvars(0, tb_capacity_size_limitter);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial ... | 7.615417 |
module tb_capacity_timeout ();
localparam RATE = 1000.0 / 20.0;
initial begin
$dumpfile("tb_capacity_timeout.vcd");
$dumpvars(0, tb_capacity_timeout);
// #100000;
// $finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) rese... | 7.17141 |
module tb_cascade ();
localparam NUM = 4;
localparam DECIMAL_POINT = 14;
localparam WIDTH = 16;
reg clk;
reg rst;
reg [NUM*WIDTH-1:0] in_signal_pack;
reg [ WIDTH-1:0] in_signal [NUM-1:0];
integer i, j;
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
... | 6.736914 |
module tb_cast5_core ();
reg r_clk;
reg r_rst;
reg r_flag;
reg r_key_en;
reg [127:0] r_key;
reg r_din_en;
reg [ 63:0] r_din;
reg [ 31:0] r_err;
reg [ 2:0] r_count;
reg r_test;
wire s_dout_en;
wire [ 63:0] s_dout;
wire ... | 6.66467 |
module tb_decoder;
reg [31:0] inst;
reg inst_16;
reg clk;
wire arith;
wire dp;
wire sdibe;
wire llp;
wire lssd;
wire gpca;
wire gspa;
wire misc;
wire smr;
wire lmr;
wire cbsc;
wire ucb;
reg of;
integer file;
decoder top (
inst,
inst_16,
clk,
arith,
d... | 8.277876 |
module tb_catboard_blinky_host;
reg clock;
wire [7:0] led;
wire uart_tx;
reg uart_rx;
initial begin
$from_myhdl(clock, uart_rx);
$to_myhdl(led, uart_tx);
end
catboard_blinky_host dut (
clock,
led,
uart_tx,
uart_rx
);
endmodule
| 7.51189 |
module: CF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_CF;
// Inputs
reg [15:0] gyroData;
reg [15:0] y_accel_data;
reg [15:0] z_accel_data;
reg clk;
// Outputs
wire [... | 7.014675 |
module tb_cgmii;
//Registro
reg tb_clock;
reg tb_reset;
reg [3:0] tb_debug_pulse;
wire [7:0] tb_tx_ctrl;
wire [63:0] tb_tx_data;
initial begin
tb_clock = 1'b0;
tb_reset = 1'b0;
tb_debug_pulse = 4'b0000;
#1 tb_reset = 1'b1;
#1 tb_reset = 1'b0;
#10 tb_debug_pul... | 7.085932 |
module tb_cgmiiandenco;
parameter LEN_TX_CTRL = 8;
parameter LEN_TX_DATA = 64;
parameter LEN_CODED_BLOCK = 66;
reg tb_clock;
reg tb_reset;
reg tb_enable;
reg [ 9:0] counter;
reg [ 3:0] tb_debug_pulse... | 6.917279 |
module. This TB verifies
// that the chacha20 core can be used as specified in RFC 7539.
// Testvectors are taken from the RFC.
//
//
// Copyright (c) 2016, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the follow... | 6.733226 |
module tb_channel_management;
reg clk100;
wire [7:0] debug;
wire hpd;
wire auxch_in;
wire auxch_out;
wire auxch_tri;
// Datapath requirements
reg [2:0] stream_channel_count;
reg [2:0] source_channel_count;
// Datapath control
wire tx_clock_train;
wire ... | 6.597603 |
module tb_check_idle_resp (
// Inputs - System.
hclk_i,
hresetn_i,
// Inputs - AHB bus.
htrans_i,
hsel_i,
hready_i,
hrdata_bus_i,
hrdata_i
);
//----------------------------------------------------------------------
// MODULE PARAMETERS.
parameter NUM_SLVS = 0;
parameter RD... | 7.744873 |
module tb_Chi;
localparam DataLength = 20;
reg [1599:0] in_data;
reg [1599:0] out_ans;
wire [1599:0] out_data;
reg [1599:0] in_mem [0:DataLength-1];
reg [1599:0] golden_mem[0:DataLength-1];
integer i, err_num;
Chi chi0 (
.in (in_data),
.out(out_data)
);
initial $readmemh(`IN_... | 6.697827 |
module testRSS ();
//constants
parameter N = 16;
parameter len_data_test = 1000;
//set counter for FOR LOOP
integer count;
integer i;
integer cout_for_dec = 10;
integer f;
//memory for test
reg data_for_test[len_data_test-1:0];
// ====== ports initialization begin ====== //
reg clk, r... | 6.529798 |
module tb_cilantro_rv_top;
reg clk;
reg rst;
reg [31:0] instruction_in;
wire [31:0] data_out;
reg [32:0] memory[1023:0];
// Instantiate DUT here
cilantro_rv_top DUT (
.clk(clk),
.rst(rst),
.instr_in(instruction_in),
.data_out(data_out)
);
// Testbench clock generation (for e... | 6.578052 |
module tb_cisc ();
reg clk, reset, clkreset;
wire clk1, clk2;
wire [20:0] cword;
wire [7:0] ird, eab, edb, dout;
wire [2:0] ib, sb, state;
wire [7:0] di, t1, t2, b, pc, irf, ire, aluout, abus, bbus;
cisc CPU (
clk1,
clk2,
cword,
ird,
eab,
edb,
dout,
ib,
... | 7.458522 |
module tb_cla4;
reg [3:0] tb_a, tb_b; // 4bits 2 input
reg tb_ci; // 1bit 1 input
wire [3:0] tb_s; // 4bits output
wire tb_co; // 1bit output
wire [4:0] tb_result; // 5bits output
assign tb_result = {tb_co, tb_s};
cla4 U0_cla4 (
.a (tb_a),
.b (tb_b),
.ci(tb_ci),
.s (t... | 6.757753 |
module tb_clark_park_tr ();
initial $dumpvars(1, tb_clark_park_tr);
reg rstn = 1'b0;
reg clk = 1'b1;
always #(13563) clk = ~clk; // 36.864MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg en_theta = 0;
reg [11:0] theta = 0; // 当前电角度（简记为 ψ）。取值范围0~4095。0对应0°；10... | 6.933763 |
module tb_cla_clk;
reg clock; //input clock
reg [31:0] tb_a, tb_b; //32bits 2 input
reg tb_ci; //carry in
wire [31:0] tb_s_cla; //32bits sum(output)
wire tb_co_cla; //carry out
parameter STEP = 10; //define STEP=10ns
cla_clk U0_cla_clk (
.clock(clock),
.a(tb_a),
.b(tb_b),
... | 6.728434 |
module tb_clk ();
reg clk = 0;
reg reset = 1;
wire [15:0] out;
top top0 (
clk,
reset,
out
);
always #5 clk = ~clk;
initial begin
#5820000 reset = 0;
#112 reset = 1;
end
endmodule
| 7.317761 |
module wb_clkrst (
// Clk & Rst Interface
clk_o,
rst_o
);
//
// Clock and Reset Interface
//
output clk_o;
output rst_o;
//
// Internal registers
//
reg clk_o;
reg rst_o;
initial begin
clk_o = 0;
rst_o = 0;
#1;
rst_o = 1;
#`Trst;
rst_o = 0;
end
//
// C... | 7.197419 |
module tb_clk_div ();
reg clk_in;
reg rst_n;
wire clk_2;
wire clk_5;
ClkDiv #(
.DIV_NUM(2)
) clk2 (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk_2)
);
ClkDiv #(
.DIV_NUM(5)
) clk5 (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk_5)
);
initi... | 6.770648 |
module tb_clk_divider ();
reg clk;
reg rst;
wire clk2;
wire clk4;
wire clk8;
initial begin
clk = 1'b1;
rst = 1'b1;
#100 rst = 1'b0;
end
always #10 clk = ~clk;
clk_divider ins (
.clk (clk),
.rst (rst),
.clk2(clk2),
.clk4(clk4),
.clk8(clk8)
);
endmodule... | 6.740558 |
module tb_clk_gen (
clk
);
output clk;
reg clk;
integer period_hi;
integer period_lo;
reg en;
initial begin
period_hi = 20_000; // 20ns 25MHz
period_lo = 20_000; // 20ns
en = 1'b0;
clk = 1'b0;
end
always @(en) begin
while (en == 1'b1) begin
clk = ... | 6.651295 |
module tb_clk_pll ();
reg clk;
reg rst_n;
wire pll_clk;
wire locked;
clk_pll clk_pll_inst (
.areset(~rst_n),
.inclk0(clk),
.c0(pll_clk),
.locked(locked)
);
initial begin
clk = 1'b1;
rst_n = 1'b0;
#10 rst_n = 1'b1;
#5000 $finish;
end
always #1 clk = ~clk... | 7.050562 |
module: clocking
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_clock;
// Inputs
reg clk_50M;
reg rst_n;
reg clk_main_out;
reg clk_ddr_p;
reg clk_ddr_n;
// Outputs
wire... | 7.048701 |
module tb_clock1;
parameter TF = 2;
parameter TH = TF / 2;
wire clk1;
initial begin
$dumpfile("tb_clock1.vcd");
$dumpvars(0);
end
initial begin
$monitor("%0d\tclk1=", $time, clk1);
#10 $finish;
end
clock1 CLK1GEN (.clk1(clk1));
endmodule
| 6.524111 |
module: clocking
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_clocking;
// Inputs
reg clk_25M;
reg rst_n;
reg clk_main_out;
reg clk_ddr_p;
reg clk_ddr_n;
// Outputs
w... | 7.048701 |
module ******************* */
/* ********** 1) Main clock and test clock set to 50MHz ** */
/* ********** 2) Auto stop time is 10Us ** */
/* ********** ** */
/* ********** ... | 7.793578 |
module tb_clock_divider;
// Inputs
reg clock_in;
// Outputs
wire clock_out;
// Instantiate the Unit Under Test (UUT)
// Test the clock divider in Verilog
Clock_divider uut (
.clock_in (clock_in),
.clock_out(clock_out)
);
initial begin
// Initialize Inputs
clock_in = 0;
// crea... | 7.862983 |
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