code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_clock_generator (
input [7:1] i_clkdiv,
input [63:0] i_clkperiod
);
// ---------------- TBench signal --------------------------------
reg clk_tb = ~0; // start with falling edge
always @ (clk_tb)
begin
clk_tb <= #(`CLK_PERIOD/2) ~clk_tb;
end
... | 7.459005 |
module tb_clock_max (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
i... | 7.855653 |
module tb_clock_max_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_... | 8.417937 |
module tb_clock_min (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
i... | 7.912033 |
module tb_clock_minmax (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
... | 7.867852 |
module tb_clock_minmax_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] peri... | 7.867852 |
module tb_clock_min_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_... | 8.294223 |
module tb_clock_typ (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_bits;
i... | 7.543793 |
module tb_clock_typ_inverted (
tb_status,
CLK,
offset_bits,
period_bits,
duty_bits,
minLH_bits,
maxLH_bits,
minHL_bits,
maxHL_bits,
jRise_bits,
jFall_bits
);
parameter initialize = 0;
input [1:0] tb_status;
output CLK;
input [63:0] offset_bits;
input [63:0] period_... | 7.72527 |
module tb_clz32 ();
reg [31:0] d;
wire [ 4:0] clz;
pfpu_clz32 dut (
.d (d),
.clz(clz)
);
reg [5:0] i;
reg [7:0] j;
initial begin
$display("Testing clz32 module");
for (j = 0; j < 100; j = j + 1) begin
for (i = 0; i < 32; i = i + 1) begin
d = (32'h80000000 >> i);
... | 7.157389 |
module: cl_serial
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cl_serial;
// Inputs
reg cl_sertc_p;
reg cl_sertc_n;
reg clk_spi;
reg fifo_spi_wen;
reg [7:0] fifo_spi_din... | 7.064472 |
module TB_Cmd_Decode;
reg clk;
reg rst_n;
reg rx_done;
reg [7:0] uart_data;
wire wr_trig;
wire rd_trig;
wire wfifo_wr_en;
wire [7:0] wfifo_data;
Cmd_Decode Cmd_Decode_inst (
.clk (clk),
.rst_n (rst_n),
.rx_done (rx_done),
... | 6.751964 |
module tb_cmd_parser;
reg CLOCK50;
reg [3:0] KEY;
always #1 CLOCK50 <= ~CLOCK50;
//
// 例化top顶层模块
wire [19:0] SRAM_ADDR;
wire [15:0] SRAM_DQ;
wire SRAM_LB_N, SRAM_UB_N;
wire SRAM_WE_N, SRAM_OE_N;
wire SRAM_CE_N;
// top module
top top_inst (
.CLOCK_50(CLOCK50),
.KEY(KEY),
// sr... | 6.514063 |
module tb_cmos_inverter;
// Inputs
reg inv_in;
// Outputs
wire inv_out;
// Instantiate the Unit Under Test (UUT)
cmos_inverter uut (
.inv_in (inv_in),
.inv_out(inv_out)
);
initial begin
$dumpfile("tb_cmos_inverter.vcd");
$dumpvars(0, tb_cmos_inverter);
// Initialize Inputs
... | 7.184922 |
module tb_cmsdk_mcu;
//wires
wire NRST; // active low reset
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire XTAL2; // crystal pin 2
//instantiation
M0_Simulation uut1 (
.NRST(NRST),
.nTRST(nTRST),
.TDI(TDI),
.SWDIOTMS(SWDIOTMS),
.SWCLKTCK(SWCLKTCK),
.XTA... | 7.131043 |
module TB_CNN;
reg clk;
reg reset;
wire signed [39:0] CNN_output;
wire write_strobe;
CNN uut (
.clk(clk),
.reset(reset),
.CNN_output(CNN_output),
.write_strobe(write_strobe)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 0;
#50;
reset = 1;
#10;
... | 6.700888 |
module tb_cnn_avgp_3x3_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter KERNEL = 3; //3*3 Kernel
parameter R... | 6.986005 |
module tb_cnn_conv_1x1_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT = 64; //Height
parameter CHANNEL_NUM_IN = 64; //The number of c... | 7.255475 |
module tb_cnn_conv_3x3_64 ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter CHANNEL_NUM_IN = 64; //The number of channel in
... | 7.525571 |
module tb_cnn_conv_3x3_dilation_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter CHANNEL_NUM_IN = 64; //The nu... | 7.525571 |
module tb_cnn_conv_3x3_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 612; //Width
parameter IMAGE_HEIGHT = 612; //Height
parameter CHANNEL_NUM_IN = 1; //The number of ... | 7.525571 |
module tb_cnn_conv_7x7_64 ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter CHANNEL_NUM_IN = 4; //The number of channel in
... | 7.191386 |
module tb_cnn_conv_7x7_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 20; //Width
parameter IMAGE_HEIGHT = 20; //Height
parameter CHANNEL_NUM_IN = 3; //The number of ch... | 7.191386 |
module tb_cnn_maxp_3x3_multi_channel ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT = 16; //Height
parameter KERNEL = 3; //3*3 Kernel
parameter R... | 7.316838 |
module tb_cnn_maxp_3x3_top ();
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// General
parameter IMAGE_WIDTH = 1224; //Width
parameter IMAGE_HEIGHT = 1224; //Height
parameter CHANNEL_NUM = 1; //The number of channel
p... | 7.316838 |
module tb_cnt5;
reg tb_clk, tb_reset_n, tb_inc; // 3 regs
wire [2:0] tb_cnt; // 3bits wire tb_cnt
cnt5 U0_cnt (
.cnt(tb_cnt),
.clk(tb_clk),
.reset_n(tb_reset_n),
.inc(tb_inc)
); // instance by using cnt5
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; // every 5ns, i... | 6.540576 |
module tb_cntr8;
reg tb_clk, tb_reset_n, tb_inc, tb_load;
reg [7:0] tb_d_in;
wire [7:0] tb_d_out;
wire [2:0] tb_o_state;
cntr8 U0_cntr8 (
tb_clk,
tb_reset_n,
tb_inc,
tb_load,
tb_d_in,
tb_d_out,
tb_o_state
);
parameter STEP = 10;
// clock period=10ns
always... | 6.930155 |
module tb_cnt_updown ();
reg [1:0] up_down;
reg clk, reset;
wire [31:0] count;
updown_counter M1 (
count,
up_down,
clk,
reset
);
initial begin
#150 $finish;
end
initial begin
end
always begin
#5 clk = ~clk;
end
initial begin
$dumpfile("./updown_counter.du... | 6.777875 |
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
);
reg [31:0] test_id = 0;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
... | 6.668841 |
module tb_codec_top ();
wire slave_read; // Read request signal. Acvtive high.
wire slave_write; // Write request signal. Active high.
wire [2:0] slave_address; // Bus address.
wire [31:0] slave_readdata; // Read bus.
wire [31:0] slave_writedata; // Write bus.
wire slave_chipselect; // Chip select. R... | 7.888047 |
module TB_collision_instruction;
reg clk;
reg clk_en;
reg reset;
reg start;
reg [31:0] dataa;
reg [31:0] datab;
reg [2:0] n;
wire done;
wire [31:0] result;
CollisionInstruction #(46) U1 (
clk,
clk_en,
reset,
start, // Execution inputs
dataa,
datab, // Data inp... | 6.827139 |
module TB_collision_searcher;
reg clk;
reg reset;
reg start;
reg [4:0] target;
reg [511:0] message;
reg [31:0] counter;
wire [31:0] digests_computed;
wire done;
wire [31:0] result;
CollisionSearcher U1 (
clk,
reset,
start, // Execution inputs
target,
message,
... | 6.827139 |
module: colour_space_conversion
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_colour_space_conversion;
// Inputs
reg clk;
reg [8:0] r1_in;
reg [8:0] g1_in;
reg [8:0] b1_in... | 7.109511 |
module tb_columnmix ();
reg clk;
reg rst_n;
reg [127:0] data_in;
reg start_in;
reg en_de;
// internal wires
wire [127:0] data_out;
wire ready_out;
// dump variable
parameter DUMP_FILE = "tb.vcd";
initial begin
$display("Dump variables..");
$dumpvars("AC");
$dumpfile... | 6.832923 |
module tb_comb_str;
integer i;
reg A, B, C, D, sel;
wire y;
comb_str comb (
y,
sel,
A,
B,
C,
D
);
initial begin
for (i = 0; i <= 5'b11111; i = i + 1) begin
{A, B, C, D, sel} = i;
#5;
end
end
endmodule
| 6.58145 |
module tb_comp4bit_beh;
reg [3:0] A, B;
wire AgtB, AeqB, AltB;
comp4bit_beh compa (
A,
B,
AgtB,
AeqB,
AltB
);
initial $monitor($time, " A=%4b, B=%4b, AgtB=%b,AeqB=%b,AltB=%b ", A, B, AgtB, AeqB, AltB);
initial begin
#0 A = 4'b0000;
B = 4'b0000;
#10 A = 4'b1000;
... | 6.528606 |
module TB_Comparador_Mayor;
// Inputs
reg CLK;
reg [7:0] A;
reg [7:0] B;
//outputs
wire Out;
// Instantiate the Unit Under Test (UUT)
Comparador_Mayor uut (
.CLK(CLK),
.A (A),
.B (B),
.Out(Out)
);
initial begin
// Initialize Inputs
CLK = 0;
A = 8'b100... | 6.772632 |
module Tb_comparator;
reg [31:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9;
wire [0:3] highest;
comp_last_layer inst (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
in9,
highest
);
initial begin
in0 = 32'b010000110110110111111100101... | 6.574266 |
module tb_comparator3 ();
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
wire lt;
wire et;
wire gt;
comparator3 test_comparator3 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.et(et),
.gt(gt)
);
initial begin
//////////////////
A = ... | 6.843472 |
module tb_comparator8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire et;
wire gt;
comparator8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.et(et),
.gt(gt)
);
initial begin
// write your code here
... | 6.843472 |
module tb_comparator_3;
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
Comparator_3 test_comparator3 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
//////////////////
A = 3... | 6.843472 |
module tb_comparator_4bit ();
reg [3:0] a;
reg [3:0] b;
wire agtb, altb, aeqb;
comparator_4bit comp (
.agtb(agtb),
.altb(altb),
.aeqb(aeqb),
.a(a),
.b(b)
);
initial begin
$dumpfile("tb_comparator_4bit.vcd");
$dumpvars(0, tb_comparator_4bit);
end
initial begin
... | 6.843472 |
module tb_comparator_8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
Comparator_8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
//////////
A = 8'b0000... | 6.843472 |
module tb_compare;
reg clk = 1'b0;
initial begin
forever #10 clk = ~clk; // generate a clock
end
wire [ 2:0] stream_channel_count;
wire [72:0] data;
wire ready;
wire [ 2:0] v_stream_channel_count;
wire [72:0] v_data;
wire v_ready;
test_source i_test_source (
.clk ... | 6.626547 |
module tb_complex ();
reg clk = 1'b0;
reg [15:0] cnt = 16'b0000000000000000;
wire out;
initial begin
while (1) begin
#1;
clk = 1'b0;
#1;
clk = 1'b1;
end
end
always @(posedge clk) begin
cnt <= cnt + 1;
end
complex dut (
.x(cnt[7:0]),
.y(cnt[15:8]),
... | 6.883067 |
module tb_complexMUL ();
parameter p_inputWidth = 8;
parameter p_PointPosition = 3;
reg [p_inputWidth-1:0] inAr;
reg [p_inputWidth-1:0] inAi;
reg [p_inputWidth-1:0] inBr;
reg [p_inputWidth-1:0] inBi;
wire [2*p_inputWidth - p_PointPosition : 0] o_ResR;
wire [2*p_inputWidth - p_PointPosition : 0] o_ResI... | 7.001079 |
module tb_complex_fsm ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk;
reg sys_rst_n;
reg pi_money_... | 8.512986 |
module tb_complex_mult;
parameter N = 2;
// UUT Signals
reg clk;
reg ab_valid;
reg signed [N-1:0] ar, ai, br, bi;
wire p_valid;
wire signed [N+N:0] pr, pi;
// Simulation Variables
reg [4*N-1:0] i, j;
reg signed [N-1:0] exp_ar, exp_ai, exp_br, exp_bi;
reg signed [N+N:0] real_part_dsp, imag_... | 6.613969 |
module TB_COMPRESSOR;
localparam ENDCOUNT = 10000;
localparam NUM_PATTERNS = 8;
localparam LEN_ENCODE = $clog2(NUM_PATTERNS);
reg [ 255:0] data_i;
reg clk;
reg rst_n;
reg en_i;
wire [255 + LEN_ENCODE:0] data_o;
wire [ ... | 6.514525 |
module tb_comp_case;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
comp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_comp_case.vcd");
... | 7.045737 |
module tb_comp_case_net;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
comp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_comp_case_net.... | 7.35958 |
module tb_comp_video_timing ();
reg clk;
reg reset;
reg flybk;
reg csr;
wire csa;
always #`CLK_P clk <= ~clk;
////////////////////////////////////////////////////////////////////////////////
wire [7:0] pr;
wire [7:0] pg;
wire [7:0] pb;
wire hs, vs, de;
reg load_dma;
`define C_RES_X 11... | 7.103479 |
module tb_concat_module ();
parameter NB_ADDR = 26; // Jump addr in J type instructions
parameter NB_PC = 32;
parameter NB_UPPER_PC = 4; // Number of bits of upper PC+1
parameter NB_LOWER_BITS = 2;
// concat module
reg instruction[NB_PC-1:0]; // instruccion completa
// reg next_pc[NB_PC-1:0]... | 7.589526 |
module tb_control ();
reg Rst;
reg Clk;
reg [8:0] ms_m;
reg [7:0] DataOut_Bus;
reg [2:0] band;
wire [2:0] fun;
wire [5:0] b_sel;
wire LE_sel;
wire [1:0] outbus;
wire [2:0] c_sel;
wire [7:0] Address_Instruction_Bus;
control uut (
.Rst(Rst),
.Clk(Clk),
.ms_m(ms_m),
.DataOut... | 6.899995 |
module TB_controller_model;
// Inputs
reg sys_clk;
reg sys_reset;
reg [21:0] sys_addr;
reg [15:0] sys_data_to_sdram;
reg rw;
reg in_valid;
// Outputs
wire [15:0] sys_data_from_sdram;
wire sys_data_from_sdram_valid;
wire out_valid;
wire busy;
wire sdram_clk;
wire sdram_cke;
wire [11:0] s... | 6.524437 |
module TB_ControlPID;
// Inputs
reg [7:0] y_k_i;
reg clk_i;
reg dataf_i;
reg reset;
reg [7:0] coeff_1;
reg [7:0] coeff_2;
reg [7:0] coeff_3;
reg [7:0] ref_i;
// Outputs
wire dataf_oo;
wire [15:0] servo_o;
// Instantiate the Unit Under Test (UUT)
ControlPID uut (
.dataf_oo(dataf_oo),... | 6.661511 |
module ControlUnitTestbench;
reg [2:0] opcode;
wire PCWrite;
wire RegWrite;
wire isSend;
wire isBranch;
wire [1:0] ULAOp;
wire MemWrite;
wire MemRead;
wire RegMemWrite;
ControlUnit dut (
opcode,
PCWrite,
RegWrite,
isSend,
isBranch,
ULAOp,
MemWrite,
M... | 7.533746 |
module tb_converter;
reg tb_data_clk = 0;
reg tb_rst = 0;
//master
wire [ 15:0] tb_dmaster;
wire tb_vmaster;
reg tb_rmaster;
//slave
reg [127:0] tb_dslave;
reg tb_vslave;
wire tb_rslave;
reg tb_vslave_off;
reg tb_vslave_togg... | 8.179145 |
module tb_converters_cgrundey ();
reg enable;
reg ctr_enable;
reg ctr_clear;
reg conv_enable_n;
wire clk_out;
wire [5:0] counter_out, out184, out185;
clk M1 (
enable,
clk_out
);
counter6bit_cgrundey U1 (
clk_out,
ctr_clear,
ctr_enable,
counter_out
);
sn184_... | 6.503465 |
module tb_convert_fxp_float ();
initial $dumpvars(0, tb_convert_fxp_float);
localparam WII = 16;
localparam WIF = 16;
localparam WOI = 15;
localparam WOF = 18;
reg rstn = 1'b0;
reg clk = 1'b1;
always #(10000) clk = ~clk; // 50MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
... | 6.631833 |
module tb_Conv_Data_mover;
parameter integer MEM0_DEPTH = 896;
parameter integer MEM1_DEPTH = 896;
parameter integer MEM0_ADDR_WIDTH = 10;
parameter integer MEM1_ADDR_WIDTH = 10;
parameter integer MEM0_DATA_WIDTH = 128;
parameter integer MEM1_DATA_WIDTH = 128;
parameter integer PE_SIZE = 16;
parameter ... | 7.19881 |
module tb_conv_mask ();
localparam T = 20;
reg clk, rst_n, act;
reg [7:0] a, b;
wire [15:0] result;
wire [7:0] c_i;
integer i;
conv_mask result_1 (
clk,
rst_n,
act,
a,
b,
result,
c_i
);
always begin
clk = 1'b1;
#(T / 2);
clk = 1'b0;
#(T / 2);
... | 6.834287 |
module testbench_CORDIC_main;
parameter width = 16; //width of x and y
// Inputs
reg signed [width-1:0] x_start, y_start;
reg signed [31:0] angle;
reg clock;
//reg signed [63:0] i;
wire signed [width-1:0] cosine, sine;
parameter An = 32000;
// here, 32000 is the scaling factor
// 32,000 is mult... | 8.5053 |
module tb_CORDIC_combination_2bit_int_angle_16bit ();
localparam LEN = 16;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ----------------------------------------------------------------... | 7.190503 |
module tb_cordic_exponential_8bit ();
localparam SZ = 8;
reg [SZ-1:0] Xin, Yin;
reg [SZ-1:0] angle;
wire [SZ+1:0] exp;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------... | 8.389862 |
module tb_cordic_hyperbolic_8bit ();
localparam SZ = 8;
reg [SZ-1:0] Xin, Yin;
reg [SZ-1:0] angle;
wire [SZ:0] Xout, Yout;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// -------------------------------------------------------... | 8.356309 |
module tb_CORDIC_combination_16bit ();
localparam LEN = 16;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------ ... | 7.190503 |
module tb_CORDIC_combination_16bit_2bit_int_angle ();
localparam LEN = 16;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ----------------------------------------------------------------... | 7.190503 |
module tb_CORDIC_Hyperbolic_combination_32bit ();
localparam LEN = 32;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// --------------------------------------------------------------------... | 7.166328 |
module tb_CORDIC_sequential_32bit ();
localparam LEN = 32;
wire [LEN-1:0] cosh, sinh;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ------------------------------------------------------------------------------ ... | 6.75044 |
module: core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_core;
// Inputs
reg [31:0] io_IR;
reg [31:0] from_data_mem;
reg data_valid;
reg data_ready;
reg c... | 6.608059 |
module tb_core_mem (
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
output wire ack,
input wire [ 15 : 0] addr,
input wire [127 : 0] block_wr,
output wire [127 : 0] block_rd
);
localparam NUM_WORDS = 128;
localparam WAIT_CYCLES ... | 7.142714 |
module tb_core_pixel ();
wire [7:0] O_PIXEL_IN_ADDR0;
wire [7:0] O_PIXEL_IN_ADDR1;
wire [7:0] O_PIXEL_IN_ADDR2;
wire [7:0] O_PIXEL_IN_ADDR3;
wire [7:0] O_PIXEL_OUT_ADDRB;
wire [7:0] O_PIXEL_OUT_ADDRG;
wire [7:0] O_PIXEL_OUT_ADDRR;
wire [7:0] O_PIXEL_OUT_ADDR0;
wire [7:0] O_PIXEL_OUT_ADDR1;
wire [7... | 6.542703 |
module tb_count #(
parameter WIDTH = 4
) ();
reg clk;
reg rst;
reg en_i;
wire [WIDTH-1:0] count_o;
integer j;
count #(
.WIDTH(WIDTH)
) i_count (
.clk_i(clk),
.rst_i(rst),
.en_i(en_i),
.count_o(count_o)
);
initial begin
$dumpfile("tb_count.vcd");
// $... | 6.60798 |
module tb_counter;
reg clk, reset;
wire [3:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
counter UUT (
.clk(clk),
.reset(reset),
.q(q)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
... | 6.555401 |
module tb_counter4bit ();
wire [3:0] q;
reg clk, reset;
initial clk = 0;
always #2 clk = ~clk;
initial begin
$monitor("q = %b ", q, " clk = %b ", clk, " reset = %b ", reset);
end
counter4bit ctr (
q,
clk,
reset
);
initial begin
reset = 1'b1;
#4 reset = 1'b0;
// ... | 6.883755 |
module tb_counter6bit_cgrundey ();
reg clk_enable;
reg ctr_enable;
reg ctr_clr;
wire clk_out;
wire [5:0] count1;
wire [5:0] count2;
// Instantiate the clock generator with a period of 100 ns
clk #(100) clk1 (
clk_enable,
clk_out
);
// Intantiate two versions... | 6.986135 |
module tb_counter9b_updown;
reg clk, reset, dir;
wire [7:0] count;
counter8b_updown counter (
count,
clk,
reset,
dir
);
initial begin
clk <= 0;
reset <= 0;
dir <= 0;
#500 reset = 1;
#10 reset = 0;
#490 $stop;
end
always begin
#5 clk = ~clk;
end... | 6.83216 |
module TB_COUNTER_5B;
parameter P = 5;
// Inputs
reg CLK;
reg RST;
reg EN;
//outputs
wire [P-1:0] Y;
// Instantiate the Unit Under Test (UUT)
COUNTER_5B uut (
.CLK(CLK),
.RST(RST),
.EN (EN),
.Y (Y)
);
initial begin
// Initialize Inputs
CLK = 0;
RST = 0... | 6.549991 |
module tb_counter_60;
// counter_60 Parameters
parameter PERIOD = 10;
// counter_60 Inputs
reg rst_n = 0;
reg clk = 0;
reg load = 0;
reg set = 0;
reg [1:0] set_id = 0;
reg [3:0] set_num = 0;
reg signal = 0;
// counter_60 Outputs
wire [3:0] ones;
wire [2... | 7.632061 |
module tb_counter_async ();
localparam S_RATE = 1000.0 / 20.0;
localparam M_RATE = 1000.0 / 210.7;
initial begin
$dumpfile("tb_counter_async.vcd");
$dumpvars(0, tb_counter_async);
#100000;
$finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always ... | 7.737253 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module tb_counter_top ();
/* Size of ROM */
parameter ROM_WIDTH = 8;
parameter ROM_ADDR_BITS = 8;
/* ROM Ports */
reg CLK;
reg EN;
reg [ROM_ADDR_BITS-1:0] ADDR;
wire [ROM_WIDTH-1:0] DATA_OUT;
/* Counter_top Ports */
reg C_RST;
reg C_EN;
reg C_DIR;
wire [7:0] C_CNT;
integer i;
/* Instan... | 6.651759 |
module tb_count_slow;
reg clk, slowena, reset;
wire [3:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
count_slow UUT (
.clk(clk),
.reset(reset),
.slowena(slowena),
.q(q)
);
initial // Clock generation
begin
clk = 0;
f... | 6.750727 |
module tb;
// Do this in your test bench
initial begin
$dumpfile("test.vcd");
$dumpvars(0, tb);
end
parameter N = 8;
reg [N-1:0] a, b;
wire [N-1:0] s;
wire cout;
cla CarryLookahead (
a,
b,
s,
cout
);
initial begin
$monitor($time, "%d + %d = %d (+8*%d)", a, b,... | 6.961556 |
module: Decorder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cpath_decode;
// Inputs
reg clock;
reg reset;
reg [31:0] io_IR;
reg io_br_eq;
reg io_br_lt;
reg io_br_ltu;... | 6.64125 |
module async_ram (
input wire [15:0] a,
input wire we_n,
inout wire [7:0] d
);
reg [7:0] mem[0:65535];
assign d = (we_n) ? mem[a] : 8'hZZ;
always @* begin
if (we_n == 1'b0) mem[a] = d;
end
endmodule
| 7.601231 |
module: tv80n_wrapper
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cpu;
// Inputs
reg reset_n;
reg clk;
reg clk_enable;
reg wait_n;
reg int_n;
reg nmi_n;
reg busrq_n;
... | 6.539653 |
module tb_cpu0 ();
// cpu pin
reg clk;
reg rstn;
wire [7:0] err;
wire [31:0] i_addr;
wire [31:0] i_wdata;
reg [31:0] i_rdata;
wire i_en;
wire [3:0] i_we;
wire [31:0] d_addr;
wire [31:0] d_wdata;
reg [31:0] d_rdata;
wire d_en;
wire [3:0] d_we;
wire [3:0] f_ope_data;
wire [31:0] f_in1_d... | 6.626065 |
module tb;
// Do this in your test bench
initial begin
$dumpfile("test.vcd");
$dumpvars(0, tb);
end
parameter N = 100;
reg [N-1:0] a, b;
wire [N-1:0] s;
wire cout;
adder100 CarryLookahead (
a,
b,
1'b0,
cout,
s
);
initial begin
$monitor($time, "%d + %d =... | 6.961556 |
module tb ();
reg RST;
reg CLK;
reg [31:0] D_IN;
wire CRC_RDY;
wire [35:0] D_OUT;
integer fp;
integer i;
parameter DUTY = 2;
always #DUTY CLK = ~CLK;
initial begin
CLK = 1;
RST = 1;
#8 RST = 0;
end
initial begin
fp = $fopen("./crc.out", "w");
$fmonitor(fp, "At time", $time... | 7.002324 |
module tb_crc16 ();
reg clk_i;
reg rstn_i;
reg [7:0] byte_i;
reg etkin_i;
wire [15:0] crc16_o;
crc16 uut (
.clk_i (clk_i),
.rstn_i (rstn_i),
.byte_i (byte_i),
.etkin_i(etkin_i),
.crc16_o(crc16_o)
);
always begin
clk_i = 1'b0;
#5;
clk_i = 1'b1;
#5;
end
... | 6.842413 |
module tb_crc32;
reg clk;
reg nrst;
reg enable;
reg [7 : 0] data;
wire [31 : 0] crc_out;
crc32 DUT (
.nrst (nrst),
.clock (clk),
.enable(enable),
.din (data),
.crc_o(crc_out)
);
always begin
#2.5 clk = ~clk;
end
initial begin
fork
begin
#... | 6.713297 |
module tb_crc_comb ();
localparam FRAME_SIZE = 4;
localparam CRC_SIZE = 4;
localparam MASK = 4'b0000;
wire [ CRC_SIZE - 1 : 0] crc_comb_out [0 : FRAME_SIZE];
reg [FRAME_SIZE - 1 : 0] data_in;
reg [CRC_SIZE - 1 : 0] crc_init;
reg [CRC_SIZE - 1 : 0] crc_poly;
reg [CRC_SIZE - 2 : 0] crc_poly... | 7.449577 |
module tb_crc_parallel;
localparam CRC_SIZE = `CRC_SIZE;
localparam FRAME_SIZE = `FRAME_SIZE;
localparam CRC_INIT = 0;
localparam CODE_SIZE = FRAME_SIZE + CRC_SIZE;
localparam PATTERN_VECTOR_NUMBER = `PATTERN_VECTOR_NUMBER;
localparam PATTERN_POLYNOMIAL_NUMBER = `PATTERN_VECTOR_NUMBER;
localparam CODE_WOR... | 6.80547 |
module tb_crossbar #(
parameter STAGE = 0,
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter ACT_LEN = 25,
parameter width_2B = 16,
parameter width_4B = 32,
parameter width_6B = 48
) ();
reg clk;
reg rst_n;
//input from PHV
reg ... | 7.606265 |
module tb_csi_rx_lane_aligner;
reg clk;
reg [3:0] bytes_valid;
reg [63:0] bytes_i;
wire [63:0] bytes_o;
wire synced;
reg reset;
wire reset_g;
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
mipi_csi_rx_lane_aligner ins1 (
.clk_i(clk),
.reset_i(reset),
.bytes_valid_i(bytes... | 6.552817 |
module tb_csi_rx_lane_aligner_8b2lane;
reg clk;
reg [2:0] bytes_valid;
reg [15:0] bytes_i;
wire [15:0] bytes_o;
wire synced;
reg reset;
wire reset_g;
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
mipi_csi_rx_lane_aligner #(
.MIPI_GEAR (8),
.MIPI_LANES(2)
) ins1 (
.clk... | 6.552817 |
module tb_csi_rx_lane_phy;
reg RST_N;
reg CLK_P;
wire CLK_N;
reg CLK_DIV;
reg DIN_P;
wire DIN_N;
reg DOUT_CLK;
wire DOUT_VALID;
wire [7:0] DOUT;
initial begin
CLK_P = 0;
CLK_DIV = 0;
DOUT_CLK = 0;
RST_N = 0;
#100;
RST_N = 1;
end
always begin
#(2) CLK_P <= ~CL... | 6.552817 |
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