code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_csi_rx_word_align;
reg RST_N, CLK;
wire [7:0] DIN0, DIN1;
wire FSYNC;
wire VALID;
wire [31:0] DOUT;
always #(10) CLK = ~CLK;
initial begin
#0;
RST_N = 0;
CLK = 0;
#100;
RST_N = 1;
@(posedge CLK);
end
csi_rx_word_align u_csi_rx_word_align (
.RST_N(RST_... | 6.817039 |
module tb_csi_rx_word_align;
reg RST_N, CLK;
wire [7:0] DIN0, DIN1;
wire FSYNC;
wire VALID;
wire [31:0] DOUT;
wire DETECT;
wire FS;
wire FE;
wire [ 7:0] L0;
wire [ 7:0] L1;
wire [15:0] DET_D0;
wire [15:0] DET_D1;
wire [15:0] PIXEL_NUM;
wire [15:0] LIN... | 6.817039 |
module tb_csrbrg ();
reg sys_clk;
reg sys_rst;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [13:0] csr_a;
wire csr_we;
wire [31:0] csr_do;
reg [31:0] csr_di;
/* 100MHz system clock */
initial sys_clk = 1'b0... | 7.579757 |
module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_CT;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
reg down;
reg chip_se... | 8.169432 |
module tb_ctrl #(
parameter GUI_RUN = 0,
CLK_FREQ_MHZ = 200
) (
// Clock and reset outputs
output reg clk_x2,
output reg clk,
output reg clk_div2,
output reg rst_n,
output [31:0] count_vec,
input [31:0] timeout,
// Simulation status and control inputs
input ... | 8.371975 |
module tb_CTRL_ex_time;
parameter s_IDLE = 2'b00;
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
reg r_Exp_increase = 1'b0;
reg r_Exp_decrease = 1'b0;
reg r_Clock = 1'b0;
reg r_Reset = 1'b0;
reg [1:0] r_Main_FSM = s_IDLE;
wire [4:0] w_count_time;
//Instantiation of CTRL_ex_time, calle... | 6.562911 |
module tb_ctrl_fsm ();
parameter INSTR_WIDTH = 16;
parameter ADDR_WIDTH_OP = 4;
parameter ADDR_WIDTH_PC = 12;
parameter OPCODE_LGNT = 8;
parameter JMPR_OPCODE = 4;
parameter SEG_REG_WIDTH = 4;
reg clk_i;
reg a_reset_l;
reg [INSTR_WIDTH-1:0] out_data_pram_i; //output data from the PRAM
reg intr_h_... | 7.612174 |
module: cumsum
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_cumsum;
// Inputs
reg clk;
reg ce;
reg rst;
reg [13:0] in;
// Outputs
wire [22:0] out;... | 7.392478 |
module tb_dac_diff;
reg tb_data_clk = 0;
reg tb_rst = 0;
//slave
reg [1:0] tb_data;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
// util_adc_diff
util_dac_diff #(
.WORD_WIDTH(2),
.BYTE_WIDTH(16),
.ONEZERO_OUT(16'h7FFF),
.ZEROONE_OUT(16'h8000),
... | 8.17104 |
module tb_dac_switch;
reg tb_data_clk = 0;
reg tb_rst = 0;
//slave
reg tb_data;
localparam CLK_PERIOD = 500;
localparam RST_PERIOD = 1000;
// util_adc_diff
util_dac_switch #(
.BYTE_WIDTH(16)
) dut (
// diff input
.fifo_valid(tb_data),
.fifo_data("FIFO_DATA"),
.fifo_d... | 9.196998 |
module tb_daq #(
parameter NDAQ = 5
) (
input wire clk,
input wire [31:0] systime,
output wire eth_tx0,
output wire eth_tx1,
output wire eth_tx_en,
input wire eth_rx_clk,
input wire [31:0] daq_data[NDAQ],
input wire [NDAQ-1:0] daq_valid,
input wire [NDAQ-1:0] daq_end,
inpu... | 7.252753 |
module tb_dat #(
parameter DATA_WIDTH = 8
) ();
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data_i;
reg [`OP_WIDTH-1:0] ctr_aluop_i;
reg ctr_a_reg_en_i;
reg [`CTR_CARRYMUX_WIDTH-1:0] ctr_carrymux_i;
wire carry_o;
wire [DATA_WIDTH-1:0] data_o;
integer j;
dat #(
.DATA_WIDTH(DATA_WIDTH)
) ... | 7.067317 |
module tb_data32_to_data16 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire rec_en_out; //输出16位数据使能信号
wir... | 7.797857 |
module: dataControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_dataControl;
// Inputs
reg clk;
reg reset_n;
reg [455:0] wenmiao_rx_frame;
reg wenmiao_tx_busy;
reg wenm... | 6.805526 |
module DataMemoryTestbench;
reg clock;
reg [3:0] address;
reg [7:0] writeData;
wire [7:0] dataOut;
reg MemRead;
reg MemWrite;
DataMemory dut (
clock,
address,
writeData,
dataOut,
MemRead,
MemWrite
);
initial begin
clock = 0;
address = 0;
writeData =... | 6.894818 |
module tb_DATAPATH;
parameter n = 16, m = 16;
wire [n+m-1:0] tb_Product;
wire tb_done;
reg tb_clk, tb_rst, tb_start;
reg [15:0] tb_multiplicand, tb_multiplier;
DATAPATH DUT (
.Product(tb_Product),
.done(tb_done),
.clk(tb_clk),
.multiplicand(tb_multiplicand),
.multiplier(tb_mult... | 6.540094 |
module tb_data_async ();
localparam S_RATE = 1000.0 / 200.0;
localparam M_RATE = 1000.0 / 21.7;
initial begin
$dumpfile("tb_data_async.vcd");
$dumpvars(0, tb_data_async);
#100000;
$finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
always #(M_RATE ... | 7.930142 |
module tb_data_gen ();
reg sys_clk;
reg sys_rst_n;
wire [19:0] data;
wire [ 5:0] point;
wire sign;
wire seg_en;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
data_gen #(
.CNT_MAX (9),
... | 6.938083 |
module tb_data_mem;
// Inputs
reg clk;
reg rst;
reg wea;
reg web;
reg [`DATA_WIDTH*2-1:0] dina;
reg [`DATA_WIDTH*2-1:0] dinb;
reg wben;
reg rden;
reg inst_v;
reg [`INST_WIDTH-1:0] inst;
// Outputs
wire [`DATA_WIDTH*2-1:0] douta;
wire [`DATA_WIDTH*2-1:0] doutb;
// Instantiate the Unit U... | 6.649235 |
module tb_mem_data;
// Parameters
localparam MEMORY_WIDTH = 8;
localparam MEMORY_DEPTH = 128;
localparam NB_ADDR = 7;
localparam NB_DATA = 32;
localparam RAM_PERFORMANCE = "LOW_LATENCY";
localparam INIT_FILE = "";
// Ports
reg i_clock = 0;
reg i_mem_write_flag = 0;
reg i_mem_read_flag = 0;
reg... | 6.731737 |
module tb_data_multiplexer ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_multiplexer.vcd");
$dumpvars(0, tb_data_multiplexer);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 5;
parameter DATA_WIDTH = ... | 7.584495 |
module tb_data_packing ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_packing.vcd");
$dumpvars(0, tb_data_packing);
#100000 $finish();
end
parameter BUSY = 0;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg cke = ... | 7.120757 |
module tb_data_rd_ctrl ();
//********************************************************************//
//****************** Internal Signal and Defparam ********************//
//********************************************************************//
//wire define
wire rd_en; //数据读使能信号
wire [31:0] rd_ad... | 7.376374 |
module tb_data_serializer ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_serializer.vcd");
$dumpvars(0, tb_data_serializer);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 4;
parameter DATA_WIDTH = 4;
... | 7.052546 |
module tb_data_spliter ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_spliter.vcd");
$dumpvars(0, tb_data_spliter);
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
parameter NUM = 4;
parameter DATA_WIDTH = 32;
param... | 7.093038 |
module tb_data_split_pack ();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_data_split_pack.vcd");
$dumpvars(0, tb_data_split_pack);
#10000 $finish();
end
parameter RAND_BUSY = 1;
reg reset = 1'b1;
always #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;... | 7.093038 |
module tb_data_stream;
reg tx_symbol_clk;
reg tx_align_train;
reg tx_clock_train;
reg tx_link_established;
reg f;
wire [72:0] msa_merged_data;
wire test_signal_ready;
wire [ 2:0] stream_channel_count;
initial begin
tx_symbol_clk = 1'b0;
t... | 6.691095 |
module prescaler (
w_gated_sclk_reg,
out,
o_slave_select_OBUF,
clk,
CLK
);
output w_gated_sclk_reg;
output [0:0] out;
input o_slave_select_OBUF;
input clk;
input CLK;
wire CLK;
wire clk;
wire o_slave_select_OBUF;
wire [0:0] out;
wire [4:0] plusOp;
wire \w_counter_reg_n_0_[0] ;... | 7.858126 |
module Tb_Data_writer ();
reg clk, Rx_tick;
reg [7:0] Din;
wire fin, Wen;
wire [15:0] addr;
wire [ 7:0] Dout;
Data_Writer DStore (
.clk(clk),
.Din(Din),
.Rx_tick(Rx_tick),
.fin(fin),
.Wen(Wen),
.Addr(addr),
.Dout(Dout)
);
initial begin
clk = 1'b0;
fo... | 6.839678 |
module tb_DBU ();
localparam WIDTH = 32;
localparam CWKTIME = 10;
reg clk, rst, succ, step;
reg [2:0] sel;
reg m_rf, inc, dec;
wire [15:0] led;
wire [ 7:0] an;
wire [ 7:0] seg;
DBU #(WIDTH) dbu (
.clk (clk),
.rst (rst),
.succ(succ),
.step(step),
.sel (sel),
.m_rf... | 6.501632 |
module tb_DCPU16;
// Clock
reg clk;
// Active low reset
reg rst_n;
// RAM interface
wire [15:0] ram_addr;
wire [15:0] ram_dout;
// Instantiate DCPU-16
DCPU16 core0 (
.rst_n (rst_n),
.clk (clk),
.ram_addr (ram_addr),
.ram_dout (ram_dout)
);
// RAM
ram ram0 (
.ra... | 7.170894 |
module tb_dct_main #(
parameter DATA_WIDTH = 8, // pixel bit depth
parameter COEFF_WIDTH = 9,
parameter FIRST_STAGE_WIDTH = 21,
// parameter SECOND_STAGE_WIDTH = 33,
parameter SECOND_STAGE_WIDTH = 25,
parameter QUANT_STAGE_WIDTH = 14,
parameter RUNL_STAGE_WIDTH = 16
)... | 7.687836 |
module tb_dct_stage #(
parameter DATA_WIDTH = 8, // pixel bit depth
parameter OUTPUT_WIDTH = 12, // output coefficient width
parameter COEFF_WIDTH = 12 // coefficient bit width
) ();
// input signals
reg clk, data_vld, resetn;
reg [DATA_WIDTH-1 : 0] p0, p1;
// output signals
wire sync;
... | 6.85393 |
module tb_dds ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
//wire define
wire [7:0] data_out;
//reg define
reg sys_clk;
reg s... | 7.593829 |
module tb_dds_top;
parameter DATA_WIDTH = 12;
parameter ADDR_WIDTH = 12;
reg clk;
reg rst_n;
reg [ 11:0] phase_data;
reg [ 31:0] freq_data;
wire [DATA_WIDTH-1:0] dout;
initial begin
$dumpfile("tb_dds_top.dump");
//$dumpfile("addertb.vc... | 7.091297 |
module TB_debouncer ();
reg clk, reset;
wire [(`SWITCHES-1):0] swout;
reg [(`SWITCHES-1):0] swin;
debouncer #(
.DELAY(`DEBOUNCE_TIMEOUT)
) debouncer[`SWITCHES - 1 : 0] (
.clk(clk),
.rst(reset),
.in_switch(swin),
.out_switch(swout)
);
reg runt_check;
initial begin
$d... | 7.444772 |
module testbench;
reg [2:0] S;
reg reset;
wire [7:0] Q;
Dec Dec_1 (
S,
reset,
Q
);
initial begin
reset = 1'b1;
#10 reset = 1'b0;
#10 S = 3'b110; //6
#10 S = 3'b000; //0
#10 S = 3'b010; //2
#10 S = 3'b111; //7
#10 S = 3'b001; //1
#10 S = 3'b100; //4
... | 7.015571 |
module tb_decimal_splitter;
reg [6:0] dec;
wire [3:0] tens, units;
decimal_splitter tb_decimal_splitter__decimal_splitter (
.dec(dec),
.tens(tens),
.units(units)
);
initial begin
dec = 25;
#100 dec = 56;
#100 dec = 83;
end
endmodule
| 7.848117 |
module tb_decoder;
reg tb_data_clk = 0;
reg tb_rst = 0;
reg [175:0] tb_m_axis_tdata = 0;
reg tb_m_axis_tvalid = 0;
wire tb_m_axis_tready;
wire [ 15:0] tb_s_axis_tdata;
wire [ 7:0] tb_s_axis_tuser;
wire tb_s_axis_tvalid;
reg tb_s_axis_tready;
reg... | 8.277876 |
module tb_decoder2x4 ();
reg [1:0] in;
reg en;
wire [3:0] dout;
decoder2x4 test_decoder2x4 (
.in (in),
.en (en),
.dout(dout)
);
initial begin
en <= 1'b0;
in <= 2'b00;
#10;
in <= 2'b01;
#10;
in <= 2'b10;
#10;
in <= 2'b11;
#20;
en <= 1'b1;
... | 6.727177 |
module tb_Decoder3by8;
reg [2:0] tb_usr_input;
reg tb_ENABLE;
wire [7:0] tb_Dout;
reg [2:0] count = 3'd0;
//instantiate module
Decoder3by8 uut (
.usr_input(tb_usr_input),
.Dout(tb_Dout),
.ENABLE(tb_ENABLE)
);
initial begin
$display($time, " << starting simulation >> ");
tb... | 7.055777 |
module tb_decoder3to8_gate;
reg [2:0] in;
wire [7:0] out;
decoder3to8_gate dec (
out,
in[2],
in[1],
in[0]
);
initial $monitor($time, " in=%3b, out=%8b", in, out);
initial begin
#0 in = 3'b000;
repeat (7) #10 in = in + 3'b001;
end
endmodule
| 7.257758 |
module tb_decoder3_8 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire [7:0] out;
//reg define
reg in1... | 7.798816 |
module: Decoder4to16_less
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Decoder4to16_less;
// Inputs
reg [3:0] in;
// Outputs
wire [15:0] out;
// Instantiate the Unit Un... | 7.145307 |
module tb_decoder4x16;
wire [15:0] dout;
reg [3:0] in;
reg en;
decoder4x16 test_decoder4x16 (
.dout(dout),
.in (in),
.en (en)
);
initial begin
en <= 1'b0;
in <= 4'b0000;
#10;
in <= 4'b0001;
#10;
in <= 4'b0010;
#10;
in <= 4'b0011;
#20;
en <= ... | 6.821244 |
module tb_decoder_assgn ();
wire [15:0] decoder_out;
reg enable;
reg [3:0] binary_in;
decoder_assign uut (
decoder_out,
enable,
binary_in
);
initial begin
binary_in = 4'b0;
enable = 1'b0;
#10;
binary_in = 4'b1;
enable = 1'b1;
#10;
binary_in = 4'b0001;
enable... | 6.873406 |
module decoder_Nx2pN_top;
reg [2:0] IN;
wire [(2**3)-1:0] OUT;
integer i = 0;
decoder_Nx2pN #(
.N(3)
) decoder (
IN,
OUT
);
initial begin
for (i = 0; i <= 2 ** 3; i = i + 1) begin
$display("IN = %0d, OUT = %b", IN, OUT);
IN = i;
#1;
end
end
endmodule
| 7.875318 |
module tb_decode;
parameter PERIOD = 2;
parameter IMUL = 0;
parameter BARREL_SHIFTER = 1;
reg [31:0] instd = 32'h4200_1000;
reg clk = 0;
reg reset = 1;
wire reqe, rdye;
wire [ 3:0] aluop;
wire [ 4:0] shift;
wire [15:0] imm;
wire [ 3:0] rd;
wire [ 3:0] rm;
wire [ 3:0] rn;
wire [15:0] ctlsig... | 6.942186 |
module tb_decode_execute ();
localparam STEP = 10;
reg [31 : 0] ir;
reg [31 : 0] pc;
reg [31 : 0] rs1_data;
reg [31 : 0] rs2_data;
wire [4 : 0] rs1_num;
wire [4 : 0] rs2_num;
wire wb_reg;
wire [4 : 0] rd_num;
wire [31 : 0] rd_data;
wire [6 : 0] opcode;
wire [2 : 0] func3;
wire [31 : 0] i... | 6.544139 |
module TOP;
// Instruction Memory Interface Parameters
parameter IDATAW = 128;
parameter ISIZEW = 8;
parameter IADDRW = 32;
// Clock Interface
reg clk;
reg reset;
// Control Interface
reg flush;
reg handle_int;
wire halt;
//... | 6.594167 |
module TB_DECONCAT;
localparam ENDCOUNT = 10000;
localparam NUM_PATTERNS = 8;
localparam LEN_ENCODE = $clog2(NUM_PATTERNS);
reg [255+LEN_ENCODE:0] data_i;
reg clk, rst_n, en_i;
wire [255:0] scanned_o;
wire en_o;
DECONCAT #(
.NUM_PATTERNS(NUM_PATTERNS)
) DUT (
.data_i(data_i[255... | 6.746632 |
module tb_dec_counter;
reg clk, reset;
wire [3:0] count;
dec_counter counter (
count,
clk,
reset
);
initial begin
#0 clk = 0;
#0 reset = 0;
#75 reset = 1;
#5 reset = 0;
#1000 $stop;
end
always begin
#5 clk = ~clk;
end
endmodule
| 7.290193 |
module tb_DEC_INPUT_KEY;
reg input_key;
reg valid_cmd;
reg reset;
reg clk;
wire active;
wire mode;
DEC_INPUT_KEY DUT (
input_key,
valid_cmd,
reset,
clk,
active,
mode
);
initial begin
$dumpvars(0, tb_DEC_INPUT_KEY);
$dumpfile("my.vcd");
clk = 0;
... | 7.268056 |
module stimulate #(
parameter N = 1
) (
output clk,
output [N-1:0] out
);
reg clks = 1'b0;
reg [N-1:0] outs = 0;
initial begin
while (1) begin
#1;
clks <= 1'b0;
#1;
clks <= 1'b1;
end
end
always @(posedge clk) begin
outs <= outs + 1;
end
assign clk = clks... | 7.159411 |
module tb_delay ();
localparam N = 3;
localparam DELAY = 4;
wire clk;
wire [N-1:0] in;
wire [N-1:0] out;
stimulate #(
.N(N)
) stim_i (
.clk(clk),
.out(in)
);
delay_line #(
.N(N),
.DELAY(DELAY)
) dut (
.clk (clk),
.idata(in),
.odata(out)
);
endmod... | 6.930738 |
module tb_delay_fifo ();
parameter DELAY_CYCLES = 1;
parameter BITWIDTH = 32;
parameter ADDRWIDTH = 4;
parameter MEMHEIGHT = 2 ** ADDRWIDTH;
parameter INVALIDHEIGHT = MEMHEIGHT / 4;
parameter VALIDHEIGHT = MEMHEIGHT - INVALIDHEIGHT;
localparam input_file_path = {`path, "tb/data/delay_fifo_input.bin"};
... | 7.192433 |
module: delay_line
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_delay_line #(
parameter WIDTH = 8,
parameter DELAY = 4
);
wire c... | 7.993436 |
module: delta_picker
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_delta_picker;
// Inputs
reg clk;
reg rst;
reg [1:0] layer;
reg layer_valid;
reg [31:0] fetcher;
reg fe... | 6.63449 |
module tb_delta_sigma_adc;
// delta_sigma_adc Parameters
parameter PERIOD = 10;
parameter W = 16;
parameter N = 1024; //量化位数
// delta_sigma_adc Inputs
reg clk = 0;
reg rst_n = 0;
reg signed [W-1:0] din = -32768;
// delta_sigma_adc Outputs
wire dout;
... | 6.606775 |
module tb_demo #(
// parameters declared here.
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 12,
parameter C_BASEADDR = 32'h80000000,
// AXI Stream parameters
// Slave
parameter C_S_AXIS_DATA_WIDTH = 512,
parameter C_S_AXIS_TUSER_WIDTH = 128,
// Master
paramet... | 7.731347 |
module demux_1x2_top;
reg [3:0] in0;
reg sel;
wire [3:0] out0, out1;
integer i = 0;
demux_1x2 demux (
in0,
sel,
out0,
out1
);
initial begin
for (i = 0; i < 16; i = i + 1) begin
in0 = i + 1;
sel = i[0];
#1;
$display("in0 = %0d, sel = %0d, out0 = %0d, ... | 6.98808 |
module tb_demux_case;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_case uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5... | 7.797713 |
module tb_demux_case_net;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_case uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5... | 7.797713 |
module tb_demux_for;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_for uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (o5),... | 7.565734 |
module tb_demux_for_net;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_for uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
.o5 (... | 7.873836 |
module tb_demux_generate;
// Inputs
reg i;
reg [2:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire o7, o6, o5, o4, o3, o2, o1, o0;
// Instantiate the Unit Under Test (UUT)
demux_generate uut (
.sel(sel),
.o0 (o0),
.o1 (o1),
.o2 (o2),
.o3 (o3),
.o4 (o4),
... | 8.136728 |
module: deserializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_deserializer;
wire rxd;
wire rst;
wire clk;
wire [7:0] data;
wire ... | 7.284927 |
module tb_detect_errors;
parameter CYCLE = 16;
parameter whereis_aux = 0;
parameter packetsize = 33;
parameter segment_number_max = 16'd5;
reg rx_en = 0, clk = 0, rst = 0;
reg [7:0] rx_data = 0;
wire [31:0] count, ok, ng, lostnum;
wire valid;
wire [2:0] state;
reg [15:0] segment_number;
detec... | 7.67994 |
module tb_devboard;
parameter PERIOD = 2;
reg clk = 1;
reg reset = 1;
always #(PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_devboard.vcd");
$dumpvars(0, tb_devboard);
// Power on reset, no touchy >:[
#(PERIOD * 2) reset <= 0;
#(PERIOD * 200);
$finish;
end
wire ack, stb,... | 7.625449 |
module tb_dff8;
reg clk, reset, en;
reg [7:0] d;
wire [7:0] q;
dff8 tb_dff8 (
.clk(clk),
.reset(reset),
.en(en),
.d(d),
.q(q)
);
integer i;
initial begin
clk = 1'b0;
i = 0;
end // initial
always begin
#10 clk = ~clk;
end // always
always @(posed... | 6.799424 |
module tb_dff_asyncres;
// Inputs
reg clk, async_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_asyncres uut (
.clk(clk),
.async_reset(async_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_asyncres.vcd");
$dumpvars(0, tb_dff_asyncres);... | 7.388007 |
module tb_dff_asyncres_syncres;
// Inputs
reg clk, async_reset, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_asyncres_syncres uut (
.clk(clk),
.async_reset(async_reset),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile... | 7.388007 |
module tb_dff_async_reset;
// Inputs
reg clk, async_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_async_reset uut (
.clk(clk),
.async_reset(async_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_async_reset.vcd");
$dumpvars(0, tb_dff_a... | 6.904937 |
module tb_dff_async_set;
// Inputs
reg clk, async_set, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_async_set uut (
.clk(clk),
.async_set(async_set),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_async_set.vcd");
$dumpvars(0, tb_dff_async_set);
... | 6.904937 |
module tb_dff_clear;
reg d, clk, reset;
wire q;
dff_async_clear dff (
q,
d,
reset,
clk
);
always @(posedge clk) begin
$display($time, " d=%b, clk=%b, reset=%b, q=%b\n", d, clk, reset, q);
end
initial begin
forever begin
#0 clk = 0;
#5 clk = 1;
#5 clk = ... | 7.15127 |
module tb_dff_const1;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const1 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const1.vcd");
$dumpvars(0, tb_dff_const1);
// Initialize Inputs
clk = 0;
... | 6.820369 |
module tb_dff_const3;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const3 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const3.vcd");
$dumpvars(0, tb_dff_const3);
// Initialize Inputs
clk = 0;
... | 7.059134 |
module tb_dff_const4;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const4 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const4.vcd");
$dumpvars(0, tb_dff_const4);
// Initialize Inputs
clk = 0;
... | 6.877993 |
module tb_dff_const5;
// Inputs
reg clk, reset;
// Output
wire q;
// Instantiate the Unit Under Test (UUT)
dff_const5 uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_dff_const5.vcd");
$dumpvars(0, tb_dff_const5);
// Initialize Inputs
clk = 0;
... | 6.513805 |
module tb_dff_en; //enabled d flip flop test bench
reg tb_clk, tb_en, tb_d; // 3inputs
wire tb_q; // wire tb_q
_dff_en U0_dff_en (
.clk(tb_clk),
.en (tb_en),
.d (tb_d),
.q (tb_q)
); //instance by using _dff_en
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5; //eve... | 7.297135 |
module tb_dff_r; // testbench of Resettable D flipflop
reg tb_clk, tb_reset_n, tb_d; // 3 inputs
wire tb_q; // wire tb_q
_dff_r U0_dff (
.clk(tb_clk),
.reset_n(tb_reset_n),
.d(tb_d),
.q(tb_q)
); //instance by using _dff_r
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#... | 6.870625 |
module tb_dff_rs; //set, reset d flip flop test bench
reg tb_clk, tb_set_n, tb_reset_n, tb_d; // 4 inputs
wire tb_q; // wire tb_q
_dff_rs U0_dff_rs (
.clk(tb_clk),
.set_n(tb_set_n),
.reset_n(tb_reset_n),
.d(tb_d),
.q(tb_q)
); //instance by using _dff_rs
always begin
tb_... | 7.000466 |
module tb_dff_rs_sync_async; //sync async set,reset d flip flop test bench
reg tb_clk, tb_set_n, tb_reset_n, tb_d; // 4 inputs
wire tb_q_sync, tb_q_async; // use 2 wires
_dff_rs_sync_async U0_dff_rs_sync_async (
.clk(tb_clk),
.set_n(tb_set_n),
.reset_n(tb_reset_n), //instance by _dff_rs_syn... | 7.205853 |
module
`timescale 1ns/1ps
`include "./include/gscl45nm.v"
module tb_syn;
wire q;
reg d, clk;
dff d1 (clk, d, q);
always #5 clk = ~clk;
initial
begin
$monitor ("Time = %g d=%b, q=%b", $time, d, q);
clk = 0;
d = 0;
#6;
d = 1;
#3;
d = 0;
#14;
d = 1;
#14;
d = 0;
#18;
d = 1;
#6;
d = ... | 6.608387 |
module tb_dff_sync ();
reg clock, d, clear;
wire q;
dff_async_clear dff (
.q(q),
.d(d),
.clear(clear),
.clock(clock)
);
initial begin
$dumpfile("tb_dff.vcd");
$dumpvars;
end
initial clock = 1'b0;
always #5 clock = ~clock;
initial begin
d = 1'b0;
clear = 1... | 6.839537 |
module tb_dff_syncasync_reset;
// Inputs
reg clk, async_reset, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_syncasync_reset uut (
.clk(clk),
.async_reset(async_reset),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("... | 7.531848 |
module tb_dff_syncres;
// Inputs
reg clk, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_syncres uut (
.clk(clk),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_syncres.vcd");
$dumpvars(0, tb_dff_syncres);
//... | 7.198298 |
module tb_dff_sync_reset;
// Inputs
reg clk, sync_reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_sync_reset uut (
.clk(clk),
.sync_reset(sync_reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_dff_sync_reset.vcd");
$dumpvars(0, tb_dff_sync_re... | 7.368056 |
module tb_DFlipFlop;
//Inputs
reg d, clk;
//Output
wire q, q1;
integer i;
//Instancia a unidade a ser testada
DFlipFlop uut (
.d (d),
.clk(clk),
.q (q),
.q1 (q1)
);
//Pulso do clock
always begin
clk = 1'b0;
#10;
clk = 1'b1;
#10;
end
initial begin
... | 7.353168 |
module: Dflop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Dflop;
// Inputs
reg rst;
reg clk;
reg din;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test... | 7.468095 |
module
//-------------------------------------------------------------------
module tb_dft();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_clk; //... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_complex_abs();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <=... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_fifo();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_cl... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_postproc();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~t... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_preproc();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_sqrsum();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_sqrt();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <= ~tb_cl... | 8.13663 |
module
//-------------------------------------------------------------------
module tb_dft_twiddle_rom();
//-------------------------------------------------------------------
// Clock and reset
//-------------------------------------------------------------------
reg tb_clk = 0;
always
begin
#7.692;
tb_clk <=... | 8.13663 |
module tb_digitization;
reg clk;
reg [7:0] input_bit;
wire [7:0] freq;
digitization UUT (
.clk(clk),
.input_bit(input_bit),
.freq(freq)
);
initial begin
$display("******************************************************");
$display("BEGIN TESTBENCH");
$display("****************... | 6.693934 |
module tb_display_clock;
// display_clock Parameters
parameter PERIOD = 10;
// display_clock Inputs
reg load = 0;
reg set = 0;
reg [3:0] set_id = 0;
reg [3:0] set_num = 0;
reg [3:0] seconds_ones = 1;
reg [3:0] minutes_ones = 3;
reg [3:0] load_minutes_ones = 5;
reg [2:0] seco... | 7.856061 |
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