code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_distance_detection;
reg CLK, RST, front, rear;
reg [4:0] distance;
wire [4:0] front_distance, rear_distance;
distance_detection DUT (
.CLK(CLK),
.RST(RST),
.front(front),
.rear(rear),
.distance(distance),
.front_distance(front_distance),
.rear_distance(rear_... | 7.024912 |
module tb_divider_4over1;
reg enable, clk, reset_n, accept_in;
wire accept_out, ready_out;
//
reg [63:0] Q;
reg [15:0] M;
wire [63:0] quot;
divider_4over1 uut (
enable,
clk,
reset_n,
accept_in,
accept_out,
ready_out,
Q,
M,
quot
);
initial be... | 6.97433 |
module tb_divider_5 ();
reg sys_clk;
reg sys_rst_n;
wire clk_flag;
//初始化时钟 复位
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk <= ~sys_clk;
divider_5 divider_5_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.clk_flag... | 7.540646 |
module tb_divider_6 ();
reg sys_clk;
reg sys_rst_n;
wire clk_flag;
//初始化时钟 复位
initial begin
sys_clk = 1'b1;
sys_rst_n = 1'b0;
#20 sys_rst_n = 1'b1;
end
always #10 sys_clk <= ~sys_clk;
divider_6 divider_6_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.clk_flag... | 7.605545 |
module tb_divider_clock (
tb_status,
referenceCLK,
CLK,
pulseOffset,
pulseWidth,
divisor,
delay1_bits,
delay2_bits,
state1,
state2
);
parameter initialize = 0;
parameter initialReferenceClkState = 1;
input [1:0] tb_status;
input referenceCLK;
output CLK;
input [31:0]... | 7.188607 |
module tb_divider_five ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire clk_out;
//reg define
reg sys_clk;
... | 7.680233 |
module tb_divider_for_defog;
reg [7:0] t2;
reg [11:0] dividend;
reg clk;
reg nrst;
wire [7:0] quotient;
initial begin
nrst = 1'b0;
clk = 1'b0;
dividend = 12'd4095;
t2 = 8'd188;
#5 nrst = 1'b1;
#100 t2 = 8'd103;
#100 t2 = 8'd44;
end
always #5 clk = !clk;
divider_for_defog... | 6.676391 |
module tb_divider_six ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire clk_out;
//reg define
reg sys_clk;
... | 7.970112 |
module tb_divrem ();
reg clk, cpurst, diven_p;
initial begin
$fsdbDumpfile("divrem.fsdb");
$fsdbDumpvars;
//
clk = 1'b0;
diven_p = 1'b0;
cpurst = 1'b1;
#1000;
cpurst = 1'b0;
#1000;
@(posedge clk);
#1;
diven_p = 1'b1;
@(posedge clk);
#1;
diven_p = 1'b0;
... | 7.460354 |
module tb_div_89;
// div_89 Parameters
parameter PERIOD = 10;
// div_89 Inputs
reg clk = 0;
reg rst_n = 0;
reg MC = 0;
// div_89 Outputs
wire f45;
wire f89;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
div_89 u_div_89 (
... | 6.512217 |
module tb_div_by3 ();
reg clk_in;
reg reset_n;
wire clk_out;
div_by3 div_by3_i (
.clk_in (clk_in),
.reset_n(reset_n),
.clk_out(clk_out)
);
always begin
#5 clk_in = ~clk_in;
end
initial begin
clk_in = 1'b0;
reset_n = 1'b0;
#10;
reset_n = 1'b1;
#200000;
... | 6.612358 |
module tb_div_by_two ();
reg clk_in;
reg reset_n;
wire clk_out;
div_by_two div_by_two_i (
.clk_in (clk_in),
.reset_n(reset_n),
.clk_out(clk_out)
);
always begin
#10 clk_in = ~clk_in;
end
initial begin
clk_in = 1'b0;
reset_n = 1'b0;
#10;
reset_n = 1'b1;
#2... | 6.860617 |
module tb_dlatch; // TestBench of D-Latch
reg tb_clk, tb_d; // 2 inputs
wire tb_q, tb_q_bar; // use 2 wires
_dlatch U0_dlatch (
.clk(tb_clk),
.d(tb_d),
.q(tb_q),
.q_bar(tb_q_bar)
); //instance by using dlatch
always begin
tb_clk = 0;
#5;
tb_clk = 1;
#5;
end
i... | 7.181609 |
module dmaer (
input wire clk,
input wire rst_n,
input wire start,
input wire rnw_in,
output reg inprogress,
output reg req,
output reg rnw,
input wire ack,
input wire done
);
initial begin
inprogress = 1'b0;
req = 1'b0;
rnw = 1'b1;
end
alw... | 7.059175 |
module tb_dmac_1 (); //tb_dmac_1
reg Clk, reset_n;
reg M_grant;
reg [31:0] M_din, S_din;
reg S_sel, S_wr;
reg [7:0] S_address;
wire M_req, M_wr, Interrupt;
wire [31:0] M_dout, S_dout;
wire [7:0] M_address;
wire op_clear, op_start, op_done;
wire [2:0] op_mode;
wire wr_en, rd_en;
wire [3:0] dat... | 6.711455 |
module tb_dmac_2 (); //tb_dmac_2
reg Clk, reset_n;
reg M_grant;
reg [31:0] M_din, S_din;
reg S_sel, S_wr;
reg [7:0] S_address;
wire M_req, M_wr, Interrupt;
wire [31:0] M_dout, S_dout;
wire [7:0] M_address;
wire op_clear, op_start, op_done;
wire [2:0] op_mode;
wire wr_en, rd_en;
wire [3:0] dat... | 6.679944 |
module tb_dmac_3 (); //tb_dmac_3
reg Clk, reset_n;
reg M_grant;
reg [31:0] M_din, S_din;
reg S_sel, S_wr;
reg [7:0] S_address;
wire M_req, M_wr, Interrupt;
wire [31:0] M_dout, S_dout;
wire [7:0] M_address;
wire op_clear, op_start, op_done;
wire [2:0] op_mode;
wire wr_en, rd_en;
wire [3:0] dat... | 6.716693 |
module tb_DMAC_SLAVE;
reg clk, reset_n, opdone, s_sel, s_wr;
reg [15:0] s_addr;
reg [31:0] s_din;
wire [ 1:0] wr_en;
wire op_start, opdone_clear, s_interrupt;
wire [31:0] data_size;
wire [31:0] dest_addr, src_addr;
wire [ 1:0] opmode;
wire [31:0] s_dout;
DMAC_SLAVE U0_SLAVE (
clk,
re... | 6.815496 |
module tb_dmx ();
reg sys_clk;
reg sys_rst;
/* 83.333MHz system clock */
initial sys_clk = 1'b0;
always #6 sys_clk = ~sys_clk;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do_tx;
wire [31:0] csr_do_rx;
wire dmx_signal;
dmx_tx #(
.csr_addr(4'h0),
.clk_freq(833... | 7.504928 |
module tb_DPD ();
localparam M = 3;
localparam MEMORY_DEPTH = 32768; // 激励数据的深度
localparam DATA_WIDTH = 32; // 包含实部与虚部
localparam LUT_DEPTH = 4096;
reg JESD_clk = 0;
reg AXI_clk = 0;
reg reset = 0;
reg [... | 7.732496 |
module instantiation.
//
// Verilog Test Fixture created by ISE for module: DPSFnmCE
//
// Dependencies: None
//
// Revision:
//
// 0.01 07L22 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_DPSFmnCE_v;
// Inputs... | 6.950232 |
module tb_ds18b20 ();
//********************************************************************//
//******************** Parameter And Internal Signal *****************//
//********************************************************************//
//wire define
wire stcp;
wire shcp;
wire ds;
wire oe;
wire... | 8.094535 |
module tb_DS192_sel;
wire write_en;
reg clk;
reg rst_n;
reg [16:0] pixel_counter;
wire [15:0] BRAMDATA;
wire [23:0] RGB_sep, RGB_com;
wire [15:0] RGB;
bufferram bufferram_i (
.addra(pixel_counter),
.douta(BRAMDATA)
);
RGB_separate RGB_separate_module (
... | 6.60598 |
module tb_DS64_sel;
wire write_en;
reg clk;
reg rst_n;
reg [16:0] pixel_counter;
wire [15:0] BRAMDATA;
wire [23:0] RGB_sep, RGB_com;
wire [15:0] RGB;
bufferram bufferram_i (
.addra(pixel_counter),
.douta(BRAMDATA)
);
RGB_separate RGB_separate_module (
... | 6.660945 |
module tb_dsu_tx(clk, rst, TxD_start, TxD_data, TxD, TxD_busy);
input clk, rst, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter Baud = 115200;
//parameter Baud = 9600;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been trans... | 7.481741 |
module tb_dual_div;
// dual_div Parameters
parameter PERIOD = 10;
parameter P_WIDTH = 5;
parameter S_WIDTH = 3;
// dual_div Inputs
reg clk = 0;
reg rst_n = 0;
reg [S_WIDTH-1:0] Si = 0;
reg [P_WIDTH-1:0] Pi = 0;
// dual_div Outputs
wire Fdiv;
ini... | 7.047055 |
module : tb_dual_port_BRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in t... | 6.955551 |
module : tb_dual_port_RAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in th... | 6.955551 |
module tb_dut_uart_txrx;
parameter c_CLOCK_PERIOD_NS = 10;
//parameter c_CLKS_PER_BIT = 868;
//The parameter c_BIT_PERIOD = 8600;
//not required
//parameter c_BIT_PERIOD = 8600;
//Used to generate 100MHz clock
//using the parameter c_CLOCK_PERIOD_NS = 10;
reg r_Clock = 0;
//Signal to ... | 6.830521 |
module tb_dvi_demo ();
//
// System Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #4 sys_clk = ~sys_clk;
//
// Ethernet Clock 125MHz
//
reg phy_clk;
initial phy_clk = 1'b0;
always #4 phy_clk = ~phy_clk;
//
// TMDS CLOCK 74.2MHz
//
reg tmds_clk;
initial tmds_clk = 1'b... | 8.210692 |
module tb ();
reg clk, nreset;
always begin
#5 clk = !clk;
end
// Declare dynamic array
reg [7:0] mem[];
initial begin
#10;
// Allocate array for 4 locations
$display("Setting array size to 4");
mem = new[4];
$display("Initial the array with default values");
for (int i = 0; ... | 7.195167 |
module tb;
parameter BITS = 8;
reg clk, rst, valid, in;
reg [BITS-1 : 0] pattern;
wire out;
dyn_pattern_imp #(
.BITS(BITS)
) u0 (
.clk(clk),
.rst(rst),
.valid(valid),
.in(in),
.out(out),
.pattern(pattern)
);
always #1 clk = ~clk;
initial begin
clk = ... | 6.746419 |
module: D_FF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_D_FF;
// Inputs
reg arst;
reg clk;
reg en;
reg data;
// Outputs
wire out;
// Instantiate the Unit Under Tes... | 7.281187 |
module tb_e213.v
Test bench for (2,1,3) efficient backward label Viterbi Decoder.
John O'Shea, joshea@emc.com
===========================================================================*/
`timescale 1 ns/1 ns
module tb_e213;
`include "params_e213.inc.v"
reg [`n-1:0] Rx_data [0:22];
reg [`n-1:0] R... | 7.003508 |
module tb_edge_det;
reg clk, rst_n, data;
wire rise_edge;
wire fall_edge;
wire data_edge;
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
initial begin
repeat (100) begin
@(posedge clk) data = {$random};
end
$fin... | 6.661764 |
module tb_eeprom_byte_rd_wr ();
//wire define
wire scl;
wire sda;
wire stcp;
wire shcp;
wire ds;
wire oe;
//reg define
reg clk;
reg rst_n;
reg key_wr;
reg key_rd;
//时钟、复位信号
initial begin
clk = 1'b1;
rst_n <= 1'b0;
key_wr <= 1'b1;
key_rd <= 1'b1;
#200 rst_n <= 1'b1;... | 7.919131 |
module tb_efm;
// efm Parameters
parameter PERIOD = 10;
parameter WIDTH = 9;
// efm Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// efm Outputs
wire y_o;
wire [WIDTH-1:0] e_o;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
in... | 7.049262 |
module tb_EightxOneMux;
reg [2:0] Read;
reg [3:0] Din0, Din1, Din2, Din3, Din4, Din5, Din6, Din7; //4 registers of size 8 bits
wire [3:0] Output;
EightxOneMux show (
.Din0(Din0),
.Din1(Din1),
.Din2(Din2),
.Din3(Din3),
.Din4(Din4),
.Din5(Din5),
.Din6(Din6),
.Din... | 7.10896 |
module tb_elements; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quanti... | 8.15573 |
module tb_elevator;
reg clk;
reg reset;
reg en;
reg [3:0] F;
wire [3:0] D;
wire [3:0] Q;
wire A;
wire B;
wire A_latch;
wire B_latch;
wire [3:0] LED;
initial begin
$from_myhdl(clk, reset, en, F);
$to_myhdl(D, Q, A, B, A_latch, B_latch, LED);
end
elevator dut (
clk,
rese... | 7.448055 |
module: ENC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_ENC;
// Inputs
reg [31:0] D_IN;
reg [7:0] K_IN;
reg CLK;
// Outputs
wire [31:0] D_OUT;
// Instantiate the Uni... | 7.176694 |
module tb_Encoder8x3;
reg [7:0] data;
wire [2:0] code;
Encoder8x3 encoder8x3 (
.code(code),
.data(data)
);
initial begin
#0 data = 8'b0000_0001;
#5 data = 8'b0000_0010;
#5 data = 8'b0000_0100;
#5 data = 8'b0000_1000;
#5 data = 8'b0001_0000;
#5 data = 8'b0010_0000;
#5 d... | 6.757371 |
module tb_Encoders;
reg [15:0] in = 0;
reg [ 3:0] out4;
reg [ 2:0] out3;
reg [ 1:0] out2;
Encoder_16 enc (
in,
out4
);
Encoder_8 enc8 (
in[7:0],
out3
);
Encoder_4 enc4 (
in[3:0],
out2
);
initial begin
in = 16'b0000000000000000;
#20;
in = 16'b000000... | 6.841873 |
module encoder_2pNxN_top;
parameter N = 5;
reg [(2**N)-1:0] IN;
wire [N-1:0] OUT;
integer i = 0;
encoder_2pNxN #(
.N(N)
) encoder (
IN,
OUT
);
initial begin
for (i = 0; i < 2 ** N; i = i + 1) begin
IN = 1 << i;
#1;
$display("IN = %b, OUT = %0d", IN, OUT);
... | 6.936903 |
module tb_encoder_comparator;
parameter LEN_TX_CTRL = 8;
parameter LEN_TX_DATA = 64;
parameter LEN_CODED_BLOCK = 66;
reg tb_clock;
reg tb_reset;
reg tb_enable;
reg [ 9:0] counter;
reg [ LEN_TX_CTRL-1:0] tb_tx_c... | 6.520722 |
module tb_encoder_comparator ;
parameter LEN_TX_CTRL = 8 ;
parameter LEN_TX_DATA = 64 ;
parameter LEN_CODED_BLOCK = 66 ;
reg tb_clock ;
reg tb_reset ;
reg tb_enable ;
reg [9:0] counter ;
reg [LEN_TX_CTRL-1:0] tb_tx_ctrl ;
reg [LEN_TX_DATA-1:0] tb_tx_data ;
reg [LEN_CODED_BLOCK-1:0] ... | 6.520722 |
module tb_enhanced_prio ();
wire [3:0] fst, snd;
reg [9:0] r;
// Instantiation of enhanced_prio module
enhanced_prio UUT (
.fst(fst),
.snd(snd),
.r (r)
);
// Test vector generator
initial begin
// test vector 1
r <= 10'b0000000000;
#200;
// test vector 2
r <= 10'b000... | 6.993576 |
module TB_epb_wb_bridge ();
initial begin
$display("PASSED");
$finish;
end
endmodule
| 6.550148 |
module: error_propagator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_error_propagator_error;
parameter MATRIX_WIDTH = 4, // width of the weight matrix aka the numb... | 6.768408 |
module: tft_color
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_etc_lcd;
// Inputs
reg sclk;
reg srst;
// Outputs
wire hsync;
wire vsync;
wire [15:0] rgb;
wire tft_bl;
wire tf... | 8.17593 |
module tb_ethernet_udp_rmii ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg sys_clk; //PHY芯片接收数据时钟信号
reg... | 7.473692 |
module tb_Euclid_GCD #(
parameter W = 16
) ();
reg clk;
// Data signals
reg [W-1:0] operand_A;
reg [W-1:0] operand_B;
wire [W-1:0] result_data;
// Control signals
wire input_available;
reg reset;
wire result_taken;
wire result_rdy;
wire [1:0] state;
wire [1:0] nstate;
Euclid_GCD UUT (... | 6.938021 |
module tb_execute ();
localparam STEP = 10;
parameter NOP = 32'b00000000_00000000_00000000_00010011;
reg [31 : 0] pc;
reg [31 : 0] imm;
reg [`ALU_OP_WIDTH - 1 : 0] alu_op_sel;
reg [`SEL_SRC_A_WIDTH - 1 : 0] src_a_sel;
reg [`SEL_SRC_B_WIDTH - 1 : 0] src_b_sel;
reg [31 : 0] rs1_data;
reg [31 : 0] rs... | 6.655532 |
module : tb_execution_unit
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in t... | 8.059788 |
module : tb_execution_unit_multi_cycle
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to d... | 8.059788 |
module tb_exe_pulse_lighting ();
//ϵͳź
reg clk200M; //200Mʱ
reg rst_n; //λ͵ƽЧ
//
reg [ 7:0] mode; //ģʽ
reg [15:0] distance; //ֵ(m)
reg [31:0] phase_diff; //λƫ(5ns)
reg [31:0] expose_time; //̽عʱ
reg [15:0] laser_width; //
reg flag_en; //Ч־,ߵƽЧ
//ź
wire ... | 6.593836 |
module of testbench
`include "define_state.h"
module tb_experiment1;
logic Clock_50;
logic [17:0] Switches;
logic [3:0] Push_buttons;
logic [8:0] LED_Green;
wire [15:0] SRAM_data_io;
logic [15:0] SRAM_write_data, SRAM_read_data;
logic [19:0] SRAM_address;
logic SRAM_UB_N;
logic SRAM_LB_N;
logic SRAM_WE_N;
logic SRA... | 7.998111 |
module tb_experiment1a;
logic Clock_50;
logic [17:0] switch;
logic VGA_clock;
logic VGA_Hsync;
logic VGA_Vsync;
logic VGA_blank;
logic VGA_sync;
logic [7:0] VGA_red;
logic [7:0] VGA_green;
logic [7:0] VGA_blue;
// Instantiate the unit under test
experiment1a uut (
.CLOCK_50_I(Clock_50),... | 7.004582 |
module tb_experiment1b;
logic Clock_50;
logic [17:0] switch;
logic VGA_clock;
logic VGA_Hsync;
logic VGA_Vsync;
logic VGA_blank;
logic VGA_sync;
logic [7:0] VGA_red;
logic [7:0] VGA_green;
logic [7:0] VGA_blue;
// Instantiate the unit under test
experiment1b uut (
.CLOCK_50_I(Clock_50),... | 7.004582 |
module tb_experiment3a;
logic CLOCK;
logic RESETN;
experiment3a uut (
.CLOCK_I(CLOCK),
.RESETN_I(RESETN),
.BCD_COUNT_O()
);
initial begin
CLOCK = 1'b0;
RESETN = 1'b0;
#10 RESETN = 1'b1;
end
always begin
CLOCK = #5 ~CLOCK;
end
endmodule
| 7.004582 |
module tb_experiment3b;
logic CLOCK;
logic RESETN;
logic LOAD;
logic [3:0] LOAD_VALUE[1:0];
assign LOAD_VALUE = {4'h0, 4'h0};
experiment3b uut (
.CLOCK_I(CLOCK),
.RESETN_I(RESETN),
.LOAD_I(LOAD),
.LOAD_VALUE_I(LOAD_VALUE),
.BCD_COUNT_O()
);
initial begin
// Initiali... | 7.004582 |
module tb_experiment4;
logic Clock_50;
logic [17:0] Switches;
logic [8:0] LED_Green;
wire [15:0] SRAM_data_io;
logic [15:0] SRAM_write_data, SRAM_read_data;
logic [19:0] SRAM_address;
logic SRAM_UB_N;
logic SRAM_LB_N;
logic SRAM_WE_N;
logic SRAM_CE_N;
logic SRAM_OE_N;
logic SRAM_resetn;
//... | 7.004582 |
module tb_exploremips ();
reg clk;
reg rst;
wire [31:0] W_debug_wb_pc;
wire [ 3:0] W_debug_wb_rf_wen;
wire [ 4:0] W_debug_wb_rf_wnum;
wire [31:0] W_debug_wb_rf_wdata;
Top mips (
clk,
rst,
// debug
W_debug_wb_pc,
W_debug_wb_rf_wen,
W_debug_wb_rf_wnum,
... | 6.562994 |
module tb_exp_iteration_2bit_int_angle_16bit ();
localparam LEN = 16;
wire [LEN-1:0] exp;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ----------------------------------------------------------------------... | 7.424702 |
module TBExtendedTest ();
reg clk, rst;
MIPS cpu (
.clk(clk),
.rst(rst)
);
integer i = 0;
integer cnt = 0;
initial begin
$readmemh("C:/Users/24312/Desktop/tiny-CPU/dat/extendedtest.dat", cpu.im.instruction_memory);
end
initial clk = 0;
initial begin
rst = 0;
#5 rst = 1;
... | 7.023844 |
module tb_ext_crc;
reg rx_clk, rx_enable;
reg [7:0] rx_data;
wire [7:0] rawdata;
wire raw_en;
ext_crc uut (
.rx_clk(rx_clk),
.rx_data(rx_data),
.rx_enable(rx_enable),
.sfd_wait(1'b0), // 0
.rawdata(rawdata),
.raw_en (raw_en)
);
localparam CYCLE = 16;
localpara... | 7.050573 |
module tb_ex_cnt ();
reg tb_sclk, tb_rst_n;
wire [9:0] tb_cnt;
initial begin
tb_sclk <= 1'b0;
tb_rst_n <= 1'b0;
#200.1
tb_rst_n <= 1'b1;
end
always #10 tb_sclk <= ~tb_sclk;
ex_cnt ex_cnt_inst (
.sclk (tb_sclk),
.rst_n(tb_rst_n),
.cnt (tb_cnt)
);
endmodule
| 6.679251 |
module tb_ex_ipcore ();
reg tb_clk;
wire tb_oclk1;
wire tb_oclk2;
wire tb_locked;
wire [1:0] tb_cnt;
wire [7:0] tb_odata;
initial begin
tb_clk <= 1'b0;
end
always #10 tb_clk = ~tb_clk;
ex_ipcore ex_ipcore_instance (
.clk(tb_clk),
.oclk1(tb_oclk1),
.oclk2(tb_oclk2),
... | 6.548534 |
module tb_ex_shift_reg ();
reg tb_lvds_clk;
reg tb_rst_n;
reg tb_lvds_d;
wire [7:0] tb_o_lvds_d;
reg [3:0] i_30;
reg [0:0] mem1x16[15:0];
initial begin
tb_lvds_clk <= 1'b0;
tb_rst_n <= 1'b0;
tb_lvds_d <= 1'b0;
#90.1
tb_rst_n <= 1'b1;
end
always #10 tb_lvds_clk <= ~tb_lvds_cl... | 6.506087 |
module tb_ex_spi ();
reg tb_sclk;
reg tb_rst_n;
reg tb_work_en;
reg tb_spi_sdo;
wire tb_spi_clk;
wire tb_spi_sdi;
wire tb_spi_csn;
wire tb_conf_end;
reg [15:0] send_mem[31:0];
reg [15:0] shift_buf;
initial begin
tb_sclk <= 1'b0;
tb_rst_n <= 1'b0;
#100;
tb_rst_n <= 1'b1;
end... | 7.056943 |
module tb_fa ();
reg a;
reg b;
reg cin;
wire sum;
wire cout;
full_adder UUT (
.a (a),
.b (b),
.cin (cin),
.sum (sum),
.cout(cout)
);
initial begin
#10 a = 0;
b = 0;
cin = 0;
#10 a = 0;
b = 1;
#10 a = 1;
b = 0;
#10 a = 1;
b... | 6.785935 |
module tb_fadder_1bit ();
wire sum, cout;
reg a, b, cin;
fadder_1bit fadd (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
a = 0;
b = 0;
cin = 0;
#5 a = 0;
b = 0;
cin = 1;
#5 a = 0;
b = 1;
cin = 0;
#5 a = 0;
... | 6.554951 |
module tb_fadder_4bit ();
wire [3:0] sum;
wire cout;
reg [3:0] a, b;
reg cin;
fadder_4bit faddr (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
$dumpfile("tb_fadder_4bit.vcd");
$dumpvars;
end
initial begin
a = 4'b0101;
b = 4'b100... | 6.593624 |
module tb_fadder_dec ();
reg a, b, cin;
wire sum, cout;
fadder_dec addr (
.cout(cout),
.sum(sum),
.cin(cin),
.a(a),
.b(b)
);
initial begin
$dumpfile("tb_fadder_dec.vcd");
$dumpvars;
end
initial $monitor(" a = %b, b = %b, cin = %b, sum = %b, cout = %b", a, b, cin, ... | 7.094135 |
module: FanSpeed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FanSpeed;
// Inputs
reg arst;
reg clk;
reg [7:0] speed;
// Outputs
wire pwm_data;
// Instantiate the Uni... | 8.365707 |
module TB_fan_controller ();
reg clk;
reg rst;
wire f0, f1, f2;
fan_controller fan_controller_inst (
.wb_clk_i(clk),
.wb_rst_i(rst),
.fan_control({f2, f1, f0})
);
initial begin
$dumpvars;
clk <= 1'b0;
rst <= 1'b1;
#40 rst <= 1'b0;
#400000 $display("PASSED");
$fini... | 6.620747 |
module tb_Fast_median_filter;
reg sclk;
reg s_rst_n;
reg in_line_vaild;
reg [7:0] din;
wire dout_flag;
wire [7:0] median;
reg [7:0] mem_a[130559:0]; //480*272=130560-----13bit
//------------- generate system signals ------------------------------------
initial begin
sclk = 1;
s_rst_n <= 0;... | 7.20021 |
module fa_Nb_top;
parameter W = 2;
reg [W-1:0] IN0, IN1;
reg CIN;
wire [W-1:0] SUM;
wire CO;
fa_Nb #(
.WIDTH(W)
) fa (
.CARRY_IN(CIN),
.IN0(IN0),
.IN1(IN1),
.SUM(SUM),
.CARRY_OUT(CO)
);
integer i = 0;
initial begin
for (i = 0; i <= 2 ** (2 * W + 1); i = i... | 7.030295 |
module fdc(
output PIN_nSHIFT, // serial clock
output PIN_nOUT,
output PIN_nDI,
input PIN_nDO,
input PIN_nRUN,
input PIN_nSET,
output PIN_nERR,
output PIN_nDONE,
output PIN_nTR
);
reg CLK;
reg nSH;
reg nOUT;
reg nDI;
wire nDO;
wire nRUN;
wire nSET;
reg ... | 6.757907 |
module tb_fdiv;
reg clk0;
wire clk1;
wire clk2;
parameter Tburst = 100000000, Ton = 1, Toff = 1;
fdiv fd (
clk0,
clk1,
clk2
);
initial begin
repeat (Tburst) begin
#Toff clk0 = 1'b1;
#Ton clk0 = 1'b0;
end
end
endmodule
| 6.617482 |
module tb_fetch ();
localparam STEP = 10;
reg clk;
reg rst;
reg [31 : 0] pc;
reg stall;
reg [31 : 0] rs1;
reg [31 : 0] imm;
reg [31 : 0] pc_sel;
reg taken;
wire [31 : 0] ir_code;
wire [31 : 0] next_pc;
fetch fetch (
.clk(clk),
.rst(rst),
.pc(pc),
.stall(stall),
... | 7.007226 |
module : tb_fetch_issue
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the ... | 8.699001 |
module : tb_fetch_issue_intr
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in... | 8.699001 |
module : tb_fetch_receive
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in th... | 8.854399 |
module TOP;
// Instruction Memory Interface Parameters
parameter IDATAW = 128;
parameter ISIZEW = 8;
parameter IADDRW = 32;
reg clk;
reg reset;
// Control Interface
reg flush;
reg [IADDRW-1:0] load_address;
reg load;
// Code Segment
reg... | 6.594167 |
module tb_ffcore ();
parameter NATIVE_ADDR_WDITH = 3;
parameter NATIVE_DATA_WIDTH = 32;
parameter M = 32'd100;
FF_Test_Core #(
.NATIVE_ADDR_WDITH(NATIVE_ADDR_WDITH),
.NATIVE_DATA_WIDTH(NATIVE_DATA_WIDTH),
.M(M)
) inst_FF_Test_Core (
.REFCLK (REFCLK),
.NATIVE_CLK (NATI... | 7.398432 |
module tb_fft ();
reg SCLK;
reg signed [13:0] data_out;
//------------------------------------//
wire signed [13:0] data_out_re;
wire signed [13:0] data_out_im;
//--------------时钟部分----------------//
initial SCLK = 0;
always #10 SCLK = ~SCLK;
//-------------------------------------//
... | 6.502988 |
module tb_fft_2 ();
reg clk; //50mhz
reg rst; //复位
reg [31:0]s_axis_data_tdata;//fft 输入的处理数据,低16位为实部信号，高16位虚部信号，本次matlab才生的信号都是失信号
reg [31:0] data[511:0]; ////数组，将FPGA读取的信号数据寄存在数组中
wire s_axis_config_tready; //fft core 准备好接收配置信号
wire s_axis_data_tready; //fft core 准备好接收处理数据信号
wire [31:0] xk_re; /... | 6.936962 |
module tb_fft_3 ();
//------------------------------//
reg sclk;
reg [31:0] s_axis_data_tdata;
reg [31:0] data [1023:0];
wire s_axis_config_tready;
wire s_axis_data_tready;
wire [31:0] data_re;
wire [31:0] data_im;
wire m_axis_data_tvalid;
wire [15:0]... | 7.483662 |
module tb_FFT_FSM;
reg i_clk;
reg i_rst;
reg i_en;
reg i_new_data;
reg [15:0] i_data;
wire [31:0] o_dout;
wire o_active_write;
wire [7:0] o_addr;
FFT_FSM dut (
i_clk,
i_rst,
i_en,
i_new_data,
i_data,
o_dout,
o_active_write,
o_addr
);
initial begin... | 6.748723 |
module TB_Fibonacci ();
parameter clock_time = 1000000;
reg next;
reg reset;
wire [6:0] disp1;
wire [6:0] disp2;
wire [6:0] disp3;
wire [6:0] disp4;
Fibonacci fib (
.next (next),
.reset(reset),
.disp1(disp1),
.disp2(disp2),
.disp3(disp3),
.disp4(disp4)
);
initi... | 6.692512 |
module: fifo36_to_ll8
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo36_to_ll8;
// Inputs
reg clk;
reg reset;
reg clear;
reg [35:0] f36_data;
reg f36_src_rdy_i;
reg l... | 6.518526 |
module tb_fifo72togmii ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk... | 7.037264 |
module tb_fifo9togmii ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk ... | 7.116518 |
module tb_fifos_interface ();
parameter FIFO_DEPTH = 32;
parameter LOG2_FIFO_DEPTH = 5;
parameter DATA_LINE_WIDTH = 40;
parameter CONTROL_LINE_WIDTH = 0;
reg clk = 0;
reg i_mc_sreq_wen = 0;
wire o_mc_sreq_fifo_empty = 0, o_mc_sreq_fifo_full = 0;
reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_mc_sreq... | 7.508918 |
module tb_fifo_0 ();
//-----------------接口定义-------------------=//
reg sclk; //系统时钟
reg rd_clk; //读数据时钟
reg data_tvalid = 0; //FFT数据准备完毕
reg [13:0] data; //数据
reg rx_ready; //单片机接收准备
wire tx_ready; //uart发送准备
wire data_out;
//===============产生时钟信号==================//
initial sclk = 1;
alw... | 7.434651 |
module tb;
parameter DATA_WIDTH = 4,
FIFO_DEPTH = 4,
PTR_WIDTH = 3;
reg clk, reset, put, get;
wire empty_bar, full_bar;
wire [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] data_in;
integer i=0;
//override parameters via instantiation
<<<<<<< HEAD
FIFO_2clk #(DATA_WIDTH,FIFO_DEPTH) u1(
... | 7.110249 |
module tb;
parameter DATA_WIDTH = 4, FIFO_DEPTH = 4, PTR_WIDTH = 3;
reg rclk, wclk, reset, put, get;
wire empty_bar, full_bar;
wire [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] data_in;
integer i = 0;
//no parameters for GLS!
FIFO_2clk u1 (
.rclk(rclk),
.wclk(wclk),
.reset(reset)... | 6.746419 |
module: fifo_2clock_cascade
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo_2clock_cascade;
// Inputs
reg wclk;
reg [35:0] datain;
reg src_rdy_i;
reg rclk;
reg dst_rdy... | 6.93239 |
module tb_fifo_async_fwft ();
localparam S_RATE = 1000.0 / 200.0;
localparam M_RATE = 1000.0 / 201.7;
initial begin
$dumpfile("tb_fifo_async_fwft.vcd");
$dumpvars(0, tb_fifo_async_fwft);
#100000;
$finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = 1'b1;
... | 7.464611 |
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