code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_fifo_asyn_sync ();
wire [31:0] data_out_asyn;
wire [31:0] data_out_sync;
wire fifo_full;
wire fifo_empty_asyn;
wire fifo_empty_sync;
reg [31:0] data_in;
reg en_write;
reg en_read_asyn;
reg en_read_sync;
reg w_clk;
reg wrst_n;
reg r_clk;
reg rrst_n;
fifo_asyn_sync U1 (
da... | 6.574519 |
module: fifo_demux2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo_demux2;
// Inputs
reg clk;
reg rst;
reg [31:0] in;
reg in_valid;
reg select;
reg select_valid;
re... | 6.910751 |
module tb_fifo_gate;
parameter DATA_WIDTH = 32;
reg clk;
reg rst;
reg [DATA_WIDTH-1:0] data;
reg data_valid;
wire data_ready;
reg pass;
reg pass_valid;
wire pass_ready;
wire... | 6.628012 |
module: fifo_splitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo_splitter;
// Inputs
reg clk;
reg rst;
reg [31:0] data_in;
reg data_in_valid;
reg data_out1_ready;... | 6.761017 |
module tb_fifo_sum ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire tx;
//reg define
reg clk;
... | 6.968116 |
module tb_fifo_width_convert ();
localparam S_RATE = 1000.0 / 100.0;
localparam M_RATE = 1000.0 / 100.0;
initial begin
$dumpfile("tb_fifo_width_convert.vcd");
$dumpvars(0, tb_fifo_width_convert);
#10000000 $finish;
end
reg s_clk = 1'b1;
always #(S_RATE / 2.0) s_clk = ~s_clk;
reg m_clk = ... | 7.194647 |
module tb_fillEmptyCell ();
parameter STEP = 20;
reg [79:0] cell_all_in;
wire [79:0] cell_all_out;
wire full;
wire calc_done;
reg [3:0] random_pos;
fillEmptyCell filler (
.cell_all_in(cell_all_in),
.cell_all_out(cell_all_out),
.random_prob(6'b1),
.random_pos(random_pos),
.cal... | 8.177563 |
module tb_filter ();
localparam T = 20;
parameter N = 8;
reg clk, rst_n, act;
reg [N-1:0] a, b;
wire [2*N-1:0] result;
wire [N-1:0] c_i;
integer i;
filter result_1 (
clk,
rst_n,
act,
a,
b,
result,
c_i
);
always begin
clk = 1'b1;
#(T / 2);
clk = 1... | 6.504595 |
module tb_filter_window;
reg sclk;
reg s_rst_n;
reg in_line_vaild;
reg [7:0] din;
wire [7:0] Data00;
wire [7:0] Data10;
wire [7:0] Data20;
wire [7:0] Data01;
wire [7:0] Data02;
wire [7:0] Data11;
wire [7:0] Data12;
wire [7:0] Data21;
wire [7:0] Data22;
wire dout_flag;
//------------- g... | 6.946433 |
module tb_fir ();
wire CLK_i;
wire RST_n_i;
wire [12:0] DIN_i;
wire VIN_i;
wire [12:0] H0_i;
wire [12:0] H1_i;
wire [12:0] H2_i;
wire [12:0] H3_i;
wire [12:0] H4_i;
wire [12:0] H5_i;
wire [12:0] H6_i;
wire [12:0] H7_i;
wire [12:0] H8_i;
wire [12:0] H9_i;
wire [12:0] H10_i;
wire [12:0] ... | 7.402326 |
module: FixedPoint_FIR_Filter_TM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version ... | 7.257827 |
module tb_fir_adv ();
parameter nb = 11, order = 10, tot_bit = (order + 1) * nb;
wire CLK_i;
wire RST_n_i;
wire [nb-1:0] DIN1_i;
wire [nb-1:0] DIN2_i;
wire [nb-1:0] DIN3_i;
wire VIN_i;
wire [tot_bit-1:0] H_i;
wire [nb-1:0] DOUT1_i;
wire [nb-1:0] DOUT2_i;
wire [nb-1:0] DOUT3_i;
wire VOUT_i;
w... | 7.298441 |
module tb_fir;
parameter N = 8;
parameter STEP = 10;
integer count, fd;
reg [N*5-1:0] inj_data;
// Inputs
reg clk, rst;
reg [N-1:0] Xin;
reg [N-1:0] H0, H1, H2, H3;
// Outputs
wire [15:0] Yout;
// Instantiate the Unit Under Test (UUT)
//fir#(.N(N)) fir(
fir fir (
.clk (clk),
.rs... | 7.064631 |
module: FIR1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or... | 7.743492 |
module : tb_five_stage_cache_top_factorial
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), ... | 7.648506 |
module : tb_five_stage_cache_top_gcd
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to dea... | 7.648506 |
module : tb_five_stage_cache_top_mandelbrot
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"),... | 7.648506 |
module : tb_five_stage_cache_top_primes
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to ... | 7.648506 |
module: FixedPoint_Adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FixedPoint_Adder;
parameter WI1 = 8; //INPUT-1 integer length
parameter WF1 = 8; //INPUT-1 fraction lengt
... | 6.79281 |
module tb_fjmem ();
parameter adr_width = 24;
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
wire [adr_width-1:0] flash_adr;
wire [15:0] flash_d;
wire flash_oe_n;
wire flash_we_n;
reg [15:0] flash_do;
assign flash_d = (flash_oe_n) ? 16'bz : flash_do;
... | 7.208186 |
module: FlashingLED
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_FlashingLED;
// Inputs
reg clk;
reg rst;
// Note: CLK must be defined as a reg when using this method
... | 7.230286 |
module tb_flash_be_ctrl ();
//wire define
wire cs_n; //Flash片选信号
wire sck; //Flash串行时钟
wire mosi; //Flash主输出从输入信号
//reg define
reg sys_clk; //模拟时钟信号
reg sys_rst_n; //模拟复位信号
reg key; //模拟全擦除触发信号
//时钟、复位信号、模拟按键信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
key <= 1'b0;
... | 7.521548 |
module tb_flash_pp_ctrl ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg sys_clk;
reg sys_rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
sys_clk = 0;
sys_rst_n <= 0;
key <= 0;
#100 sys_rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 sy... | 7.767329 |
module tb_flash_se_ctrl ();
//wire define
wire cs_n;
wire sck;
wire mosi;
//reg define
reg sys_clk;
reg sys_rst_n;
reg key;
//时钟、复位信号、模拟按键信号
initial begin
sys_clk = 0;
sys_rst_n <= 0;
key <= 0;
#100 sys_rst_n <= 1;
#1000 key <= 1;
#20 key <= 0;
end
always #10 sy... | 8.149322 |
module tb_flip_flop;
reg clk, rst_n, d;
wire q;
// Instantiate counter
flip_flop ff0 (
.clk(clk),
.rst_n(rst_n),
.d(d),
.q(q)
);
// set up the clock period
always #5 clk = ~clk;
initial begin
// initialize clock and reset
clk <= 0;
rst_n <= 0;
... | 8.404567 |
module tb_float_step ();
localparam RATE = 1000.0 / 200.0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
initial begin
$dumpfile("tb_top.vcd");
$dumpvars(0, tb_float_step);
#10000 $finish;
end
function [31:0] double_to_float(inpu... | 6.810774 |
module.
//------------------------------------------------------------------
module tb_fltcpu();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CLK_HALF_PERIOD = 1;
... | 6.659433 |
module tb_forth1;
reg sys_clk_i;
reg sys_rst_i;
reg io_rd;
reg io_wr;
reg [15:0] io_din;
reg [15:0] io_addr;
reg [15:0] io_dout;
initial begin
$dumpfile("vcd/forth1.vcd");
$dumpvars(0, tb_forth1);
end
initial begin
$from_myhdl(io_din, sys_clk_i, sys_rst_i);
$to_myhdl(io_dout, io_... | 6.55735 |
module tb_forwarder ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ... | 7.249102 |
module: FPadder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, o... | 7.372755 |
module tb_fpmul ();
wire CLK_i;
wire [31:0] DATA_i;
wire [31:0] RES_i;
clk_gen CG (.CLK(CLK_i));
data_maker SM (
.CLK (CLK_i),
.DATA(DATA_i)
);
FPmul UUT (
.CLK (CLK_i),
.FP_A(DATA_i),
.FP_B(DATA_i),
.FP_Z(RES_i)
);
endmodule
| 6.907347 |
module FPMult_tb;
// Inputs
reg clk;
reg rst;
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] result;
wire [4:0] flags;
integer i;
// Instantiate the Unit Under Test (UUT)
FPMult_reduced uut (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.result(result),
.flags(fl... | 7.463027 |
module tb_fpmul ();
wire CLK_i;
wire RST_n_i;
wire [31:0] DIN_i;
wire [31:0] DOUT_i;
clk_gen CG (
.CLK (CLK_i),
.RST_N(RST_n_i)
);
data_maker SM (
.CLK (CLK_i),
.RST_N(RST_n_i),
.DATA (DIN_i)
);
FPmul UUT (
.clk (CLK_i),
.rst_n(RST_n_i),
.FP_A (DI... | 6.907347 |
module tb_fpu;
reg clk;
reg [1:0] rmode;
reg [2:0] fpu_op;
reg [31:0] opa, opb;
wire [31:0] out;
wire inf, snan, qnan;
wire ine;
wire overflow, underflow;
wire zero;
wire div_by_zero;
fpu dut_fpu_0
(
.clk (clk),
.rmode(rmode),
.fpu_op(fpu_op),
.opa(opa),
.opb(opb),
.out(out),
.inf(inf),
.snan(snan),
.qnan(q... | 6.534917 |
module tb_fpu_normalizer ();
// Testbench for fpu_normalizer
reg [23:0] mantissa;
reg [7:0] exponent;
reg [22:0] normalized_mantissa;
reg [7:0] normalized_exponent;
wire overflow;
wire underflow;
fpu_normalizer fpu_normalizer_inst (
.mantissa(mantissa),
.exponent(exponent),
.normali... | 6.875816 |
module tb_fpu_sp_comparator ();
// Inputs
reg signed [7:0] a;
reg signed [7:0] b;
// Outputs
wire unsigned [7:0] difference;
wire sign;
wire overflow;
// Instantiate the Unit Under Test (UUT)
fpu_comparator #(
.size(8)
) uut (
.a(a),
.b(b),
.difference(difference),
.... | 6.663318 |
module tb_fractionaln;
// fractionaln Parameters
parameter PERIOD = 10;
parameter P_WIDTH = 5;
parameter S_WIDTH = 3;
parameter INT_WIDTH = 8;
parameter FRAC_WIDTH = 24;
// fractionaln Inputs
reg Fin = 0;
reg rst_n = 0;
reg [ INT_WIDTH-1:0] Integer = 0;
reg ... | 7.695816 |
module tb_frameGenerator;
localparam LEN_TX_DATA = 64;
localparam LEN_TX_CTRL = 8;
reg tb_clock;
reg tb_reset;
wire [LEN_TX_DATA-1 : 0] tb_o_tx_data;
wire [LEN_TX_CTRL-1 : 0] tb_o_tx_ctrl;
initial begin
tb_clock = 1'b0;
tb_reset = 1'b0;
#1 tb_reset ... | 6.714946 |
module tb_frame_sync_generator;
reg clk;
reg clk_lp;
wire frame_sync_output;
GSR GSR_INST (
.GSR_N(1'b1),
.CLK (1'b0)
);
frame_sync_generator ins1 (
.lp_clk_i(clk_lp),
.out_clk_i(clk),
.frame_sync_o(frame_sync_output)
);
initial begin
clk = 1'b0;
end
always b... | 6.736331 |
module tb_freq ();
/*
reg sclk;
reg rst_n;
reg pulse;
wire [31:0] cnt_clk;
wire [31:0] cnt_squ;
wire [31:0] cnt_pulse;
initial sclk = 1;
always #5 sclk = ~sclk;
initial begin
rst_n = 0;
#100
rst_n = 1;
end
reg [31:0] cnt = 0;
always @(posedge sclk or negedge rst_n) begin
if(!rst_n) cnt <= 0;
else if(cnt... | 7.246341 |
module testbench;
reg inpClk, reset;
wire S;
FreqDiv FD1 (
inpClk,
reset,
S
);
initial begin
inpClk = 1'b1; // 1
reset = 1'b0; // 0
#20 reset = 1'b1; // 1
#10 reset = 1'b0; // 0
end
always begin
#10 inpClk = ~inpClk;
end
endmodule
| 7.015571 |
module tb_freq_div ();
reg rst, inclk;
wire sec_clk, min_clk, hour_clk;
freq_div test_feq (
rst,
inclk,
sec_clk,
min_clk,
hour_clk
);
initial begin
inclk = 0;
rst = 0;
end
initial #27 rst = 1;
initial begin
repeat (1000) #5 inclk = ~inclk;
end
endmodule... | 7.159323 |
module tb_freq_meter ();
//********************************************************************//
//****************** Parameter And Internal Signal *******************//
//********************************************************************//
//wire define
wire stcp; //输出数据存储寄时钟
wire shcp; //移位寄存器的时钟输入... | 8.138754 |
module TB_from_controller ();
wire clk;
reg reset;
wire [7:0] from_data;
wire [6:0] from_addr;
wire from_clk;
reg wb_cyc_i, wb_stb_i, wb_we_i;
reg [15:0] wb_adr_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
wire wb_ack_o;
from_controller from_controller (
.wb_clk_i (clk),
.wb_rst_i (... | 6.605472 |
module tb_fsm ();
reg clk;
reg rst_n;
reg key_in;
wire [1:0] state;
initial begin
clk = 1'b1;
rst_n = 1'b0;
key_in = 1'b1;
#100 rst_n = 1'b1;
#100 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key_in = 1'b0;
#20 key_in = 1'b1;
#80 key... | 7.134834 |
module tb_FSM_ex_control;
parameter s_IDLE = 2'b00; //States for the main FSM
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
parameter s_INIT = 3'b000; //States for the sub-FSM
parameter s_NRE_1 = 3'b001;
parameter s_ADC_1 = 3'b010;
parameter s_NOTHING = 3'b011;
parameter s_NRE_2 = 3'b100... | 7.792768 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantit... | 7.554736 |
module tb_ftdi_chip_model #(
parameter CHIP_EW = 0 // FTDI USB chip data width, 0=8bit, 1=16bit, 2=32bit. for FT232H is 0, for FT600 is 1, for FT601 is 2.
) (
output reg ftdi_clk,
output reg ftdi_rxf_n,
output reg ftdi_txe... | 7.23555 |
module tb_full_adder_cout;
// Inputs
reg a, b, c;
// Outputs
wire cout;
// Instantiate the Unit Under Test (UUT)
fa_cout uut (
.a(a),
.b(b),
.c(c),
.cout(cout)
);
initial begin
$dumpfile("tb_full_adder_cout.vcd");
$dumpvars(0, tb_full_adder_cout);
// Initialize Inpu... | 7.161246 |
module tb_full_adder_sum;
// Inputs
reg a, b, c;
// Outputs
wire sum;
// Instantiate the Unit Under Test (UUT)
fa_sum uut (
.a (a),
.b (b),
.c (c),
.sum(sum)
);
initial begin
$dumpfile("tb_full_adder_sum.vcd");
$dumpvars(0, tb_full_adder_sum);
// Initialize Input... | 7.161246 |
module tb_fusion #(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
) ();
reg [GPIO_D-1:0] gpio_o_dat... | 6.522731 |
module tb_fw ();
reg exmem_regwr, memwb_regwr;
reg [4:0] exmem_rd, memwb_rd, idex_rs1, idex_rs2;
wire [1:0] forwardA, forwardB;
forwarding_unit fw (
exmem_regwr,
exmem_rd,
memwb_regwr,
memwb_rd,
idex_rs1,
idex_rs2,
forwardA,
forwardB
);
initial begin
exm... | 6.724096 |
module tb_f_word_set ();
reg sys_clk;
reg sys_rst_n;
reg key_add;
reg key_sub;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#10000;
key_add <= 1'b1;
#50;
end
always #10 sys_clk = ~sys_clk;
f_word_set f_word_set_inst (
.sys_clk (),
.sys_rst_n(),
.key_add (... | 6.697354 |
module tb_gameChecker ();
wire [1:0] RamAddr;
wire [23:0] RamDat;
wire gameComplete;
reg CLK, RST = 1'b0;
reg [31:0] cycleCounter = 0;
// Testbench memory manipulation I/O
reg [23:0] ramInA = 24'h000000;
wire [23:0] ramOutA;
reg ramWrenA = 1'b1;
reg [1:0] ramAddrA = 2'b00;
gameChecker DUT_gameCh... | 6.665633 |
module tb_gates ();
reg a_in;
reg b_in;
wire o_and;
wire o_nand;
wire o_or;
wire o_nor;
wire o_xor;
wire o_xnor;
wire o_inv;
wire o_buf;
integer i;
and_gate AND_GATE (
.a_in (a_in),
.b_in (b_in),
.y_out(o_and)
);
nand_gate NAND_GATE (
.a_in (a_in),
.b_in (b... | 7.322367 |
module: gate_and
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_gate_and #(
parameter INPUT_COUNT = 8,
parameter INPUT_RANGE = 2**8
);
// Inputs
r... | 7.54105 |
module
// Module Name: /home/lsriw/SR/KonradAdasiewicz/lab2/gate_module/tb_gate_module.v
// Project Name: gate_module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: gate_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Addi... | 6.999332 |
module tb_genDone;
reg clk, rst, gen_en, sobel_en2;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGen(clk, rst, gen_en, sobel_en, addr, done);
addressGen ADDGEN (
clk,
rst,
gen_en,
sobel_en2,
addr,
done
);
reg gen_done, sobel_done;
wire gray... | 7.571897 |
module tb_generate1;
reg sysclk;
reg reset;
reg status;
parameter bus_width = 15;
reg [bus_width:0] din;
reg [bus_width:0] rdout;
initial begin
$dumpfile("vcd/generate1.vcd");
$dumpvars(0, tb_generate1);
end
initial begin
$from_myhdl(sysclk, reset, wrb, din);
$to_myhdl(rdout);
en... | 7.1758 |
module tb_generator (
clk,
resetn,
// num_data,
// fifo write bus
// fifo_full,
fifo_data,
fifo_wrreq,
ack
);
// paramenters
parameter DWIDTH = 8;
parameter input_file = "";
//
parameter WIDTH = 56;
parameter HEIGHT = 56;
localparam num_data = WIDTH * HEIGHT;
//portmap
... | 7.35437 |
module tb_generic_sync_ram;
reg clk;
reg [7:0] address;
reg [7:0] data_in;
wire [7:0] data_out;
reg [7:0] data_out_r;
reg cs;
reg we;
reg oe;
generic_sync_mem mem (
.clk(clk),
.address(address),
.data_in(data_in),
.data_out(data_out),
.cs(cs),
.we(we),
.oe(oe... | 6.666288 |
module: game_engin
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_gameengine;
// Inputs
reg clk;
reg collision_detected;
reg [1:0] player_choice;
reg [1:0] enemy_choice;
r... | 7.016196 |
module tb_gige_tx ();
reg srst;
reg clk;
wire tx_c_90, tx_dv;
wire [3:0] tx_d;
// clock
initial begin
clk = 0;
forever #(4) clk = ~clk;
end
// reset
initial begin
srst <= 1;
repeat (15) @(posedge clk);
srst <= 0;
end
top_gige #(
.SIM_FLAG(1)
) inst_top_gige (
... | 7.264755 |
module tb_gmii2fifo18 ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk ... | 6.655554 |
module tb_gmii2fifo72 ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk ... | 6.743546 |
module tb_gmii2fifo9 ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk =... | 6.740253 |
module tb_gmiisend ();
//
// System Clock 125MHz
//
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
reg gmii_tx_clk;
initial gmii_tx_clk = 1'b0;
always #8 gmii_tx_clk = ~gmii_tx_clk;
reg fifo_clk;
initial fifo_clk = 1'b0;
always #13.468 fifo_clk = ~fifo_clk;
//
// Te... | 7.834436 |
module tb_gng;
reg tb_clock;
reg tb_reset;
reg tb_clockEnable;
wire tb_valid_out;
wire [15:0] tb_data_out;
wire [2:0] nterm;
wire [7:0] ndata;
wire [7:0] nidle;
assign nterm = tb_data_out[(15-7)-:3];
assign ndata = tb_data_out[(15-4)-:8];
assign nidle = tb_data_out[(15-8)-:6];
initial begin
... | 7.097798 |
module tb_good_latch;
// Inputs
reg clk, reset, d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
good_latch uut (
.clk(clk),
.reset(reset),
.d(d),
.q(q)
);
initial begin
$dumpfile("tb_good_latch.vcd");
$dumpvars(0, tb_good_latch);
// Initialize Inputs
... | 6.676618 |
module tb_good_mux;
// Inputs
reg i0, i1, sel;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
good_mux uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.y (y)
);
initial begin
$dumpfile("tb_good_mux.vcd");
$dumpvars(0, tb_good_mux);
// Initialize Inputs
sel = ... | 7.020985 |
module tb_good_shift_reg;
// Inputs
reg clk, reset, d;
// Outputs
wire dout;
// Instantiate the Unit Under Test (UUT)
good_shift_reg uut (
.clk(clk),
.reset(reset),
.d(d),
.dout(dout)
);
initial begin
$dumpfile("tb_good_shift_reg.vcd");
$dumpvars(0, tb_good_shift_reg);
... | 7.276209 |
module tb_good_shift_reg;
// Inputs
reg clk, reset, d;
// Outputs
wire dout;
// Instantiate the Unit Under Test (UUT)
good_shift_reg uut (
.clk(clk),
.reset(reset),
.d(d),
.dout(dout)
);
initial begin
$dumpfile("tb_good_shift_reg.vcd");
$dumpvars(0, tb_good_shift_reg);
... | 7.276209 |
module tb_Gray ();
wire [2:0] code;
reg up;
reg down;
reg reset;
Gray_counter uut (
.clk_up(up),
.clk_down(down),
.code(code),
.reset(reset)
);
integer i;
initial begin
reset = 1;
#5;
reset = 0;
$display("%b", code);
up = 1;
#5;
up = 0;
... | 6.513005 |
module tb_GRAY2MEM;
reg clk, rst;
reg gen_done, sobel_done;
wire gray_en, sobel_en;
wire [5:0] state;
FSM fsm (
clk,
rst,
gen_done,
sobel_done,
gray_en,
sobel_en,
state
);
reg gen_en;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGe... | 7.189963 |
module tb_graycode;
reg clk;
reg rstn;
reg [3:0] xin;
wire [3:0] out;
graycode r0 (
clk,
xin,
rstn,
out
);
always #5 clk = ~clk;
initial begin
$dumpfile("graycode.vcd");
$dumpvars(0, tb_graycode);
$monitor($time, " %b", out);
rstn <= 0;
clk <= 0;
repeat (... | 6.781936 |
module.
`timescale 1ns/1ns
`include "greater.v"
module tb_greater;
reg [1:0] a;
reg [1:0] b;
wire out;
greater test_greater(a, b, out);
initial begin
$dumpfile("tb_greater.vcd");
$dumpvars(0, tb_greater);
// vector assignment like pattern matching
// in functional progra... | 6.603418 |
module tb_handshakee (); /* this is automatically generated */
// clock
reg clk;
initial begin
clk = 0;
forever #(1) clk = ~clk;
end
reg rst_n;
initial begin
rst_n <= 0;
#10 rst_n <= 1;
end
// (*NOTE*) replace reset, clock, others
reg valid_i;
reg data_i;
reg ready_i;
wi... | 6.542843 |
module tb_hardtanh_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam ... | 7.132403 |
module tb_hard_png ();
initial $dumpvars(1, tb_hard_png);
reg rstn = 1'b0;
reg clk = 1'b1;
always #10000 clk = ~clk; // 50MHz
initial begin
repeat (4) @(posedge clk);
rstn <= 1'b1;
end
reg istart = 1'b0;
reg ivalid = 1'b0;
wire iready;
reg [ 7:0] ibyte = 0;
... | 6.682756 |
module tb_ha_1b;
reg IN0, IN1;
wire SUM, CO;
ha_1b ha (
.IN0(IN0),
.IN1(IN1),
.SUM(SUM),
.CARRY_OUT(CO)
);
initial begin
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : %0b, CO : %0b", IN0, IN1, SUM, CO);
IN0 = 0;
IN1 = 0;
#1;
$display("IN0 : %0b, IN1 : %0b, SUM : ... | 6.524754 |
module tb_hk_mash111;
// mash111 Parameters
parameter PERIOD = 10;
// parameter WIDTH = 24;
parameter WIDTH = 9;
parameter A_GAIN = 2;
parameter OUT_REG = 1;
// mash111 Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// mash111 Outputs
wire [ 3:0] ... | 6.799648 |
module hsc_vlg_tst ();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg ext_clk;
reg ext_rst_n;
reg [0:0] treg_mem_clk;
reg [0:0] treg_mem_clk_n;
reg [15:0] treg_mem_dq;
reg [1:0] treg_mem_dqs;
// wires ... | 7.177094 |
module tb_hsync ();
reg clk;
wire hsync;
wire h264;
wire hblank_n;
always #50 clk = ~clk;
hsync hsync0 (
.clk(clk),
.hsync(hsync),
.h264(h264),
.hblank_n(hblank_n)
);
initial begin
clk <= 0;
#100000 $finish;
end
endmodule
| 6.516932 |
module: i2c_fsm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_i2c_fsm;
// Inputs
reg clk;
reg rst;
reg arst;
reg start;
reg scl_pad_i;
reg sda_pad_i;
// Outputs
wire ... | 7.65446 |
module tb_i2c_master;
// Inputs
reg [7:0] i_addr_data;
reg i_cmd;
reg i_strobe;
reg i_clk;
// Outputs
wire io_scl;
wire [7:0] o_data;
wire [2:0] o_status;
// Bidirs
wire io_sda_w;
reg io_sda;
reg en = 0;
assign io_sda_w = en ? io_sda : 1'bZ;
/*
initial
$monitor($time, ": i_clk=%b i_a... | 7.069776 |
module tb_i2s;
reg clk;
reg reset;
reg signed [15:0] IN_L, IN_R;
wire i2s_sclk;
wire i2s_lrclk;
wire i2s_dout;
wire signed [15:0] OUT_L, OUT_R;
wire i2s_din;
wire i2s_sampled;
// 24 MHz clock source
always #20.8333 clk = ~clk;
// reset
initial begin
`ifdef icarus
$dumpfile("tb_i2s.vcd");... | 6.554753 |
module tb_iclarke ();
reg [31:0] valp, vbet;
reg clk;
reg rst_n;
always #50 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
valp = 32'h46;
vbet = 32'h56;
#500;
rst_n = 1'b1;
#5000;
$finish;
end
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(0,... | 6.766365 |
module tb_icnbc;
parameter N = 8;
parameter MIN_LD = 2;
parameter MEM_DEPTH = 256;
reg clk;
reg rst;
reg [N-1:0] n;
reg start;
reg [N-1:0] min_ld;
wire [ 3:0] codes [N-1:0];
initial begin
clk <= 1'b0;
rst = 1'b1;
end
always #5 clk = ~clk;
initial be... | 6.627426 |
module tb_idle_deletion;
localparam CGMII_IDLE = 8'h07;
reg clock;
reg reset;
reg [63:0] data;
reg [63:0] data_aux;
reg [7:0] ctrl;
reg valid;
reg enable;
reg [9:0] counter;
wire [63:0] output_data;
initial begin
clock = 1'b0;
reset = 1'b1;
data = {64{1'b0}};
data_a... | 7.498726 |
module tb_idle_insert_file;
localparam NB_DATA = 64;
localparam NB_CTRL = 8;
localparam N_LANES = 20;
localparam N_BLOCKS = 100;
reg clock, reset, enable, in_valid; //control inputs
reg tb_enable_files;
reg [NB_DATA-1 : 0] tb_input_data;
reg [NB_CTRL-1 : 0] tb_input_ctrl;
reg [0 : NB_DATA-1] temp_... | 6.525598 |
module tb_ifchain1;
reg clk;
reg rstn;
reg status;
reg [3:0] a;
reg [3:0] b;
initial begin
$dumpfile("vcd/ifchain1.vcd");
$dumpvars(0, tb_ifchain1);
end
initial begin
$from_myhdl(a, b, clk, rstn);
$to_myhdl(status);
end
//wire rstn;
test dut_test (
clk,
rstn
)... | 6.592245 |
module top ();
wire [31:0] inst;
reg clk;
reg reset;
reg [31:0] wb_newpc;
reg [31:0] wb_newmsr;
reg wb_newpcmsr_valid;
reg exe_annul;
reg wb_annul;
reg [31:0] mem_newpc;
reg [31:0] mem_newmsr;
reg mem_newpc_valid;
reg mem_newmsr_valid... | 7.326089 |
module tb_IF;
// Parameters
localparam NB_PC_CONSTANT = 3;
localparam NB_PC = 32;
localparam NB_INSTRUCTION = 32;
localparam NB_MEM_WIDTH = 8;
// Ports
reg i_clock;
reg i_IF_branch;
reg i_IF_j_jal;
reg i_IF_jr... | 6.51731 |
module tb_iic_controller;
reg clk;
reg rst_n;
wire scl;
wire sda;
pullup (scl);
pullup (sda);
reg soc;
reg [ 9:0] sclDiv;
//master
wire [ 7:0] iic_rdms;
wire [ 7:0] iic_rdls;
wire iic_ack;
//slaver
reg [15:0] SwriteData;
wire [ 7:0] SreadData;
wire SwriteOK;
... | 6.574125 |
module tb_iic_test ();
reg sys_clk; //100M
reg rst_n;
reg [31:0] i_cfg_dat;
reg i_cfg_start_en;
wire iic_sda;
wire iic_scl;
iic_test u_iic_test (
.sys_clk (sys_clk), //100M
.rst_n (rst_n),
.i_cfg_dat (i_cfg_dat),
... | 6.627936 |
module data_mem_imre #(
parameter DATA_WIDTH = 100,
parameter WORD_WIDTH = 180
) (
clk,
rst_n,
wen,
waddr,
wdata,
ren,
raddr,
rdata
);
parameter ADDR_WIDTH = $clog2(WORD_WIDTH); //9
input wen, ren, clk, rst_n;
input [(ADDR_WIDTH-1):0] waddr, raddr;
input [(DATA_WIDTH-1... | 8.169423 |
module tb_iir;
wire CLK_i;
wire RST_n_i;
wire [8:0] DIN_i;
wire VIN_i;
wire [8:0] B0_i;
wire [8:0] B1_i;
wire [8:0] B2_i;
wire [8:0] A1_i;
wire [8:0] A2_i;
wire VOUT_i;
wire [8:0] DOUT_i;
wire SMPL_END_i;
wire END_SIM_i;
clk_gen CG (
.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST... | 7.404479 |
module tb_iir_adv;
wire CLK_i;
wire RST_n_i;
wire [10:0] DIN_i;
wire VIN_i;
wire [10:0] B0_i;
wire [10:0] B1_i;
wire [10:0] B2_i;
wire [10:0] A1_i;
wire [10:0] A2_i;
wire [10:0] A1_NEG_i;
wire [10:0] A1_2_A2_i;
wire [10:0] A1A2_i;
wire VOUT_i;
wire [10:0] DOUT_i;
wire SMPL_END_i;
wire E... | 7.325604 |
module: FIR1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or... | 7.743492 |
module tb_image_src ();
parameter H_Active = 1920;
parameter H_FrontPorch = 88;
parameter H_SyncWidth = 44;
parameter H_BackPorch = 148;
parameter V_Active = 1080;
parameter V_FrontPorch = 4;
parameter V_SyncWidth = 5;
parameter V_BackPorch = 36;
parameter Frame_cnt = 10;
parameter Frame_bpp = 24... | 7.435333 |
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