code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_img_mnist_unit ();
localparam RATE = 1000.0 / 300.0;
initial begin
$dumpfile("tb_img_mnist_unit.vcd");
$dumpvars(2, tb_img_mnist_unit);
#20000000 $finish;
end
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
wire cke = 1'b1... | 6.910056 |
module tb_imm_gen ();
reg [31:0] i_instruction;
reg [ 2:0] i_sel;
wire [31:0] o_dataout;
imm_gen DUT (
i_instruction,
i_sel,
o_dataout
);
task input_t();
begin
i_instruction = 32'h12353112; //0001_0010_0011_0101_0011_0001_0001_0010
i_sel = {$random} % 8;
en... | 6.501145 |
module test_impl_micron_controller (
input clk50MHz,
input sw_7,
input sw_6,
input sw_1,
input sw_0,
output mwe_L,
output moe_L,
output madv_L,
output mclk,
output mub_L,
output mlb_L,
output mce_L,
output mcre,
input mwait,
output ready,
//output reg clk_... | 6.652946 |
module tb_impl_uart_interface (
input clk50MHz,
input rx,
output tx,
output [7:0] debug_out
);
parameter BUS_WIDTH = 32;
parameter CTRL_WIDTH = 8;
wire [7:0] req;
assign req[6:0] = 0;
wire [7:0] ack;
reg clk;
wire [BUS_WIDTH-1:0] bus;
wire [CTRL_WIDTH-1:0] ctrl;
wire [BUS_WIDTH-1:0]... | 7.862894 |
modules testbench
* Dependencies :
*
* Company : Beijing soul
* Author : Hu Gang
*
*****************************************************************************/
`timescale 1ns/1ps
module tb(/*AUTOARG*/
// Outputs
stream_valid, stream_left, stream_done, stream_data2,
... | 6.73988 |
module tb_incomp_case;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
incomp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_incomp_case.vc... | 7.284379 |
module tb_incomp_case_net;
//input
reg i0, i1, i2;
reg [1:0] sel;
// Output
wire y;
//TB_SIGNALS
reg clk, reset;
// Instantiate the Unit Under Test (UUT)
incomp_case uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.y (y)
);
initial begin
$dumpfile("tb_incomp_cas... | 7.284379 |
module tb_input_top11 ();
reg clk, rstn;
reg req;
reg [15:0] data; //input
initial begin
clk = 1'b0;
rstn = 1'b0; //复位
req = 1'b1; //打开输入请求
data = 16'h7fff; //输入1
#80 rstn = 1'b1; // 解除复位
data = 16'h7fff;
#400 data = 16'h0000; //输入0
end
always begin
#5 clk = ~clk; ... | 7.333101 |
module TB_Insertion_block #(
parameter W = 42
);
// Inputs
reg clk;
reg rst;
reg wr, rd;
reg [(W-1)-1:0] data_in;
reg sub;
reg repair_period;
// Outputs
wire [(W-1)-1:0] data_out;
wire data_valid;
wire [(W-1)-1:0] data_fail;
wire fail;
// Instantiate the Unit Under Test (UUT)
Insertio... | 6.726677 |
module TB_INST ();
reg CLOCK_50;
reg rst;
initial begin
$display("simulation started!");
rst = 1'b0;
CLOCK_50 = 1'b0;
forever #2 CLOCK_50 = ~CLOCK_50;
end
SOPC sopc1 (
.clk(CLOCK_50),
.rst(rst)
);
reg dbus_we_delay;
reg [15:0] dbus_addr_delay;
reg [31:0] dbus_data_delay;... | 7.831 |
module InstructionMemoryTestbench;
reg clock;
reg [7:0] in;
wire [7:0] out;
InstructionMemory dut (
clock,
in,
out
);
initial begin
clock = 1;
in = 0;
$display("Teste 1: Buscando a intrucao 0");
in = 0;
#1 clock = 0;
#1 clock = 1;
in = 0;
$display("Test... | 6.694363 |
module tb_instructionRegister ();
wire [3:0] OPCODE, FUNCFIELD;
wire [3:0] A_ReadReg1RT, A_ReadReg2RT;
wire [1:0] A_Offset, A_RegSWLW;
wire [3:0] A_WriteRegRT_BT;
reg [15:0] D_MemData;
reg C_IRWrite;
reg clk, rst;
instructionRegister uut (
OPCODE,
FUNCFIELD,
A_ReadReg1RT,
A_Re... | 7.102099 |
module tb_instruction_fsm;
// Inputs
reg clk;
reg reset;
reg instr_fsm_enable;
// Outputs
wire e;
wire instr_fsm_done;
wire upper;
reg [9:0] instruction;
wire [5:0] encoding;
instruction_fsm instr_fsm (
.clk(clk),
.reset(reset),
.instr_fsm_enable(instr_fsm_enable),
.e(... | 7.102099 |
module tb_instru_mem ();
parameter MEMORY_WIDTH = 8;
parameter MEMORY_DEPTH = 64;
parameter NB_ADDR = 32;
parameter NB_INSTRUCTION = 32;
reg [ NB_ADDR-1:0] read_addr;
reg clock;
reg read_enable;
reg i_write_enable;
reg [ MEMO... | 6.506437 |
module
*/
module mem(
// input [15:0] in_data,
// input [4:0] in_addr,
input [5:0] out_addr,
output [15:0] out_data);
parameter ADDR_WIDTH=6;
parameter DEPTH =1<<ADDR_WIDTH;
reg [15:0] mem_data[DEPTH-1:0];
assign out_data = mem_data[out_addr];
endmodule
| 8.043954 |
module tb_instFetch;
//Port declarition
reg clk;
reg [5:0] mem_addr;
reg rst;
wire [31:0] inst;
wire valid;
wire [15:0] inst_hw;
wire is_inst_len_16;
integer fl;
//Module instancise
inst_fetch top (
inst_hw,
clk,
rst,
inst,
valid,
is_inst_len_16
);
mem ins... | 6.736553 |
module tb_inst_mem;
// Inputs
reg clk;
reg rst;
reg inst_in_v;
reg [`INST_WIDTH-1:0] inst_in;
// Outputs
wire inst_out_v;
wire [`INST_WIDTH-1:0] inst_out;
// Instantiate the Unit Under Test (UUT)
inst_mem uut (
.clk(clk),
.rst(rst),
.inst_in_v(inst_in_v),
.inst_in(inst_in)... | 6.994919 |
module
// Module Name: C:/Users/Filipe/Documents/Classes/Spring - 2013/SystemOnChipDesign/Project5/ise_project/tb_interface_plus_cell.v
// Project Name: soc_with_memory
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: memory_test_module
//
// Dependencies... | 6.999332 |
module tb;
parameter DATA_WIDTH=8, // Width of data bus
ADDR_WIDTH=8, // Width of address bus
NUM_INTR=16, // Number of peripheral controllers i.e. max number of interrupts
INTR_SERV=4, // Number of bits required to represent each interrupts (Depends on NUM_INTR)
MAX_DELAY=30, // Max delay to serve on... | 7.110249 |
module tb_intg ();
initial begin
$dumpfile("tb_intg.vcd");
$dumpvars;
end
reg clear, clock;
wire wf;
intg mod (
.wf(wf),
.clear(clear),
.clock(clock)
);
initial clock = 1'b0;
always #0.5 clock = ~clock;
initial begin
clear = 1'b1;
#1 clear = 1'b0;
#1000 $fini... | 6.584221 |
module tb;
parameter NUM_INTR = 16;
reg pclk_i, prst_i, pwrite_i, penable_i;
reg [3:0] paddr_i;
reg [3:0] pwdata_i;
wire [3:0] prdata_o;
wire pready_o;
wire pslverr_o;
wire [3:0] intr_to_service_o;
wire intr_valid_o;
reg intr_serviced_i;
reg [NUM_INTR-1:0] intr_active_i;
integer i;
intr_ctlr ... | 6.612288 |
module tb_int_ctl ();
reg clk;
reg rst_n;
// drive signal
reg [7:0] IE;
reg [7:0] TCON;
reg [1:0] SCON;
// out signal
wire [4:0] interupt;
wire [7:0] TCON_out;
// clk generator
initial begin
clk = 0;
forever #1 clk = ~clk;
end
// reset generator
initial begin
rst... | 6.749346 |
module TOP;
// Instruction Memory Interface Parameters
parameter IDATAW = 128;
parameter ISIZEW = 8;
parameter IADDRW = 32;
// Clock Interface
reg clk;
reg reset;
reg [ 3:0] int_vec;
wire mem_valid;
reg mem_ready;
wire [31:0] mem_address;
wire mem_wr_en;
... | 6.594167 |
module tb_inverter;
reg [`WIDTH-1:0] p;
reg [`WIDTH-1:0] q;
reg clk;
reg reset;
wire finish;
wire [`WIDTH-1:0] e;
wire [`WIDTH*2-1:0] d;
inverter uut (
p,
q,
clk,
reset,
finish,
e,
d
);
initial begin
p = 32'd23;
q = 32'd5;
clk = 0;
reset = ... | 6.926467 |
module: io_buf
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_iobuf;
// Inputs
reg [15:0] I;
reg T;
// Outputs
wire [15:0] O;
// Bidirs
wire [15:0] IO;
reg [15:0] IO_B... | 6.819267 |
module: ip_header_checksum
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ip_header_checksum;
// Inputs
reg clk;
reg [31:0] header;
reg reset;
// Outputs
wire [15:0] chec... | 7.241327 |
module tb_ip_receive ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
//板卡MAC地址
parameter BOARD_MAC = 48'h12_34_56_... | 7.352738 |
module tb_ir;
reg [15:0] iw = 16'b0000010001100101;
wire [ 3:0] op;
wire [2:0] Ra, Rb, Rd, func;
wire [5:0] imm;
wire [6:0] addr;
ir r (
iw,
op,
Ra,
Rb,
Rd,
func,
imm,
addr
);
initial
$monitor(
"iw = %b, op = %b, Ra = %b, Rb = %b, Rd = %b, fun... | 6.587801 |
module top ();
wire [31:0] inst;
reg clk;
reg reset;
reg read_strobe;
reg [31:0] read_addr;
reg transl;
reg priv;
wire [31:0] read_data;
wire read_stall;
wire [ 1:0] read_fault;
// Memory for IF:
reg [63:0] memory [102... | 7.326089 |
module tb_je_ip;
reg [7:0] spram[131071:0];
reg pclk, reset_n, pixel_wr_disable, img_req;
integer file_in, r, file_out;
wire mem_wr;
wire [ 7:0] mem_dataw;
wire [16:0] mem_addrw;
wire [16:0] mem_addrr;
reg [ 7:0] mem_datar;
wire img_rdy;
reg [ 2:0] spi_rd_cnt;
wire esp3... | 6.584107 |
module tb_jkff_nand ();
reg clk;
reg J;
reg K;
wire Q;
wire QBar;
jk_ff_behavioural ff (
.clk(clk),
.J(J),
.K(K),
.Q(Q),
.QBar(QBar)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
#10;
J = 1'b0;
K = 1'b0;
#10;
J = 1'b... | 6.516483 |
module testbench;
reg J, K, clk;
wire Q, Qn;
JK_FF JK_FF_1 (
J,
K,
clk,
Q,
Qn
);
initial begin
clk <= 1'b1;
J <= 1'b0;
K <= 1'b1;
#30 J <= 1'b1;
#30 K <= 1'b0;
#30 J <= 1'b0;
end
always begin
#10 clk = ~clk;
end
endmodule
| 7.015571 |
module tb_jump ();
reg Rst;
reg Clk;
reg [5:0] cond;
reg [7:0] DataOut_Bus;
reg [2:0] band;
wire [7:0] Addres_Instruction_Bus;
jump uut (
.Rst(Rst),
.Clk(Clk),
.cond(cond),
.DataOut_Bus(DataOut_Bus),
.band(band),
.Addres_Instruction_Bus(Addres_Instruction_Bus)
);
... | 7.221413 |
module test;
wire clk;
wire reset_p;
wire reset = ~reset_p;
reg stop;
clock clock (
clk,
reset_p
);
pdp10 pdp10 (
.clk (clk),
.reset(reset)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
stop = 0;
#100000 stop = 1;
$finish;
end
initial begin
... | 6.964054 |
module tb_16bit ();
reg [15:0] a;
reg [15:0] b;
wire [30:0] y;
KA_16bit dut (
a,
b,
y
);
initial begin
#5;
a = 16'b1010101110101011;
b = 16'b1101111011011110;
#10;
end
endmodule
| 6.641143 |
module tb_keyexp ();
reg clk;
reg rst_n;
reg [127:0] key_in;
reg start_in;
reg en_de;
reg [3:0] round_in;
// internal wires
wire [127:0] key_out;
wire ready_out;
// dump variable
parameter DUMP_FILE = "tb.vcd";
initial begin
$display("Dump variables..");
$dumpvars("A... | 6.804416 |
module tb_keypad;
/* naming rule: key_row_column_name */
reg key_0_0_1 = 0, key_0_1_2 = 0, key_0_2_3 = 0, key_0_3_A = 0;
reg key_1_0_4 = 0, key_1_1_5 = 0, key_1_2_6 = 0, key_1_3_B = 0;
reg key_2_0_7 = 0, key_2_1_8 = 0, key_2_2_9 = 0, key_2_3_C = 0;
reg key_3_0_0 = 0, key_3_1_F = 0, key_3_2_E = 0, key_3_3_D =... | 6.575387 |
module tb_key_control ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
parameter CNT_1MS = 20'd19 ,
CNT_11MS = 21'd69 ,
CNT_... | 9.169656 |
module tb_key_control ();
//**************************************************************//
//*************** Parameter and Internal Signal ****************//
//**************************************************************//
parameter CNT_1MS = 20'd19 ,
CNT_11MS = 21'd69 ,
CNT_... | 9.169656 |
module tb_key_extract #(
parameter PHV_LEN = 48 * 8 + 32 * 8 + 16 * 8 + 5 * 20 + 256,
parameter KEY_LEN = 48 * 2 + 32 * 2 + 16 * 2 + 5,
parameter KEY_OFF = (3 + 3) * 3
) ();
reg clk;
reg rst_n;
reg [PHV_LEN-1:0] phv_in;
reg phv_valid_in;
//signals us... | 8.267745 |
module tb_key_filter ();
reg clk;
reg rst_n;
reg key_in;
wire key_out;
key_filter #(
.SYS_CLK(500), // 500 Hz
.FILTER_TIME(20) // 20 ms
) component (
.clk(clk),
.rst_n(rst_n),
.key_in(key_in),
.key_out(key_out)
);
initial begin
clk = 1'b1;
rst_n = 1'... | 6.827627 |
module tb_key_schedule ();
reg clk;
reg signal_start;
reg [127:0] key;
wire [127:0] outKey;
wire [3:0] state;
wire finished;
key_schedule key_schedule (
.clk(clk),
.signal_start(signal_start),
.finished(finished),
.key(key),
.outKey(outKey),
.state_response(state)
)... | 7.52862 |
module tb_key_test;
//declare input to DUT
reg clk_tb;
reg sys_rst_n_tb;
reg key_in_tb;
//declare output of DUT
wire key_en_tb;
//instancing the DUT
key_test u1 (
.clk(clk_tb),
.sys_rst_n(sys_rst_n_tb),
.key_in(key_in_tb),
.key_en(key_en_tb)
);
//creat 1KHz clock
ini... | 6.945219 |
module tb_kogge;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] y;
wire cout;
wire [8:0] sum;
kogge_adder_8bit ksa (
.a(a),
.b(b),
.cin(cin),
.y(y),
.cout(cout),
.sum(sum)
);
initial begin
a = 8'b00001000;
b = 8'b00011011;
cin = 1'b0;
#100 a = 8'b... | 7.008121 |
module tb_L1_spi_master;
reg clk;
reg rst_n;
reg im_work_en;
reg [7:0] im_data;
wire [7:0] om_data;
reg im_MISO_spi;
wire om_MOSI_spi;
wire om_SCLK_spi;
wire om_send_finish;
wire om_receive_finish;
L1_spi_master_v2 #(
.MODE(2'b00)
) tb_U1 (
.clk(clk),
.rst_n(rst_n),
.... | 7.742308 |
module tb_L2_clk_read_cnt;
reg clk;
reg rst_n;
reg im_SCLK_spi;
wire om_up_edge;
wire om_down_edge;
wire om_high_read;
wire om_low_read;
L2_clk_read_cnt tb_U1 (
.clk (clk),
.rst_n(rst_n),
.im_SCLK_spi(im_SCLK_spi),
.om_up_edge (om_up_edge),
.om_down_edge(om_down_e... | 7.205289 |
module: LampState
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lamp_state;
// Inputs
reg [3:0] active_lights;
// Outputs
wire [15:0] lights_state;
// Instantiate the Un... | 7.417602 |
module tb_lane_assist;
reg CLK, RST, assist_right, assist_left, assist_disable;
wire [2:0] lane;
lane_assist DUT (
.CLK(CLK),
.RST(RST),
.assist_right(assist_right),
.assist_left(assist_left),
.assist_disable(assist_disable),
.lane(lane)
);
initial begin
CLK = 1'b0;
... | 6.837297 |
module tb_latch_N;
// latch_N Parameters
parameter PERIOD = 10;
parameter N = 8;
// latch_N Inputs
reg clk = 0;
reg [N-1:0] d = 0;
// latch_N Outputs
wire [N-1:0] q;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
latch_N #(
.N(N)
) u_latch_N (
.clk(clk),
... | 6.84923 |
module tb_layer1;
reg clock;
reg reset_n;
reg readdatavalid;
reg [15:0] readdata;
reg waitrequest;
reg ready;
reg cont = 1;
reg [9:0] counter = 0;
reg [15:0] memory[0:131072];
wire [31:0] address;
reg [31:0] rdadr;
reg isread = 0;
reg [7:0] s1_q;
reg [7:0] s2_q;
initial begin
isread <=... | 6.927942 |
module: lb_11bitsShiftRegister
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_11bitsShiftRegister;
// Inputs
reg clk;
reg reset;
reg load;
reg shift;
reg [10:0] data_in... | 7.689198 |
module: lb_16BaudTickCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_16BaudTickCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] prescale;
// Outputs
wire done;... | 6.566402 |
module: lb_16_n_8BaudTickCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_16_n_8BaudTickCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] prescale;
reg _16_or_8_ti... | 6.584844 |
module: lb_buffer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_buffer;
// Inputs
reg clk;
reg reset;
reg re;
reg [7:0] w_data;
reg we;
// Outputs
wire full;
wire ... | 6.761163 |
module: lb_clockCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_clockCounter;
// Inputs
reg clk;
reg reset;
reg [19:0] value;
// Outputs
wire done;
// Instant... | 6.890798 |
module: lb_contNumBits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_contNumBits;
// Inputs
reg clk;
reg reset;
reg parity_en;
reg bit8;
reg [1:0] value;
reg inc;
re... | 6.726019 |
module: lb_debounce
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_debouncer;
// Inputs
reg clk;
reg sw;
reg reset;
// Outputs
wire db;
// Instantiate the Unit Under... | 7.937816 |
module: lb_UART_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_FULL_UART_toplevel;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg oe;
reg adrs;
reg [7:0] ... | 8.136444 |
module: lb_pulseMaker
//
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_pulseMaker;
// Inputs
reg clk;
reg signal_in;
reg reset;
// Outputs
wire pulse;
// Instantiate the Unit Under Test (UUT)
lb_pulseMaker uut (
.clk(clk),
.signal_in(signal_in),
.r... | 7.225992 |
module: lb_shiftreg_rx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_shiftreg_rx;
// Inputs
reg clk;
reg reset;
reg data_in;
reg shift;
// Outputs
wire [10:0] data_o... | 7.757516 |
module: soc_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_soc_block;
// Inputs
reg clk;
reg reset;
reg rx;
reg interrupt;
reg bit8;
reg parity_en;
reg odd_n_ev... | 6.636792 |
module: lb_UART_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_full_toplevel;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg oe;
reg adrs;
reg [7:0] ... | 8.136444 |
module: lb_UART_Rx_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Receive_fsm;
// Inputs
reg clk;
reg reset;
reg bit8;
reg parity_en;
reg [19:0] baudPr... | 7.600689 |
module: lb_UART_Rx_Core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Rx_Core;
// Inputs
reg clk;
reg reset;
reg [19:0] baud_value;
reg bit8;
reg parity_en;
reg ... | 7.600689 |
module: lb_UART_Rx_fsm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Rx_fsm;
// Inputs
reg clk;
reg reset;
reg baudTickCounterDone;
reg bitCounterDone;
reg rx;
... | 7.16557 |
module: lb_UART_toplevel
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_toplevel;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg [7:0] data;
reg bit8;
reg par... | 8.136444 |
module: lb_UART_Tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx;
// Inputs
reg clk;
reg reset;
reg cs;
reg we;
reg [7:0] data;
reg bit8;
reg parity_en;
reg... | 7.609279 |
module: lb_UART_Tx_Core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx_core;
// Inputs
reg clk;
reg reset;
reg [7:0] data;
reg start;
reg [19:0] baud_value;
re... | 8.892 |
module: lb_UART_Tx_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx_CU;
// Inputs
reg clk;
reg reset;
reg start;
reg bit8;
reg parity_en;
reg [19:0] ... | 8.892 |
module: lb_UART_Tx_FSM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lb_UART_Tx_FSM;
// Inputs
reg clk;
reg reset;
reg start;
reg baudTickCounterDone;
reg bitCounterDone;... | 6.929707 |
module tb_lcbbc;
parameter N = 8;
parameter MIN_HD = 2;
parameter MEM_DEPTH = 256;
reg clk;
reg rst;
reg [N-1:0] n;
reg start;
reg [N-1:0] min_hd;
wire [N-1:0] codes;
initial begin
clk <= 1'b0;
rst = 1'b1;
end
always #5 clk = ~clk;
initial begin
r... | 6.851514 |
module tb_LCD_controller;
// Inputs
reg clk;
reg reset;
// Outputs
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [3:0] SF_D;
// Instantiate the Unit Under Test (UUT)
LCDcontroller LCDcontroller_inst (
.clk(clk),
.reset(reset),
.LCD_E(LCD_E),
.LCD_RS(LCD_RS),
.LCD_RW(LCD... | 7.290108 |
module tb_LCD_control_unit;
reg clk;
reg reset;
wire LCD_RS;
wire LCD_RW;
wire LCD_EN;
wire [3:0] LCD_SF_D;
LCD_controller_module dut_LCD_controller_inst (
.clk(clk),
.reset(reset),
.LCD_RS(LCD_RS),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_SF_D(LCD_SF_D)
);
localpar... | 7.290108 |
module: lCounter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lCounter;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
... | 6.651678 |
module tb8;
reg [7:0] seq;
wire [3:0] idx;
leadingZero8 u_lze_8 (
seq,
idx
);
initial begin
#3 seq = 8'h80;
#3 $display("seq %h, idx %d\n", seq, idx);
seq = 8'h01;
#3 $display("seq %h, idx %d\n", seq, idx);
seq = 8'h08;
#3 $display("seq %h, idx %d\n", seq, idx);
seq... | 6.864263 |
module tb_LeakyIntegrator2;
parameter WI = 8;
parameter WF = 32;
reg [(WI+WF-1):0] InLeaky;
reg Clk;
reg LIdvi;
wire [(WI+WF-1):0] OutSmooth;
wire LIdvo;
parameter Clockperiod = 10;
initial Clk = 0;
always #(Clockperiod / 2) Clk = ~Clk;
LeakyIntegrator2 #(
.WI(WI),
.WF(WF)
) UUTL... | 6.531694 |
module tb_leakyrelu_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam... | 7.742861 |
module tb_led ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led_out;
//reg define
reg key_in;
//*****... | 7.421857 |
module tb_leds;
reg clk = 0;
always begin
#5;
clk = ~clk;
end
reg key;
wire w_data;
colors colors_inst (
.clk(clk),
.button(key),
.data(w_data)
);
initial begin
$dumpfile("out.vcd");
$dumpvars(0, tb_leds);
key = 1'b0;
#100;
@(posedge clk);
#0;
k... | 6.792791 |
module: lb_reset
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lf_reset;
// Inputs
reg clk;
reg resetb;
wire system_reset;
// Instantiate the Unit Under Test (UUT)
lb_r... | 7.707976 |
module tb_lightcube8_top;
reg clk;
reg rst;
//clock generating
real CYCLE_100MHz = 10;
always begin
clk = 0;
#(CYCLE_100MHz / 2);
clk = 1;
#(CYCLE_100MHz / 2);
end
wire resetn;
assign resetn = ~rst;
//reset generating
initial begin
rst = 1'b0;
#8 rst = 1'b1;
#2000 rst... | 7.429878 |
module tb_link_controller();
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 16;
parameter ADDR_PAGE_NUM_LOG = 12;
logic clk;
logic rst_n;
logic [ADDR_PAGE_NUM_LOG - 1:0]data_table_read_addr;
logic [ADDR_PAGE_NUM_LOG - 1:0]data_table_read_last_addr;
logic data_table_empty;
logic data_table_read_req;
logic data_table... | 7.254308 |
module: ll8_to_txmac
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ll8_to_txmac;
// Inputs
reg clk;
reg reset;
reg clear;
reg [7:0] ll_data;
reg ll_sof;
reg ll_eof;
reg... | 8.270685 |
module tb_lmmi_mst
#( //--begin_param--
//----------------------------
// Parameters
//----------------------------
parameter AWIDTH = 16,
parameter DWIDTH = 32,
parameter MODEL_NAME = "LMMI_MST",
parameter integer TIMEOUT_VALUE = 512
) //--end_param... | 7.428441 |
module tb_lms;
reg clk;
reg rst_n;
reg [15:0] d;
reg [15:0] x;
reg [ 3:0] u;
reg [15:0] signal;
wire [15:0] y;
wire [15:0] err;
wire [15:0] out;
initial begin
clk = 0;
rst_n = 0;
signal = 0;
d = 0;
x = 0;
u = 0;
#100
rst_n = 1;
#6000000
$finish;
end
always #10 clk = ~clk;
lms
//#(
//.W(16)
//)
lms_inst
(... | 7.461522 |
module tb_LO;
// Inputs
reg clk;
reg rst;
reg start;
// Outputs
wire [15:0] sin;
wire [15:0] cos;
// DUT
local_oscillator dut (
.clk (clk),
.rst (rst),
.start(start),
.sin (sin),
.cos (cos)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0... | 7.374222 |
module tb_logic ();
reg clk, reset;
reg a, b, c, yexpected;
wire y;
reg [31:0] vectornum, errors;
reg [3:0] testvectors[10000:0];
// instantiate device under test
logic dut (
y,
a,
b,
c
);
// generate clock
always begin
clk = 1;
#5;
clk = 0;
#5;
end
// at ... | 7.026219 |
module tb_logic_analysis;
//print_task.vϢӡװ
print_task print ();
//sys_ctrl_task.vϵͳʱӲԪϵͳλ
sys_ctrl_task sys_ctrl (
.clk (clk),
.rst_n(rst_n)
);
//input
wire clk; //FPAGʱź25MHz
wire rst_n; //ϵͳλź
reg [3:0] signal; //4·ź
reg trigger; //1·źţΪػ½ش
reg tri_mode; //źģʽѡ1--ش0--½ش
r... | 6.612361 |
module tb_log_memory;
localparam NB_DATA = 16;
localparam DEPTH = 32;
localparam NB_ADDR = $clog2(DEPTH);
reg clock, reset, run;
reg [NB_DATA-1 : 0] input_data;
wire [NB_DATA-1 : 0] output_data;
reg [NB_ADDR-1 : 0] read_addr;
wire tb_mem_full;
initial begin
clock = 0;
... | 6.661808 |
module tb_lookupflow ();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk =... | 6.57943 |
module tb_lpf ();
reg [31:0] y_ex, x, lpf_k, ek_ex, ki, uk_min, uk_max;
reg clk;
reg rst_n;
reg lpfsta;
always #50 clk = ~clk;
initial begin
clk = 1'b0;
rst_n = 1'b0;
lpfsta = 1'b0;
y_ex = 32'h46;
x = 32'h56;
lpf_k = 32'h66;
#500;
lpfsta = 1'b1;
rst_n = 1'b1;
#10... | 7.046486 |
module : tb_LRU
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software... | 7.326626 |
module tb_LTC2351_controller ();
reg clk;
reg reset_n;
wire go;
wire [15:0] sample_rate;
wire sdo;
wire [95:0] data_out;
wire valid;
wire conv;
wire [95:0] data_in;
reg en;
parameter CLK_HALF_PERIOD = 20; // 25Mhz
parameter RST_DEASSERT_DELA... | 6.815079 |
module is to test the LTC2351 model
*/
module tb_LTC2351_model();
reg clk;
reg reset_n;
reg conv;
wire sdo;
wire [95:0] data_in;
assign data_in = {2'bzz, 14'h3111, 2'bzz, 14'h3222, 2'bzz, 14'h3333, 2'bzz, 14'h3444, 2'bzz, 14'h3555, 2'bzz, 14'h3666};
par... | 7.58345 |
module tb_lut_exponential ();
localparam SZ = 8;
reg [SZ-1:0] angle;
wire [SZ-1:0] exp;
reg clk;
// ------------------------------------------------------------------------------
// Waveform generator
// ----------------------------------------------------------------... | 7.371991 |
module tb_lut_piecewise_exponential ();
localparam SZ = 8;
reg [SZ-1:0] angle;
wire [SZ-1:0] exp;
reg clk;
//wire [SZ-1:0] slope;
//wire [SZ-1:0] bias;
//wire [SZ-1:0] angle_out;
//wire [2*SZ-1:0] MulRst;
// ------------------------------------------------------------... | 7.893788 |
module TB_LUT_SHIFT;
parameter ROM_WIDTH = 5;
// Inputs
reg CLK;
reg EN_ROM1;
reg [4:0] ADRS;
//outputs
wire [ROM_WIDTH-1:0] O_D;
// Instantiate the Unit Under Test (UUT)
LUT_SHIFT uut (
.CLK(CLK),
.EN_ROM1(EN_ROM1),
.ADRS(ADRS),
.O_D(O_D)
);
initial begin
// I... | 7.0073 |
module tb_lzma_compressor ();
reg clk = 1'b0;
reg rstn = 1'b0;
always #5 clk = ~clk;
initial begin
repeat (5) @(posedge clk);
rstn <= 1'b1;
end
wire i_ready;
wire i_valid;
wire i_last;
wire [7:0] i_data;
wire o_valid;
wire [7:0] o_data;
wire o_last;
... | 6.708391 |
module: TemperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m1;
// Inputs
reg [31:0] tc_base;
reg [7:0] tc_ref;
reg [15:0] adc_data;
// Outputs
wire [31:... | 8.396779 |
module: GasDetectorSensor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m2;
// Inputs
reg arst;
reg clk;
reg din;
// Outputs
wire [2:0] dout;
// Instantiate the Unit U... | 7.168269 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.