code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module: MemoryUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m6;
// Inputs
reg arst;
reg clk;
reg wren;
reg [34:0] din;
// Outputs
wire [34:0] dout;
// Instantiat... | 7.210848 |
module tb_m6502_alu;
reg [ 7 : 0] tb_operation;
reg [ 7 : 0] tb_op_a;
reg [ 7 : 0] tb_op_b;
reg tb_carry_in;
wire [ 7 : 0] tb_result;
wire tb_carry;
wire tb_zero;
wire tb_overflow;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
//------------------------... | 7.384695 |
module: M65C02_RAM
//
// Dependencies:
//
// Revision:
//
// 1.00 12B04 MAM File Created
//
// 2.00 12K18 MAM Modified to support new version of the M65C02_RAM
// module which emulates Asynchronous LUT-based RAM,
// Synchronous, flow-through RAM (Bl... | 7.521356 |
module: ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m7;
// Inputs
reg arst;
reg clk;
reg request;
reg confirm;
reg [1:0] password;
reg [1:0] syskey;
reg [... | 7.944032 |
module tb ();
reg i_clk;
reg i_rstn;
reg [15:0] i_data;
reg [15:0] i_weight;
reg [31:0] i_pre_result;
wire [15:0] o_data_next;
wire [15:0] o_result;
mac u0 (
.i_clk(i_clk),
.i_rstn(i_rstn),
.i_data(i_data),
.i_weight(i_weight),
.i_pre_result(i_pre_resul... | 7.195167 |
module tb_MACC ();
parameter BITWIDTH = 32;
parameter ADDRWIDTH = 4;
parameter MEMHEIGHT = 2 ** ADDRWIDTH;
localparam input_A_data_path = {`path, "tb/data/MACC_input_A.bin"};
localparam input_B_data_path = {`path, "tb/data/MACC_input_B.bin"};
localparam input_C_data_path = {`path, "tb/data/MACC_input_C.bi... | 7.086065 |
module: multi_MAC_Base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mac_base;
// Inputs
reg clk;
reg sof;
reg [79:0] A;
reg [15:0] B;
// Outputs
wire [179:0] C;
wire ... | 7.174319 |
module tb_MAC_mac_unit;
reg clk;
reg reset;
reg [7:0] in_1;
reg [7:0] in_2;
reg [7:0] in_add, num_a, num_x, num_b, num_c;
reg mode;
reg mul_input_mux, adder_input_mux;
wire [16:0] mac_output;
reg [16:0] check_tri;
reg [7:0] num_a_test[2:0];
reg [7:0] num_x_test[2:0];
reg [7:0] num_b_test[2:0];... | 7.906038 |
module tb_MAC_SWITCH ();
reg clk;
reg arst_n;
initial begin
$dumpfile("./vcd/tb_switch.vcd");
$dumpvars(0, mac_switch);
arst_n <= 1'b0;
#100 arst_n <= 1'b1;
#10000 $finish;
end
always begin
clk <= 1'b1;
#10;
clk <= 1'b0;
#10;
end
reg [127:0] h_fifo_dout;
wire h_fi... | 7.392951 |
module tb_main_fsmc;
// design_main_fsmc Inputs
reg clk;
reg rst_n;
reg [15:0] fsmc_A;
reg fsmc_NE;
reg fsmc_NWE;
reg fsmc_NOE;
// design_main_fsmc Outputs
// design_main_fsmc Bidirs
wire [15:0] fsmc_D;
reg [15:0] fsmc_wdata;
wire [15:0] fsm... | 7.383994 |
module: mapping_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mapping_controller;
// Inputs
reg clk_rxg;
reg rst_rx_n;
reg [11:0] data_trained0;
reg [11:0] da... | 6.927136 |
module tb_mash111;
// mash111 Parameters
parameter PERIOD = 10;
parameter WIDTH = 24;
parameter A_GAIN = 1;
// mash111 Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// mash111 Outputs
wire [ 3:0] y_o;
wire [WIDTH-1:0] e_o;
initial begin
fore... | 7.252604 |
module tb_master #(
parameter data_width = 8,
reg_num = 4
) (
input wire clk,
input wire rst,
// outputs: generated inputs for DUT
output reg [data_width - 1 : 0] reg_a,
output reg [data_width - 1 : 0] reg_b,
// input: outputs of DUT
input wire [data_width : 0] inp
);
// file ... | 6.644801 |
module tb_master_mem ();
reg clk, reset, active;
reg [7:0] base_addr;
reg [3:0] num_row, num_col;
wire [127:0] out_addr;
wire [15:0] out_en;
wire done;
always begin
#5;
clk = ~clk;
end
initial begin
clk = 0;
#5;
reset = 1;
active = 0;
base_addr = 8'h00;
num_col = 4'... | 7.060122 |
module TB_MAXPOOL2;
// Inputs
reg [35:0] y;
reg clk;
reg start;
reg reset;
// Outputs
wire [1:0] mx2_done;
wire [3:0] mx2_count;
wire [35:0] mx2_output;
// Instantiate the Unit Under Test (UUT)
MAXPOOL2 uut (
.mx2_input(y),
.clk(clk),
.start(start),
.reset(reset),
... | 6.554961 |
module tb_mdct;
reg clock;
reg reset;
reg [ 7:0] dcti;
reg idv;
wire [11:0] dcto;
wire odv;
reg [31:0] icnt = 0;
reg [31:0] ocnt = 0;
initial begin
$dumpfile("output/vcd/_tb_mdct.vcd");
$dumpvars(0, tb_mdct);
end
initial begin
$from_myhdl(clock, ... | 7.44928 |
module: MDF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_MDF;
// Inputs
reg clk;
reg rst;
reg [3:0] entrada;
// Outputs
wire salida;
wire [15:0]q;
// Instantiate th... | 6.629823 |
module tb_mealy ();
initial begin
$dumpfile("tb_mealy.vcd");
$dumpvars;
end
reg clock;
wire outp;
reg inp, reset;
initial clock = 1'b1;
always #5 clock = ~clock;
mealy m1 (
.reset(reset),
.clock(clock),
.inp (inp),
.outp (outp)
);
initial begin
reset <= 1... | 7.573422 |
module tb_memArr ();
parameter width_height = 4;
localparam data_width = width_height * 8;
localparam en_bits = width_height;
reg clk;
reg [en_bits - 1:0] rd_en;
reg [en_bits - 1:0] wr_en;
reg [data_width - 1:0] wr_data;
reg [data_width - 1:0] rd_addr;
reg [data_width - 1:0] wr_addr;
wire [data_wid... | 6.797715 |
module tb_memories (
input wire clk_i,
input wire reset_i,
input wire [15:0] xpm_addr_i,
output reg [31:0] xpm_data_o,
input wire [15:0] xdm0_addr_i,
input wire [15:0] xdm0_data_i,
input wire xdm0_wr_en_i,
output reg [15:0] xdm0_data_o,
input wire [15:0] xdm1_addr_i,
input wire... | 7.033243 |
module tb_MEMINTERFACE;
reg clk, rst;
reg gen_done, sobel_done;
wire gray_en, sobel_en;
wire [5:0] state;
FSM fsm (
clk,
rst,
gen_done,
sobel_done,
gray_en,
sobel_en,
state
);
reg gen_en;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addre... | 7.116508 |
module: MemoryUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_MemoryUnit;
// Inputs
reg arst;
reg clk;
reg wren;
reg [34:0] din;
// Outputs
wire [34:0] dout;
// In... | 7.210848 |
module tb_memory_writeback ();
localparam STEP = 10;
parameter OP_LOAD = 7'b0000011;
parameter OP_STORE = 7'b0100011;
parameter OP_BRANCH = 7'b1100011;
parameter OP_IMM = 7'b0010011;
parameter OP_OP = 7'b0110011;
parameter OP_JUMP = 7'b1101111;
parameter FUNC3_B = 3'b000; // sb, lb
parameter FUNC3... | 7.484526 |
module tb_memtest ();
parameter fml_depth = 26;
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
wire [fml_depth-1:0] fml_adr;
wire fml_we;
wire fml_stb;
reg fml_ack;
reg [63:0] fml_di;
wire [63:0] fml_do;
/* 100MHz system clock... | 7.513725 |
module : tb_mem_interface
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
*/
module tb_mem_interface ();
reg clk, reset;
reg read, write;
reg [7:0] address;
reg [31:0]in_data;
wire valid, ready;
wire[7:0] out_addr;
wire[31:0]out_data;
reg report;
/... | 7.266902 |
module tb_mergeBoard ();
parameter STEP = 20;
reg [79:0] board_in;
reg [1:0] movDir;
wire movable;
wire [79:0] board_after;
mergeBoard mb (
.board_in(board_in),
.movDir(movDir),
.movable(movable),
.board_after(board_after)
);
initial begin
$dumpfile("tb_mergeBoard.vcd");
... | 6.88557 |
module TB_message_collector;
reg clk;
reg reset;
reg start;
reg [31:0] a;
reg [31:0] b;
wire [511:0] message;
MessageCollector U1 (
clk,
reset,
start, // Execution inputs
a,
b, // Data inputs
message // Message output
);
initial begin
clk = 1;
reset =... | 6.631377 |
module tb_me_double;
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memor... | 6.524799 |
module tb_micron_controller_init ();
parameter BUS_WIDTH = 32;
parameter CTRL_WIDTH = 8;
reg clk50MHz;
wire [BUS_WIDTH-1:0] bus;
wire [CTRL_WIDTH-1:0] ctrl;
wire [7:0] req;
assign req[6:0] = 0;
wire [ 7:0] ack;
wire [22:0] BCR_CONFIG;
assign BCR_CONFIG = {
3'b000, // [22:20] Reserved, mus... | 7.50232 |
module tb_microstep_pwm_control ();
localparam RATE = 1000.0 / 125.0;
initial begin
$dumpfile("tb_microstep_pwm_control.vcd");
$dumpvars(0, tb_microstep_pwm_control);
#10000000 $finish;
end
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~cl... | 6.970791 |
module micro_sim_tb ();
parameter GPIO_D = `GPIO_D;
parameter N = 4;
parameter IMG_SIZE = 439;
localparam PATH = "/home/ivan/XilinxProjects/2dconv-FPGA/src/TEST/MEM_CONV_MCU/";
localparam FILENAME = "mem0";
localparam OUTFNAME = "out_mem0";
wire [GPIO_D-1:0] gpio_i_data_tri_i;
wire o_led... | 6.639304 |
module tb_minimac ();
/* 100MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 25MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #20 phy_rx_clk = ~phy_rx_clk;
/* 25MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #20 ph... | 7.256816 |
module tb_minority ();
reg [2:0] test_vector;
wire y;
minority uut (
.a(test_vector[2]),
.b(test_vector[1]),
.c(test_vector[0]),
.y(y)
);
integer i;
initial begin
test_vector = 3'b000;
#5;
$display(test_vector, y);
for (i = 0; i < 7; i = i + 1) begin
assign ... | 6.578721 |
module tb_minuse ();
reg run_code, clk, in_flag, out_flag;
reg [ 7:0] in;
reg [11:0] address;
reg [15:0] code;
wire fgo, fgi;
wire [ 7:0] out;
wire [15:0] te;
mano_cpu mc (
run_code,
clk,
in_flag,
out_flag,
in,
address,
code,
fgo,
fgi,
out,
... | 6.705289 |
module: mips_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Testbench Verilog code for 16 bit single cycle MIPS CPU
module tb_mips16;
// Inputs
reg clk;
re... | 6.692025 |
module TBMipsTestLoopJalSim ();
reg clk, rst;
MIPS cpu (
.clk(clk),
.rst(rst)
);
integer i = 0;
integer cnt = 0;
initial begin
$readmemh("C:/Users/24312/Desktop/tiny-CPU/dat/mipstestloopjal_sim.dat",
cpu.im.instruction_memory);
end
initial clk = 0;
initial begin
r... | 6.533401 |
module TBMipsTestLoop ();
reg clk, rst;
MIPS cpu (
.clk(clk),
.rst(rst)
);
integer i = 0;
integer cnt = 0;
initial begin
$readmemh("C:/Users/24312/Desktop/tiny-CPU/dat/mipstestloop_sim.dat",
cpu.im.instruction_memory);
end
initial clk = 0;
initial begin
rst = 0;
... | 6.533401 |
module tb_mipstest_pipelinedloop ();
reg clk, rst;
CPU cpu (
.clk(clk),
.rst(rst)
);
wire [31:0] p1_IF_PC = cpu.IF_PC;
wire [31:0] p2_ID_PC = cpu.ID_PC;
wire [31:0] p3_EX_PC = cpu.EX_PC;
wire [31:0] p4_MEM_PC = cpu.MEM_PC;
wire [31:0] p5_WB_PC = cpu.WB_PC;
integer _cnt = 0;
initial be... | 6.559166 |
module tb_mips_bard;
// The `assert` module is defined in the same file.
// Instantiate the `mips_bard` module.
mips_bard mips_bard (
.clk(clk),
.rst(rst),
.instruction(instruction),
.pc(pc),
.data_out(data_out)
);
// Clock signal.
reg clk;
always #1 clk = ~clk;
// Reset signal.
... | 7.965727 |
module tb_mips_cpu ();
reg rst, clk;
wire [31:0] out_pc;
wire [15:0] out_result;
mips_cpu m_cpu (
rst,
clk,
out_pc,
out_result
);
initial begin
rst = 0;
#33;
rst = 1;
end
initial begin
clk = 0;
forever #5 clk = ~clk;
end
endmodule
| 6.93793 |
module tb_miriscv_top ();
parameter HF_CYCLE = 2.5; // 200 MHz clock
parameter RST_WAIT = 10; // 10 ns reset
parameter RAM_SIZE = 1024; // in 32-bit words
// clock, reset
reg clk;
reg rst_n;
miriscv_top #(
.RAM_SIZE (RAM_SIZE),
.RAM_INIT_FILE("C:\\altera\\13.0sp1\\Projects\\Riscv_Pro... | 7.796864 |
module tb_mm2s ();
reg clk = 1;
always @(*) clk <= #2 ~clk;
reg [15:0] resetn_reg = 0;
wire resetn;
wire send_data;
always @(posedge clk) resetn_reg <= {resetn_reg[14:0], 1'b1};
assign resetn = resetn_reg[12];
assign send_data = resetn_reg[15];
reg [31:0] reg_data;
initial begin
wait (s... | 7.906907 |
module tb_MM_control ();
reg Start;
reg clk, rst;
wire result_en, control;
wire [3:0] addr_x, addr_A, addr_P;
MM_control DUT (
.Start(Start),
.clk(clk),
.rst(rst),
.result_en(result_en),
.control(control),
.addr_x(addr_x),
.addr_A(addr_A),
.addr_P(addr_P)
);... | 6.504637 |
module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Modificador_ciclo_trabajo;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
... | 8.169432 |
module_stereo_dac_output.v
// Description: Test bench for interpolating stereo sigma-delta DAC
// -----------------------------------------------------------------------------
module tb_module_i2s();
localparam CLK_FREQ = 100_000_000;
localparam SAMPLE_WIDTH = 16;
localparam SAMPLE_RATE = 480... | 6.674981 |
module_name.v //[文件名小写]
// Created On : 2021-05-21
// Version : V 1.0
// Author : Rongye
// Description :
// Modification :
//
//======================================================================================================
module tb_MODULE_NAME;
//------------------------------... | 8.2186 |
module tb_Motherboard;
reg clk;
reg rst;
reg [15:0] switches;
wire [15:0] led;
integer I;
integer K;
Motherboard #(
.CLOCK_DIVIDER(1)
) DUT (
.clk100Mhz(clk),
.rst (rst),
.switches (switches),
.led (led)
);
task t... | 6.969386 |
module: top_mp
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mp;
// Inputs
reg clk;
reg rst;
// Instantiate the Unit Under Test (UUT)
top_mp uut (
.clk(clk),
.rst(rs... | 8.791186 |
module tb_mc_ctrl ();
reg clk;
reg rstn;
reg ena;
reg [5:0] ID_from_Host;
reg [5:0] Tag_from_Bus;
wire Ready_from_PE;
reg Enable_from_Bus;
reg [31:0] value_from_Bus;
reg weight_wea_from_Host;
reg ifmap_wea_from_Host;
reg psum_wea_from_Host;
wire Enable_to_PE;
wire Ready_to_Bus;
wire [31:... | 6.667301 |
module tb_multiplexer ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_multiplexer.vcd");
$dumpvars(0, tb_multiplexer);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter SEL_WIDTH... | 6.829662 |
module tb_multiplexer ();
reg [3:0] w;
reg [1:0] sel;
wire [3:0] y;
multiplexer4x1 test_multiplexer4x1 (
.w (w),
.sel(sel),
.y (y)
);
initial begin
sel <= 2'b00;
w <= 4'b0000;
#10;
w <= 4'b0001;
#10;
w <= 4'b0010;
sel <= 2'b01;
#10;
w <= 4'b0... | 6.829662 |
module tb_multiplier;
parameter N = 16;
parameter STEP = 10;
integer count, fd;
reg [N-1:0] inj_data;
// Inputs
reg clk, rst;
reg [(N/2)-1:0] in1, in2;
// Outputs
wire [N-1:0] out;
// Instantiate the Unit Under Test (UUT)
//fir#(.N(N)) fir(
multiplier multiplier (
.in1(in1),
.in2(... | 7.552829 |
module tb_mult_shift_add ();
parameter WIDTH = 8;
reg clk;
reg [WIDTH - 1 : 0] S_data1, S_data2;
wire [2 * WIDTH - 1 : 0] F_mult;
initial begin
clk = 0;
S_data1 = 0;
S_data2 = 0;
#10 S_data1 = 2;
S_data2 = 6;
#10 S_data1 = 7;
S_data2 = 9;
#10 S_data1 = 17;
S_data2 = 12;
... | 6.975821 |
module: mult_unsigned_pipe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mult_unsigned_pipe;
parameter WI1 = 1, //length of the integer part, operand 1
WF1 = 5, //len... | 7.33655 |
module
// Module Name: tb_mul_mod_module.v
// Project Name: pro_fpga_sm2
// Target Device:
// Tool versions:
// Description:
// 模乘模块验证
// 1. 产生随机输入，使能模乘模块
// 2. 等待模乘模块输出结果
// 3. 与直接模乘运算的结果进行比较
// 4. 开始下一次测试
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///... | 6.999332 |
module tb_mutex ();
reg clk;
reg arst_n;
initial begin
$dumpfile("./vcd/tb_mutex.vcd");
$dumpvars(0, mutex_impl);
arst_n <= 1'b0;
#100 arst_n <= 1'b1;
#6000 $finish;
end
always begin
#10 clk <= 1'b1;
#10 clk <= 1'b0;
end
reg req_0;
reg req_1;
initial begin
req_0 <= ... | 7.180151 |
module tb_mux16to1_gate;
reg [15:0] in;
reg [3:0] sel;
wire out;
mux16to1_gate mux (
out,
in,
sel
);
initial begin
$monitor($time, " in=%16b | sel=%4b | out=%1b", in, sel, out);
end
initial begin
#0 in = 16'b1010101010101010;
sel = 4'b0000;
repeat (15) #10 sel = sel... | 8.284665 |
module tb_mux16to1_glvl ();
reg [15:0] inp;
reg [3:0] sel;
wire outp;
mux16to1_glvl mux (
.outp(outp),
.sel (sel),
.inp (inp)
);
initial begin
$dumpfile("tb_mux16to1_glvl.vcd");
$dumpvars;
end
initial begin
$monitor("inp = %b, sel = %b, outp = %b", inp, sel, outp);
... | 8.284665 |
module BancoPruebamux2_1_2bits_reset_ff; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
//... | 7.293212 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module: mux2in1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mux2in1;
// Inputs
reg [31:0] i_dat0;
reg [31:0] i_dat1;
reg i_control;
// Outputs
wire [31:0] o_dat;
// ... | 7.071047 |
module tb_mux2x1;
reg [1:0] din;
reg sel;
wire dout;
mux2x1 mux (
dout,
sel,
din
);
initial begin
#0 din = 2'b00;
sel = 0;
#20 sel = 1;
#20 din = 2'b01;
sel = 0;
#20 sel = 1;
#20 din = 2'b10;
sel = 0;
#20 sel = 1;
#20 din = 2'b11;
sel = 0;
#2... | 6.635589 |
module tb_mux2_1(); //testbench的格式和待测试RTL模块的格式相同,也是以“module”开始以“endmodule
| 6.566912 |
module
module tb_led();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led_out ;
//reg define
reg key_in ;
//****... | 7.342042 |
module tb_mux4 ();
parameter NB = 32;
parameter NB_SELECT = 2;
reg [NB_SELECT-1:0] select;
reg [ NB-1:0] a;
reg [ NB-1:0] b;
reg [ NB-1:0] c;
reg [ NB-1:0] d;
wire [ NB-1:0] data;
initial begin
a = 32'd1;
b = 32'd80;
c = 32'd250;
d = 32'd999;
... | 6.617536 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module tb_mux4to1;
wire [31:0] out;
reg [31:0] in1, in2, in3, in4;
reg [1:0] sel;
mux4to1 m1 (
out,
in1,
in2,
in3,
in4,
sel
);
initial
$monitor($time, " in1=%h in2=%h in3=%h in4=%h sel=%b out=%h", in1, in2, in3, in4, sel, out);
initial begin
in1 = 32'b10101010... | 7.125511 |
module tb_mux4to1_glvl ();
wire outp;
reg [3:0] inp;
reg [1:0] sel;
mux4to1_glvl mux (
.outp(outp),
.inp (inp),
.sel (sel)
);
initial begin
$dumpfile("tb_mux4to1_glvl.vcd");
$dumpvars;
end
initial begin
inp = 4'b0101;
sel = 2'b00;
#5 sel = 2'b01;
#5 sel = 2'... | 7.73663 |
module tb_mux4x1;
reg [3:0] din;
reg [1:0] sel;
wire dout;
mux4x1 mux (
dout,
sel,
din
);
initial begin
#0 din = 4'b0000;
sel = 2'b00;
#20 sel = 2'b01;
#20 sel = 2'b10;
#20 sel = 2'b11;
#20 din = 4'b0001;
sel = 2'b00;
#20 sel = 2'b01;
#20 sel = 2'b10;
... | 6.937852 |
module: mux5
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_mux5;
// Inputs
reg [4:0] inputA;
reg [4:0] inputB;
reg controlSignal;
// Outputs
wire [4:0] outMux;
// Inst... | 7.087865 |
module MuxTestbenchData;
reg [7:0] in1;
reg [7:0] in2;
reg control;
wire [7:0] out;
Mux #(
.N(8)
) dut (
.in1(in1),
.in2(in2),
.control(control),
.out(out)
);
initial begin
$display("Teste 1: Selecionando a entrada 1");
in1 = 22;
in2 = 14;
control = 0;
... | 7.8824 |
module tb_MUXpreALU ();
wire [15:0] ALU_1_IN, ALU_2_IN;
reg [15:0] PC;
reg [15:0] D_ReadReg1RT, D_BT, D_Offset;
reg [15:0] D_ReadReg2RT, D_RegSW;
reg [15:0] D_JUMP_SE_Out, D_SE_Out, D_USE_Out, D_L1S_Out;
reg C_SignExtend;
reg [1:0] C_RegDstRead1R;
reg C_RegDstRead2R;
reg C_ALUSrc_A;
reg [2:0] C_A... | 6.969239 |
module MuxTestbenchData;
reg [1:0] in1;
reg [1:0] in2;
reg control;
wire [1:0] out;
Mux #(
.N(2)
) dut (
.in1(in1),
.in2(in2),
.control(control),
.out(out)
);
initial begin
$display("Teste 1: Selecionando a entrada 1");
in1 = 1;
in2 = 0;
control = 0;
... | 7.8824 |
module tb_mux_2_1 ();
reg in_1;
reg in_2;
reg sel;
wire out;
initial
//begin end之间顺序执行，速度极快
begin
in_1 <= 1'b0;
in_2 <= 1'b0;
sel <= 1'b0;
end
//每隔10ns对in_1赋值
always #10 in_1 <= {$random} % 2; //结果只能为1 0
always #10 in_2 <= {$random} % 2; //结果只能为1 0
always #10 se... | 6.981773 |
module TB_Mux_3x1;
parameter P = 32;
// Inputs
reg CLK;
reg [1:0] MS;
reg [P-1:0] D_0;
reg [P-1:0] D_1;
reg [P-1:0] D_2;
//outputs
wire [P-1:0] D_out;
// Instantiate the Unit Under Test (UUT)
Mux_3x1 uut (
.MS(MS),
.D_0(D_0),
.D_1(D_1),
.D_2(D_2),
.D_out(D_out)
... | 6.570949 |
module tb_mux8_2;
wire [7:0] t_out;
reg [7:0] t_in_a, t_in_b;
reg t_sel;
mux8_2 dut (
.in_a(t_in_a),
.in_b(t_in_b),
.sel (t_sel),
.out (t_out)
);
initial begin
$monitor(t_in_a, t_in_b, t_sel, t_out);
t_in_a = 8'b10101010;
t_in_b = 8'b01010101;
t_sel = 1'b0;
#... | 6.743904 |
module tb_mux_behav ();
reg in1, in2, sel;
wire out;
mux_behav UUT (
out,
in1,
in2,
sel
);
initial begin
in1 = 1'b0; // here we apply inputs to the logic
in2 = 1'b0;
sel = 1'b0;
#10;
in1 = 1'b0;
in2 = 1'b1;
sel = 1'b0;
#10;
in1 = 1'b1;
in2 = ... | 6.553501 |
module : tb_mux_bus
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Soft... | 7.250913 |
module tb_mux_for;
// Inputs
reg i0, i1;
reg i2, i3;
reg [1:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_for uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.i3 (i3),
.y (y)
);
initial begin
$dump... | 7.764209 |
module tb_mux_for_net;
// Inputs
reg i0, i1;
reg i2, i3;
reg [1:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_for uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.i3 (i3),
.y (y)
);
initial begin
$... | 7.89109 |
module tb_mux_generate;
// Inputs
reg i0, i1;
reg i2, i3;
reg [1:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_generate uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.i3 (i3),
.y (y)
);
initial begin... | 8.324065 |
module tb_mux_mem_data (
input [15:0] in_1,
input [15:0] in_2,
input mem_data_select,
output [15:0] mux_out
);
assign mux_out = mem_data_select ? in_1 : in_2;
endmodule
| 8.328469 |
module tb_myHough ();
// UUT Inputs
wire tb_x[10:0];
wire tb_y[9:0];
wire tb_value;
wire clk;
wire ce;
// UUT Outputs
wire [4:0] theta;
wire [10:0] rho;
// ile blockramów? 2048 x ? tyle blockramów ile theta, długość to rho
myHough myInstance (
.pixel_x(tb_x), // up to 2000px
.pixe... | 7.961568 |
module tb_myosctest;
reg rst_n; //͵ƽλź
wire clkdiv; //8Ƶź
myosctest myosctest (
.rst_n (rst_n),
.clkdiv(clkdiv)
);
initial begin
rst_n = 0;
#1000;
rst_n = 1;
#50000;
$stop;
end
endmodule
| 6.956316 |
module tb_mythcore_test;
// Inputs
reg clk, reset;
// Outputs
wire [9:0] out;
// Instantiate the Unit Under Test (UUT)
core uut (
.clk (clk),
.reset(reset),
.out (out)
);
initial begin
$dumpfile("tb_mythcore_test.vcd");
$dumpvars(0, tb_mythcore_test);
clk = 1;
res... | 7.170844 |
module tb_m_delay_line;
reg clk;
reg [3:0] delay;
reg [9:0] din;
wire [9:0] dout;
initial begin
$from_myhdl(clk, delay, din);
$to_myhdl(dout);
end
m_delay_line dut (
clk,
delay,
din,
dout
);
endmodule
| 7.290343 |
module tb_m_delay_line_w10;
reg clk;
reg [3:0] delay;
reg [9:0] din;
wire [9:0] dout;
initial begin
$from_myhdl(clk, delay, din);
$to_myhdl(dout);
end
m_delay_line_w10 dut (
clk,
delay,
din,
dout
);
endmodule
| 7.290343 |
module tb_m_fifo_2clock_cascade;
reg wclk;
reg [35:0] datain;
reg src_rdy_i;
wire dst_rdy_o;
reg [15:0] space;
reg rclk;
wire [35:0] dataout;
wire src_rdy_o;
reg dst_rdy_i;
reg [15:0] occupied;
reg reset;
initial begin
$from_myhdl(wclk, datain, src_rdy_i, space, rclk, dst_rdy_i, occupied, ... | 6.682988 |
module nand_gate_top;
reg I0, I1;
wire Out;
nand_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %... | 6.783006 |
module NanoRiscTestbench;
reg clock;
wire [7:0] instructionFromInstructionMemory;
wire [7:0] instructionAddressToInstructionMemory;
wire [7:0] dataFromDataMemory;
wire [3:0] addressToDataMemory;
wire [7:0] dataToDataMemory;
reg [15:0] cycleCounter;
integer i;
NanoRisc nRisc (
clock,
in... | 7.674536 |
module D_Flip_Flop (
R7_OBUF,
ZERO,
MUX_B_REG_VAL,
FA1_C,
CLR_IBUF,
Q_reg_0,
Clk_With_Enabled_4,
HA0_S_5,
Q_reg_1,
Sub,
Q_reg_2,
Q_reg_3,
HA0_S_6,
Q_reg_4,
Q_reg_5,
R5_OBUF,
R4_OBUF,
Q_reg_6,
Q_reg_7
);
output [0:0] R7_OBUF;
output ZERO;
... | 7.225235 |
module D_Flip_Flop_6 (
R7_OBUF,
FA4_C,
Q_reg_0,
MUX_B_REG_VAL,
CLR_IBUF,
Q_reg_1,
Clk_With_Enabled_4,
Q_reg_2,
Q_reg_3,
Sub,
Q_reg_4,
FA0_C,
Q_reg_5,
R5_OBUF,
R4_OBUF,
Q_reg_6,
Q_reg_7
);
output [0:0] R7_OBUF;
output FA4_C;
output Q_reg_0;
outp... | 6.607773 |
module D_Flip_Flop_60 (
R1_OBUF,
CLR_IBUF,
REG_BANK_INPUT,
Clk_With_Enabled
);
output [0:0] R1_OBUF;
input CLR_IBUF;
input [0:0] REG_BANK_INPUT;
input Clk_With_Enabled;
wire CLR_IBUF;
wire Clk_With_Enabled;
wire [0:0] R1_OBUF;
wire [0:0] REG_BANK_INPUT;
FDRE #(
.INIT(1'b0),
... | 6.607773 |
module D_Flip_Flop_61 (
Q_reg_0,
NEXT_IA_OBUF,
Q_reg_1,
Q_reg_2,
CLR_IBUF,
Q_reg_3,
CLK_IBUF_BUFG,
Q_reg_4,
Q_reg_5,
JMP,
Q_reg_6,
Q_reg_7,
Q_reg_8
);
output Q_reg_0;
output [0:0] NEXT_IA_OBUF;
output [1:0] Q_reg_1;
output Q_reg_2;
input CLR_IBUF;
input Q_... | 6.607773 |
module D_Flip_Flop_62 (
Q_reg_0,
Q_reg_1,
NEXT_IA_OBUF,
Q_reg_2,
CLR_IBUF,
Q_reg_3,
CLK_IBUF_BUFG,
Q_reg_4,
Q_reg_5,
Q_reg_6,
JMP,
Q_reg_7,
Q_reg_8
);
output Q_reg_0;
output Q_reg_1;
output [0:0] NEXT_IA_OBUF;
output Q_reg_2;
input CLR_IBUF;
input Q_reg_3;... | 6.607773 |
module D_Flip_Flop_7 (
R7_OBUF,
Q_reg_0,
Q_reg_1,
CLR_IBUF,
Q_reg_2,
Clk_With_Enabled_4,
Q_reg_3,
FA1_C,
Sub,
Q_reg_4,
Q_reg_5,
R5_OBUF,
R4_OBUF,
Q_reg_6,
Q_reg_7
);
output [0:0] R7_OBUF;
output [0:0] Q_reg_0;
output [0:0] Q_reg_1;
input CLR_IBUF;
in... | 7.11469 |
module tb_navre ();
reg sys_clk;
initial sys_clk = 1'b1;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
wire pmem_ce;
wire [9:0] pmem_a;
reg [15:0] pmem_d;
reg [15:0] pmem[0:1023];
always @(posedge sys_clk) begin
if (pmem_ce) pmem_d <= pmem[pmem_a];
end
wire dmem_we;
wire [9:0] dmem_a;
... | 6.65372 |
module tb_NbitRegister;
localparam N = 4;
reg [N-1:0] Data_in;
wire [N-1:0] Data_out;
reg clock;
reg clear;
NbitRegister reg0 (
.Data_in(Data_in),
.Data_out(Data_out),
.Clock(clock),
.Clear(clear)
);
//
initial begin
Data_in = 0;
clear = 1;
#20;
Data_in =... | 6.787769 |
module: netwalk_decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_netwalk_decoder;
parameter DECODER_IN_WIDTH=4;
parameter DECODER_OUT_WIDTH=1<<DECODER_IN_WIDTH;
// Inputs
... | 6.961294 |
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