code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module: netwalk_flow_meter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_netwalk_flow_meter;
// Inputs
reg clk;
reg reset;
reg glbl_program_en;
reg [5:0] meter_program_add... | 6.555677 |
module tb_thermo_maj;
reg [14:0] in1;
reg [14:0] in2;
reg [14:0] in3;
reg [14:0] in4;
wire [14:0] out2;
majority first (
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.out(out2)
);
initial begin
in1 <= 15'b000000000000011;
in2 <= 15'b000000001111111;
in3 <... | 6.775331 |
module tb_new_CPU ();
reg Clk, Rst, key_data, key_clk;
wire [15:0] RdestOut;
wire [7:0] red, green, blue;
wire hsync, vsync, blankN, vgaClk;
CPU uut (
.Clk(Clk),
.Rst(Rst),
.key_data(key_data),
.key_clk(key_clk),
.red(red),
.green(green),
.blue(blue),
.hsync(h... | 6.899623 |
module tb (
seg,
an,
clk,
sw
);
input clk;
wire rst;
// reg clk_rst;
wire clk_2hz;
wire clk_1hz;
wire clk_fast;
wire clk_blink;
wire reg_mode;
wire adj_sec_mode;
wire adj_min_mode;
wire pause_mode;
wire [3:0] digit_1;
wire [3:0] digit_2;
wire [3:0] digit_3;
wire [3:0] ... | 6.86926 |
module tb_nic;
parameter DATA_WIDTH = 64;
parameter CLK_CYCLE = 4;
parameter NUM_OF_PAC = 10000; // how many packets will be sent
reg clk, reset; // sync high active reset
// Ports from router side
reg net_ro, net_polarity, net_si;
reg [0:DATA_WIDTH - 1] net_di;
wire net_so, net_ri;
wire [0:DATA_WI... | 6.700027 |
module tb_noise;
reg clk, rst;
reg [7:0] din;
wire [31:0] a, b;
wire [3:0] state;
wire adivbyzero, bdivbyzero;
wire ab_start;
wire [7:0] gin;
wire window_7x7_start;
reg [7:0] image_data[163839:0];
//图像像素索引
reg [31:0] index;
reg empty;
integer fp1, fp2, fp3, fp4;
initial begin
//初始化激励... | 7.737418 |
module tb_non_blocking ();
wire [1:0] out;
reg sys_clk;
reg sys_rst_n;
reg [1:0] in;
//初始化系统时钟、全局复位和输入信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
in <= 2'b0;
#20;
sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_c... | 8.165388 |
module nor_gate_top;
reg I0, I1;
wire Out;
nor_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %b,... | 6.849274 |
module not_gate_top;
reg I0;
wire Out;
not_gate gate0 (
I0,
Out
);
initial begin
$display("I0 : %b, Out : %b", I0, Out);
I0 = 0;
#1;
$display("I0 : %b, Out : %b", I0, Out);
I0 = 1;
#1;
$display("I0 : %b, Out : %b", I0, Out);
end
endmodule
| 6.836215 |
module tb_Num_Inm;
reg [7:0] i_Instruction;
wire [7:0] NUM;
Num_Inm uut(
.i_Instruction(i_Instruction),
.NUM(NUM)
);
initial
begin
i_Instruction = 0;
#2i_Instruction = 8'b00000001;
#2i_Instruction = 8'b00001011;
#2i_Instruction = 8'b11111111; ... | 6.883674 |
module tb_odd_fre ();
reg clk_i;
reg rst_n;
wire clk_div;
odd_fre odd_fre_inst (
.clk_i (clk_i),
.rst_n (rst_n),
.clk_div(clk_div)
);
always #1 clk_i = ~clk_i;
initial begin
clk_i = 0;
rst_n = 0;
#100 rst_n = 1;
end
endmodule
| 7.478758 |
module tb_odd_parity_check ();
reg serial;
reg clk;
reg reset;
wire parity;
OddParityCheck pc (
.serial_in(serial),
.clk(clk),
.reset(reset),
.parity_valid(parity)
);
initial begin
clk <= 0;
reset <= 1;
serial <= 0;
#5 reset <= 0;
#10 serial <= 1; //Parit... | 7.11386 |
module tb_ofdm ();
reg clk;
reg reset;
reg [3:0] inputdata;
reg in;
reg [3:0] out_count;
wire esig;
wire [3:0] out;
reg eesig;
OFDM ofdm1 (
.reset(reset),
.clk (clk),
.x_in (in),
.x_out(out)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
integ... | 7.054788 |
module testbench #(
parameter PW = 256, // packet total width
parameter CW = 16, // packet control width
parameter N = 32, // ctrl/status width
parameter DEPTH = 8192, // simulus memory depth
parameter TARGET = "DEFAULT", // physical synthesis/si... | 6.640835 |
module tb_ones_count;
integer i;
reg [7:0] dat_in;
wire [3:0] count;
ones_count counter (
count,
dat_in
);
initial begin
for (i = 0; i <= 8'b11111111; i = i + 1) begin
dat_in = i;
#10;
end
end
endmodule
| 6.544435 |
module tb_one_port_mem;
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
//Auto-calculated, user dont touch
localparam addressWidth = $clog2(addresses);
wire [ width-1:0] readData;
reg readEnable;
reg [addressWidth-1:0] address;
reg ... | 7.798339 |
module tb_openmips_min_sopc ();
reg CLOCK_50;
reg rst;
//Turn ovr the time signal per 50 sec, so the T = 20ns, f = 50MHz
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
//The resetting signal is valid in the beginning, in the 195ns it becomes invalid, so as the min SOPC start
... | 8.249896 |
module tb ();
reg CLK;
reg RST;
wire [ 2:0] x_min;
wire [ 2:0] y_min;
wire [15:0] cost_mini;
wire output_vld;
parameter DUTY = 1;
always #1 CLK = ~CLK;
initial begin
CLK = 1;
RST = 0;
#10 RST = 1;
end
always @(posedge CLK or negedge RST) begin : proc_output_v... | 7.002324 |
module or_gate_top;
reg I0, I1;
wire Out;
or_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %b, I... | 6.94011 |
module tb_or1200_ic_ram ();
parameter dw = `OR1200_OPERAND_WIDTH; // value is 32
parameter aw = `OR1200_ICINDX; // value is 11
wire [63:0] dataout;
reg clk, rst;
reg [aw-1:0] addr;
reg [3:0] we;
reg [63:0] datain;
reg en;
initial begin
// #100 $finish;
end
initial begin
#0 rst = 1... | 6.808996 |
module tb_ov5640 ();
wire ov5640_pwdn;
wire ov5640_rst_n;
wire power_done;
wire busy;
wire rd_iic_data;
wire iic_clk;
wire iic_sda;
reg sys_clk;
reg sys_rst_n;
reg start;
reg [31:0] wr_data;
initial begin
sys_clk = ... | 6.931881 |
module tb_ov7725_data ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter H_VALID = 10'd640, //行有效数据
H_TOT... | 7.829089 |
module tb_ov7725_top ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter H_VALID = 10'd640, //行有效数据
H_TOTA... | 6.854354 |
module tb_overall #(
parameter AMBA_WORD = 32,
parameter AMBA_ADDR_WIDTH = 20,
parameter DATA_WIDTH = 32
);
Interface IF ();
Stimulus stm (.stim_bus(IF));
Checker chk (.chkbus(IF));
GoldModel gld (.goldenbus(IF));
golden_bank gldbnk (.goldenbnk(IF));
Coverage covbus (.covbus(IF));... | 6.550032 |
module: packet_sender
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_packet_sender;
// Inputs
reg clk;
reg reset;
reg wr_dst_rdy_i;
reg [7:0] packet_size_i;
reg start;
/... | 6.779287 |
module tb_padding ();
parameter DATA_WIDTH = 32;
parameter STRIDE = 2;
parameter IMAGE_WIDTH = 6; //Width
parameter IMAGE_HEIGHT = 6; //Height
parameter PADDING = 3; //3*3 Kernel
parameter CHANNEL_NUM = 4; //Height
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam IMAGE_SIZE_PADDING ... | 6.709442 |
module tb_parallel_converter;
reg [ 9:0] counter;
reg clock;
reg reset;
reg enable;
reg [ 65 : 0] data;
wire valid;
wire [(66*10)-1 : 0] out;
reg [(66*10)-1 : 0] out_aux;
reg [ 65:... | 6.580864 |
module tb_parallel_crc_ccitt;
reg clk;
reg reset;
reg enable;
reg init;
reg [ 7:0] data_in;
wire [15:0] crc_out;
serial_crc_ccitt dut (
clk,
reset,
enable,
init,
data_in,
crc_out
);
initial begin
clk = 0;
data_in = 0;
i... | 6.580864 |
module tb_parall_interf ();
parameter setup_time = 2;
parameter hold_time = 2;
parameter data_time = 4;
parameter read_wait = 5;
parameter read_time = 2;
reg tb_sclk;
reg tb_rst_n;
reg tb_cs_n;
reg tb_rd_n;
reg tb_wr_n;
reg [7:0] tb_addr;
reg [15:0] wr_data;
wire [15:0] tb_data;
assign t... | 7.095777 |
module tb_parking_system;
// Inputs
reg clk;
reg reset_n;
reg sensor_entrance;
reg sensor_exit;
reg [1:0] password_1;
reg [1:0] password_2;
// Outputs
wire GREEN_LED;
wire RED_LED;
wire [6:0] HEX_1;
wire [6:0] HEX_2;
// Instantiate the Unit Under Test (UUT)
parking_system uut (
.cl... | 6.907139 |
module receives signals from a Test sequence
// which are sent to a data monitor.
`ifndef TB_PASSIVE
`define TB_PASSIVE
// scale time unit (value of one) / precision
`timescale 1ns / 100ps
// Includes verilog files
// Can be omitted and called from the testbench
`include "./src/Passive_b.v"
`include "./src/Passi... | 8.459918 |
module tb_upcntr;
// Inputs
reg clk, reset;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
upcntr uut (
.clk(clk),
.reset(reset),
.din(din),
.pattern_detect(pattern_detect)
);
initial begin
$dumpfile("tb_upcntr.vcd");
$dumpvars(0, tb_upcntr);
//... | 7.679218 |
module tb_pattern_gen (
input wire i_clk,
input wire i_res_n,
output wire [7:0] o_ptn
);
parameter LSB_POS = 10;
reg [31:0] r_cnt;
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_cnt <= 32'd0;
end else begin
r_cnt <= r_cnt + 32'd1;
end
en... | 6.502916 |
module tb_hmac;
localparam DataLength = 20;
// HMAC input
reg clk, rst_n, start, stop;
reg [1087:0] passward_in;
reg [127:0] salt_in;
reg [255:0] golden;
wire [255:0] key_out;
wire ready;
reg [1087:0] pw_mem[0:DataLength-1];
reg [127:0] salt_mem[0:DataLength-1];
reg [255:0] golden_mem[0:DataLen... | 6.66928 |
module tb_pc ();
reg clk;
reg rst;
reg [31:0] pcin;
wire [31:0] pc;
wire inst_ce;
pc mypc (
.clk(clk),
.rst(rst),
.pcin(pcin),
.pc(pc),
.inst_ce(inst_ce)
);
initial begin
clk = 0;
end
always #1 clk = ~clk;
initial begin
rst = 1;
pcin = 32'b0;
#5 rst... | 6.666841 |
module tb_pc_mux ();
localparam STEP = 10;
reg [31 : 0] pc;
reg [31 : 0] rs1;
reg [31 : 0] imm;
reg [`SEL_PC_WIDTH - 1 : 0] pc_sel;
reg taken;
reg stall;
wire [31 : 0] next_pc;
pc_mux pc_mux (
.pc(pc),
.rs1(rs1),
.imm(imm),
.pc_sel(pc_sel),
.taken(taken),
.stall(... | 7.105148 |
module tb ();
reg clk;
reg reset;
reg countSteps;
reg updateWeight;
reg dualUpdateWeights;
reg [7 : 0] A, B;
reg [2 : 0] Addr1, Addr2;
reg [7 : 0] Data1, Data2;
pedometer Ped (
.clk(clk),
.reset(reset),
.countSteps(countSteps),
.updateWeight(updateWeight),
.dualUpdateWe... | 7.195167 |
module: Permute
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Permute;
// Inputs
reg [263:0] state_in;
reg [15:0] IV_in, INV_IV_in;
reg clk;
reg rst;
reg en;
// Outputs... | 6.536171 |
module tb_pe_array_bd;
// Inputs
reg clk;
reg rst;
reg load;
reg din_v;
reg [`DATA_WIDTH*2-1:0] din;
wire dout_v;
wire [`DATA_WIDTH*2-1:0] dout;
// Instantiate the Unit Under Test (UUT)
pe_array_bd uut (
.clk(clk),
.rst(rst),
.load(load),
.din_v(din_v),
.din(din),
... | 6.5146 |
module tb_con ();
parameter L_RAM_SIZE = 4;
parameter CLK_PERIOD = 10;
reg aclk;
reg aresetn;
reg start;
reg [31:0] din;
wire done;
wire [L_RAM_SIZE:0] rdaddr;
//input data
reg [31:0] din_mem[2**(L_RAM_SIZE+1)-1:0];
integer i;
initial begin
aclk <= 0;
start <= 0;
aresetn <= 0;
... | 6.644733 |
module tb_pe_simd;
// Inputs
reg clk;
reg rst;
reg din_v;
reg [`DATA_WIDTH*2-1:0] din_pe;
reg inst_in_v;
reg [`INST_WIDTH-1:0] inst_in;
// Outputs
wire dout_v;
wire [`DATA_WIDTH*2-1:0] dout_pe;
// Instantiate the Unit Under Test (UUT)
pe_simd uut (
.clk(clk),
.rst(rst),
.din... | 6.562255 |
module tb_phase_ctrl ();
reg clk, rst_n;
reg send_signal;
wire gen_en, phase_ctrl;
wire ram_clk;
wire [7:0] ram_rd_data;
wire ram_en;
wire [7:0] ram_addr;
wire ram_we;
wire [7:0] ram_wr_data;
wire ram_rst;
initial begin
clk = 1;
rst_n = 0;
send_signal = 0;
#10 rst_n = 1;
send_s... | 6.505544 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity... | 7.554736 |
module TB_PID;
parameter WAITTIME = 10;
parameter CLKTIME = 500000000;
reg clk, reset;
wire ready;
reg signed [15:0] PV;
wire signed [15:0] result;
reg signed [15:0] Kp;
reg signed [15:0] Kd;
reg signed [15:0] Ki;
reg enable;
PID pid (
.clk(clk),
.reset(!reset),
.Kp(Kp),
... | 6.579252 |
module tb_pingpang ();
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
initial begin
... | 7.634423 |
module tb_PipelineCPU;
reg tb_i_clk;
reg tb_i_rst_n;
wire [31:0] tb_o_write_data;
parameter STEP = 10;
always #(STEP / 2) tb_i_clk = ~tb_i_clk; // clock assign
PipelineCPU abcdefg (
tb_i_clk,
tb_i_rst_n,
tb_o_write_data
);
initial begin
tb_i_clk = 1'b0;
tb_i_rst_n = 1'b0... | 7.326475 |
module: PipelineCPU_Hazards
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_PipelineCPU_Hazards;
// Inputs
reg i_clk;
reg i_rst_n;
// Outputs
wire [31:0] o_write_data;
//... | 7.765113 |
module tb_pipelined_mips_forwarding ();
reg clk;
reg nrst;
wire [ `WORD_WIDTH - 1:0] inst; // 32-bit instruction (from instruction memory)
wire [ `WORD_WIDTH - 1:0] proc_data_in; // data from memory to processor
wire [ `WORD_WIDTH - 1:0] proc_data_... | 6.611668 |
module tb_pipelined_mips_raw ();
reg clk;
reg nrst;
wire [ `WORD_WIDTH - 1:0] inst; // 32-bit instruction (from instruction memory)
wire [ `WORD_WIDTH - 1:0] proc_data_in; // data from memory to processor
wire [ `WORD_WIDTH - 1:0] proc_data_out; /... | 6.611668 |
module tb_pipelined_mips_stalling ();
reg clk;
reg nrst;
wire [ `WORD_WIDTH - 1:0] inst; // 32-bit instruction (from instruction memory)
wire [ `WORD_WIDTH - 1:0] proc_data_in; // data from memory to processor
wire [ `WORD_WIDTH - 1:0] proc_data_ou... | 6.611668 |
module tb_pipeline_insert_ff ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_pipeline_insert_ff.vcd");
$dumpvars(0, tb_pipeline_insert_ff);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
... | 7.761626 |
module : tb_pipeline_register
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* i... | 7.497975 |
module piso_left_cyclic_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg LOAD;
reg LSHIFT;
reg [W-1:0] IN[SW-1:0];
wire [W-1:0] OUT;
integer i = 0;
piso_left_cyclic_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) piso_l (
.RST(RST),
.CLK(CLK),
.LOAD(LOAD),
.LSHIF... | 7.03152 |
module tb_piso_macro;
// Inputs
reg clk;
reg rst;
reg load;
reg ce;
reg [`DATA_WIDTH*2-1:0] p_in;
// Outputs
wire s_out;
// Instantiate the Unit Under Test (UUT)
piso_macro uut (
.clk(clk),
.rst(rst),
.load(load),
.ce(ce),
.p_in(p_in),
.s_out(s_out)
);
par... | 7.458659 |
module tb_piso_new;
// Inputs
reg clk;
reg load;
reg p_in_v;
reg [`PE_NUM*`DATA_WIDTH*2-1:0] p_in;
// Outputs
wire s_out_v;
wire [`DATA_WIDTH*2-1:0] s_out;
// Instantiate the Unit Under Test (UUT)
piso_new uut (
.clk(clk),
.load(load),
.p_in_v(p_in_v),
.p_in(p_in),
.... | 7.729949 |
module testbench;
localparam RCLK_PERIOD = 4000;
localparam TCLK_PERIOD = 4000;
localparam RST_TIME = 10000;
reg rx_clk;
reg clk;
always begin
rx_clk = 0;
forever #RCLK_PERIOD rx_clk = ~rx_clk;
end
always begin
clk = 0;
forever #TCLK_PERIOD clk = ~clk;
end
wire tx_clk;
wire [15:0... | 7.956616 |
module tb_pla;
reg clk;
reg rst_n;
reg [2:0] P;
reg [15:0] ADDR;
reg [14:0] VADDR;
reg AEC;
reg BA;
reg GAME_n;
reg EXTROM_n;
reg RW;
integer i;
integer j;
pla pla_e (
.A(ADDR),
._LORAM(P[0]),
._HIRAM(P[1]),
._CHAREN(P[2]),
._CAS(1'b0),
.VA12(VADDR[12]),
... | 6.542614 |
module: pLayer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_pLayer;
// Inputs
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
// Outputs
wire [263:0] state_out;
wire... | 6.661257 |
module: pLayer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_pLayer2;
// Inputs
reg [263:0] state_in;
reg [31:0] index;
reg clk;
reg rst;
reg enable;
// Outputs
wire [... | 6.661257 |
module top ();
localparam ITERATIONS = 100000;
reg clk;
reg reset;
always #`CLK_P clk <= ~clk;
wire [15:0] random;
rng RNG (
.clk (clk),
.reset(reset),
.rng_o(random)
);
////////////////////////////////////////////////////////////////////////////////
// DUTs
reg [15+1:0] a... | 7.239517 |
module tb_pll ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire clk_mul_2;
wire clk_div_2;
wire clk_phase_90;
... | 7.447949 |
module DFIFO #(
parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32
) // fifo width in bit
(
input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wir... | 7.141186 |
module tb_pooling;
parameter N = 512;
parameter P = N * N;
parameter L = P * 3;
parameter N2 = N / 2;
parameter P2 = N2 * N2;
parameter L2 = P2 * 3;
integer input_file, output_file;
integer i, j, c;
integer status;
integer count;
reg [7:0] tmp;
reg [3:0] din[0:L-1];
reg [3:0] dout[0:L-1]... | 6.737786 |
module tb_pos_level_latch;
// Inputs
reg clk, din;
// Outputs
wire dout;
// Instantiate the Unit Under Test (UUT)
pos_level_latch uut (
.dout(dout),
.clk (clk),
.din (din)
);
initial begin
$dumpfile("tb_pos_level_latch.vcd");
$dumpvars(0, tb_pos_level_latch);
// Initialize... | 7.414157 |
module tb_ppfifo ();
//local parameters
localparam DATA_WIDTH = 32; //32-bit data
localparam ADDR_WIDTH = 4; //2 ** 4 = 16 positions
//registes/wires
reg clk = 0;
reg rd_clk = 0;
reg rst = 0;
//write side
wire [ 1:0] write_r... | 7.567386 |
module tb_pram_adr_cnt ();
parameter data_wl = 16;
parameter adr_wl = 12;
reg [adr_wl - 1 : 0] adr_in;
reg adr_ld_in;
reg inc_in;
reg init_mode_in;
reg init_ack_in;
wire [data_wl - 1 : 0] data_in1;
wire [data_wl - 1 : 0] data_in2;
reg clk;
reg a_reset_l;
wire [adr_wl - 1 : 0] adr_out;
wir... | 7.319754 |
module tb ();
reg clk, reset;
wire [28:0] pi_out;
real pi_real;
initial begin
reset = 1'b0;
clk = 1'b0;
#10 reset = 1'b1;
#10 reset = 1'b0;
while (1) #10 clk = ~clk;
end
initial begin
$dumpfile("new.vcd");
$dumpvars();
#10000000 $display("pi = %f", pi_real);
$fin... | 7.195167 |
module tb_preescaller ();
reg clock;
reg enable;
wire slow_clock;
always #1 clock = ~clock;
preescaller tb_preescaller_DUT (
.clock(clock),
.enable(enable),
.slow_clock(slow_clock)
);
initial begin
clock = 0;
enable = 1;
#100 $display("Simulation for Preescaller Fini... | 7.595127 |
module tb_prefix;
reg [7:0] t_a, t_b;
reg t_cin;
wire [7:0] t_S;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, tb_prefix);
end
prefixAdd pra (
.a (t_a),
.b (t_b),
.cin(t_cin),
.S (t_S)
);
initial begin
t_a[7:0] = 8'b00000000; //0
t_b[7:0] = 8'b01000001; /... | 6.766041 |
module: PrimeDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_PrimeDetector;
// Inputs
reg [3:0] N;
//Outputs
wire F;
// Instantiate the Unit Un... | 6.844203 |
module tb_toplevel_primerLoopback;
localparam NMODULES = 2;
localparam LEN_DATA_BLOCK = 64;
localparam LEN_CTRL_BLOCK = 8;
reg tb_clock, tb_reset, tb_enable_frameGenerator, tb_enable_frameChecker;
reg [NMODULES-1 : 0] tb_enable_tx, tb_enable_rx;
wire [LEN_DATA_BLOCK-1 : 0] tb_data_out;
wire [LEN_CTRL_... | 7.119476 |
module tb_proc ();
reg clk, rst, interrupt;
main A (
clk,
rst,
interrupt
);
always #5 clk = ~clk;
initial begin
$monitor($time, " r0=%d, r1=%d, r3=%d r4=%d mem16=%d mem17=%d", A.regs.reg_num[0],
A.regs.reg_num[1], A.regs.reg_num[3], A.regs.reg_num[4], A.D_mem.d_mem[16],
... | 6.732844 |
module: Procesador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Procesador;
// Inputs
reg clk;
reg [7:0] sw;
// Outputs
wire [7:0] leds;
// Instantiate the Unit Under ... | 7.091721 |
module tb_processor ();
// inputs
reg clk;
reg rst;
// outputs
wire [31:0] tb_Result;
processor processor_isnt (
.clk(clk),
.reset(rst),
.Result(tb_Result)
);
always begin
#10;
clk = ~clk;
end
initial begin
clk = 0;
@(posedge clk);
rst = 1;
@(posedge cl... | 6.782286 |
module uartprog #(
parameter FILENAME = "program.hex"
) (
input mprj_ready,
output reg r_Rx_Serial // used by task UART_WRITE_BYTE
);
reg r_Clock = 0;
parameter c_BIT_PERIOD = 8681; // used by task UART_WRITE_BYTE
parameter c_CLOCK_PERIOD_NS = 100;
reg [7:0] INSTR[16384-1:0];
integer instr_cou... | 6.509248 |
module tb_ps2_state_controller ();
reg clk;
reg data;
reg parity_valid;
wire shift_en;
wire write_en;
wire reset;
wire frame_valid;
PS2InterfaceStateController control (
.clk(clk),
.data(data),
.parity_valid(parity_valid),
.shift_en(shift_en),
.write_en(write_en),
... | 6.647612 |
module pulse_tb ();
// Signal Declarations
reg clock, reset, enable; // Inputs
reg [5:0] divideby;
wire go; // Outputs
wire [9:0] LEDR;
//wire [5:0] count;
// Unit Under Test Instantiation
pulse UUT (
.clock(clock),
.reset(reset),
.enable(enable),
.divideby(divideby),
.... | 8.562464 |
module tb_pulse_sync_toggle ();
reg clock_a;
reg clock_b;
reg async_rst_n;
reg pls_a;
wire pls_b;
pulse_sync_toggle pulse_sync_toggle_i (
.clock_a (clock_a),
.clock_b (clock_b),
.async_rst_n(async_rst_n),
.pls_a (pls_a),
.pls_b (pls_b)
);
always begi... | 7.151773 |
module tb_pwm;
// Parameters
parameter CLOCK_PERIOD = 10; // Clock period in ns
parameter SIM_DURATION = 1000; // Simulation duration in ns
// Inputs
reg clk;
reg rst;
reg [6:0] duty_cycle; // Using 7 bits to represent duty cycle from 0 to 100 (0 to 100%)
reg [15:0] frequency; // Using 16 bits to ... | 7.083046 |
module tb_PWM_Generator_Verilog;
// Inputs
reg clk;
reg reset;
// Outputs
wire [35:0] PWM_OUT;
// Instantiate the PWM Generator with variable duty cycle in Verilog
robot_arm_controller PWM_Generator_Unit (
clk,
reset,
PWM_OUT
);
//
initial begin
clk = 0;
forever #100 clk = ... | 6.704379 |
module tb_decade_counter ();
wire [3:0] q;
reg clk = 0;
integer i;
decade_counter UUT (
q,
clk
);
initial begin
for (i = 0; i < 100; i = i + 1) #10;
end
always @(i) clk = ~clk;
initial begin
#7;
$monitor("%d", q);
end
endmodule
| 6.875652 |
module: random
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_QAM;
// Inputs
reg clk;
reg rst;
// Outputs
//wire [27:0] shift_reg;
//System Freqency
wire en_clk;
main_c... | 7.080575 |
module clk_wiz_0 (
input clk48,
output clk20,
input reset,
output locked
);
// just reflect the input to the output and set the input to be 20MHz in the testbench
assign clk20 = clk48;
assign locked = 1;
endmodule
| 6.750754 |
module tb_qupdater;
reg [15:0] old_Q;
reg [15:0] max_Q;
reg [ 3:0] gamma;
reg [15:0] rt;
reg [ 3:0] alpha;
wire [15:0] new_Q;
QUpdater q_updater (
old_Q,
max_Q,
gamma,
alpha,
rt,
new_Q
);
initial begin
old_Q = 16'b0000000000000001;
max_Q = 16'b000000... | 7.710726 |
module tb_Q_column3_pre;
reg enable, clk, reset_n, accept_in;
wire accept_out, ready_out;
//
reg [63:0] H_col3, Q_col1, Q_col2;
wire [63:0] Q_col3_pre;
Q_column3_pre uut (
enable,
clk,
reset_n,
accept_in,
accept_out,
ready_out,
H_col3,
Q_col1,
Q_col2,
... | 6.842615 |
module R5FP_sqrt_seq_wrap #(
parameter EXP_W = 5,
parameter SIG_W = 6
) (
input [EXP_W+SIG_W:0] a,
input [2:0] rnd,
output [7:0] status,
output [EXP_W+SIG_W:0] z,
input clk,
reset,
strobe,
output ready,
complete
);
wire [EXP_W+SIG_W+1:0] ax, zx;
R5FP_exp_incr #(
.... | 6.507974 |
module tb_ram;
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 8;
reg [DATA_WIDTH-1:0] data;
reg [ADDR_WIDTH-1:0] addr;
reg we, clk;
wire [DATA_WIDTH-1:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
ram UUT (
.clk(clk),
.we(we),
.addr(... | 7.147927 |
module: ramtest
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ramtest;
// Inputs
reg clk;
reg rst;
// Outputs
wire [20:0] sram_a;
wire sram_we_n;
wire test_in_progress;... | 6.773392 |
module ram512kb (
input wire [20:0] a,
inout wire [7:0] d,
input wire we_n
);
reg [7:0] ram[0:524287];
assign #15 d = (we_n == 1'b1) ? ram[a[18:0]] : 8'hZZ;
always @* begin
if (we_n == 1'b0) ram[a[18:0]] = #15 d;
end
endmodule
| 7.071599 |
module tb_RAM_0 ();
//-----------定义接口---------//
reg sclk;
reg [9:0] data; //输入的数据
reg [11:0] cnt; //计数,当cnt=12'd1023时写数据使能，其他读数据使能
reg [9:0] addr_we; //写地址
reg [11:0] addr_rd; //读地址
reg data_tvalid; //数据有效信号
//----------设置时钟信号----------//
initial sclk = 0;
always #5 sclk = ~sclk; //100M
/... | 6.579001 |
module tb_ram_controller;
// Inputs
reg clk;
reg sw0;
// Outputs
wire [7:0] seg;
wire [3:0] an;
wire [7:0] Led;
wire [25:0] ADDR;
wire MEMnOE;
wire MEMnWR;
wire MEMnAdv;
wire MEMWait;
wire MEMClk;
wire RAMnCS;
wire RAMCRE;
wire RAMnUB;
wire RAMnLB;
// Bidirs
wire [15:0] DATA;
... | 6.509288 |
module tb_ram_sp;
parameter DWIDTH = 8;
parameter AWIDTH = 12;
parameter CONTENT = "./memory.txt";
reg clock;
reg wren;
reg [AWIDTH-1:0] address;
reg [DWIDTH-1:0] data;
wire [DWIDTH-1:0] q;
ram_sp #(
.DWIDTH (8),
.AWIDTH (12),
.CONTENT("./ram_content.... | 6.830129 |
module test packet cua anh chang lang tu tai hoa
module tb_load_2;
parameter NUM_OUTPUT = 250; // Số spike bắn ra
parameter NUM_PICTURE = 100; // Số ảnh test
parameter NUM_PACKET = 13910; // số lượng input packet trong file
reg clk, reset_n, sys_rst, csr_rst;
wire tick, input_buffer_empty;
wire [29:0] packet_in;
wire... | 6.714146 |
module tb_random ();
localparam CLK_PER = 20; // 50 MHz
reg tb_clk;
reg reset_n;
reg [31:0] tb_seed;
wire [ 7:0] data;
initial begin
tb_clk = 1'b0;
forever begin
#(CLK_PER) tb_clk = ~tb_clk;
#(CLK_PER) tb_clk = ~tb_clk;
end
end
initial begin
reset_n ... | 6.815512 |
module tb_randomNumber1;
//Input
reg clk;
//Outputs
wire [3:0] n;
wire [2:0] Q;
integer i;
//Instancia a unidade a ser testada
randomNumber1 uut (
.clk(clk),
.Q (Q),
.n (n)
);
//Pulso do clock
always begin
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end
//Encerr... | 6.834485 |
module tb ();
reg CLK;
reg RST_n;
reg [3:0] seed;
wire [3:0] random_gen;
reg load;
parameter DUTY = 1;
always #DUTY CLK = ~CLK;
initial begin
CLK = 1;
RST_n = 0;
load = 0;
#10 RST_n = 1;
load = 1;
seed = 4'b0110;
#2 load = 0;
#30 load = 1;
... | 7.002324 |
module tb_rca;
// TB_SIGNALS
reg clk, reset;
reg [7:0] num1;
reg [7:0] num2;
wire [8:0] sum_out;
// Instantiate the Unit Under Test (UUT)
rca uut (
.num1(num1),
.num2(num2),
.sum (sum_out)
);
initial begin
$dumpfile("tb_rca.vcd");
$dumpvars(0, tb_rca);
// Initialize In... | 7.160656 |
module tb_rca_36b (); //tb module declaration
integer i; //Declare integer variables to automatically transfer values,
//through mathematical operations
reg [35:0] A; //Each input must be declared as a register type,
reg [35:0] B; //Only then can a certain value be output until the next sign... | 8.576883 |
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