code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module vsdmemsoc_tb;
// Inputs
reg CLK, reset;
reg init_en;
reg [7:0] init_addr;
reg [31:0] init_data;
// Outputs
wire [9:0] OUT;
// Other Signals
integer i;
wire [31:0] ROM =
i == 32'h0 ? {12'b1, 5'd0, 3'b000, 5'd9, 7'b0010011} :
i == 32'h1 ? {12'b101011, 5'd0, 3'b000, 5'd10, 7'b0010011} :
... | 7.032941 |
module testbench05;
reg [3:0] A, B;
reg Select;
wire [3:0] Sum;
wire Carry, Overflow;
_4bit_Adder_Sub_gate mod (
Sum,
Carry,
Overflow,
A,
B,
Select
);
initial begin
$monitor($time, " A=%4b, B=%4b, Select=%b, Carry=%b, Sum=%4b, Overflow=%b.", A, B, Select,
... | 6.538107 |
module testbench06;
reg [3:0] A, B;
reg Select;
wire [3:0] Sum;
wire Carry;
_4bit_Adder_Sub_df mod (
Sum,
Carry,
A,
B,
Select
);
initial begin
$monitor($time, " A=%4b, B=%4b, Select=%b, Carry=%b, Sum=%4b.", A, B, Select, Carry, Sum);
#0 A = 4'b0000;
B = 4'b0000;
... | 6.677562 |
module testbench11;
`include "params.v"
parameter DIM = WIDTH * HEIGHT;
parameter t = 10;
reg clk, reset;
reg [ 23:0] RGB;
wire [ 7:0] L;
reg [ 23:0] rom [0:DIM-1];
// Output ram
reg [ 7:0] out_ram[0:DIM-1];
wire [ 7:0] din;
reg [$clo... | 7.353884 |
module counter_tb ();
// Make a register for the clock you're going to generate.
reg clk;
// Make a wire for the output of the module you're testbenching for.
wire [31:0] count;
// Instantiate the module we're testbenching.
counter tb (
.clk (clk),
.count(count)
);
// Initialize the clock t... | 7.107233 |
module encoderTestBench;
reg [3:0] D;
wire A, B, V;
encoderGates4x1 e1 (
D,
A,
B,
V
);
integer i;
initial begin
for (i = 0; i < 16; i = i + 1) begin
D = i;
#50;
end
end
endmodule
| 6.713618 |
module clk_div_tb ();
// Make a register for the clock you're going to generate and the reset.
reg clk, rst;
// Generally, you make registers for inputs because you usually want to
// make procedural changes to them to see how the output is affected. In
// this case, we could get away with using wires if we ... | 6.724979 |
module. To see the results, run the simulation for a
// little while longer until the freq_counter's counter has reached the
// localparam max.
module freq_count_tb();
wire [19:0] freq;
reg clk, in, enable;
wire done;
initial begin
clk = 0;
in = 0;
enable = 1;
... | 8.236286 |
module testbench_AS;
reg [3:0] A, B;
reg Select;
wire [3:0] Sum;
wire Carry, Overflow;
ADDSUB mod (
Sum,
Carry,
Overflow,
A,
B,
Select
);
initial begin
$monitor($time, " A=%4b, B=%4b, Select=%b, Carry=%b, Sum=%4b, Overflow=%b.", A, B, Select,
Carry, Sum... | 6.516317 |
module tbCompressor ();
reg x1, x2, x3, x4, Cin;
wire Sum, Carry, Cout;
compressor4to2 inst (
x1,
x2,
x3,
x4,
Cin,
Sum,
Carry,
Cout
);
initial begin
{x2, x3, x4, Cin} = 4'b0000;
x1 = 1'b1;
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin ... | 6.65134 |
module Testbench;
reg in;
reg [1:0] sel;
wire [3:0] f;
integer i;
defparam demux2x4.sel_width = 2;
Demux demux2x4 (
in,
sel,
f
);
initial begin
$dumpfile("demux.vcd");
$dumpvars(0, Testbench);
in = 1;
for (i = 0; i < 4; i = i + 1) begin
sel = i;
#1;
e... | 7.128264 |
module eightToOneMUXTest;
wire out_t;
reg [0:7] in_t;
reg sl1_t, sl2_t, sl3_t;
eightToOneMUX loki (
out_t,
in_t,
sl1_t,
sl2_t,
sl3_t
);
initial begin
sl1_t <= 0;
sl2_t <= 0;
sl3_t <= 0;
in_t <= 8'b11010101;
#1 $display("input = %b ", in_t, "Output = %b ... | 7.166107 |
module m21Test;
reg D0_t, D1_t, s_t;
wire y_t;
m21 thor (
D0_t,
D1_t,
s_t,
y_t
);
initial begin
D0_t <= 0;
D1_t <= 1;
s_t <= 0;
#1 $display("Input = %b ", D0_t, D1_t, "Output = %b ", y_t);
end
endmodule
| 6.669187 |
module mainComparatorTest;
reg [0:7] in1_t, in2_t;
wire CO_t;
mainComparator Odin (
in1_t,
in2_t,
CO_t
);
initial begin
in1_t <= 8'b00110010;
in2_t <= 8'b11100110;
#1 $display("Input1 = %b ", in1_t, "Input2 = %b ", in2_t, "CO = %b ", CO_t);
end
endmodule
| 6.859464 |
module TestBenchForEightToThirteen (
clk_AD,
sysclk,
clk16,
datain,
dataout,
pcmlinear,
rpcmlinear,
logPCM,
rLogPCM,
fskdata
);
output reg [7:0] datain;
output [7:0] dataout;
output wire [7:0] logPCM, rLogPCM;
wire [8:0] checked, rfskdata;
output reg sysclk, clk16;
... | 6.557231 |
module testbenchReg;
reg clk = 0;
reg rst = 0;
reg l = 0;
reg [15:0] in = 16'b1111111111111111;
wire [15:0] out;
register reg_0 (
clk,
rst,
l,
in,
out
);
initial begin
$dumpvars;
#1 clk <= 1;
#5 clk <= 0;
l <= 1;
#2 clk <= 1;
#2 clk <= 0;
... | 7.075364 |
module testbench;
wire CLOCK, RESET, PUSHDATOENTRADA, POPffg/*Viene del probador*/, SET_INIT/*Viene del probador*/, POPDATOCF;
wire [1:0] IDINPUT, SEL, WEIGHT;
wire [ 3:0] DATO_IN;
wire [31:0] TABLE;
wire [6:0] TL_IN, TH_IN;
wire IDLE;
wire [3:0] PAUSE_STB, CONTINUE_STB, ERROR_FULL;
wire [3:0] DATO_OUT... | 7.015571 |
modules, 16 bit crc *
* ------------------------------------------------ */
`include "Sources/crc.v"
`include "Common/parallel_to_serial.v"
module tb(); // CRC-16/CCITT-FALSE
localparam CRC_SIZE = 16, //Size of CRC value, all following parameters should have this size
INITAL_VAL = 16'hFFF... | 8.564951 |
module testbench;
reg [15:0] in_a, in_b;
reg CLK;
reg reset;
reg [15:0] correct_ans;
wire [15:0] s;
reg [5:0] counter;
reg [5:0] ct;
reg error;
reg cin;
reg [4:0] successful_count;
wire cout;
initial cin = 0;
initial ct = 0;
initial in_a = 0;
initial in_b = 0;
initial successful_count... | 7.015571 |
module testbench_card_write; //testbench y probador de DAT
reg [3:0] card_in = 0;
reg [31:0] buffer_in = 0;
wire [31:0] buffer_out;
wire [3:0] card_out;
reg clock;
reg new_trans;
reg enable_write, enable_read, Clear_in, reset;
parameter n = 32;
parameter vector_width = 10; //reg_vector has inputs w... | 7.061901 |
modules, 32 bit crc *
* ------------------------------------------------ */
`include "Sources/crc.v"
`include "Common/parallel_to_serial.v"
module tb(); // CRC-32/POSIX
localparam CRC_SIZE = 32, //Size of CRC value, all following parameters should have this size
INITAL_VAL = 32'h00000000,... | 9.179462 |
module tb ();
reg [3:0]
zero,
one,
two,
three,
four,
five,
six,
seven,
eight,
nine,
ten,
eleven,
twelve,
thirtn,
fourtn,
fiftn,
dummy;
wire [8:0] v1_1, v1_2, v1_3, v1_4, fbc_1, fbc_2, fbc_3, fbc_4, v1_5, fbc_5, fbc... | 7.002324 |
module testbench;
reg [63:0] in_a, in_b;
reg CLK;
reg reset;
reg [64:0] correct_ans;
wire [63:0] sum;
reg [5:0] counter;
reg [5:0] ct;
reg error;
reg cin;
wire cout;
initial cin = 0;
initial ct = 0;
initial in_a = 0;
initial in_b = 0;
cla_64bit DDLab6 (
in_a,
in_b,
cin... | 7.015571 |
module tb_comparator8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
comparator8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
A = 8'b00000001;
B = 8'b... | 6.843472 |
module usr_testbench;
reg [7:0] inp;
reg clk;
reg clr;
reg [1:0] op;
reg sinr;
reg sinl;
wire [7:0] pout;
wire soutl;
wire soutr;
eightbit_usr usr (
clk,
sinr,
sinl,
clr,
op,
inp,
pout,
soutr,
soutl
);
always #50 clk = ~clk;
initial begi... | 6.67584 |
module testbench_add32 ();
reg [31:0] A;
reg [31:0] B;
wire Overflow; //溢出判定
wire [31:0] result; //输出结果
reg isSub; //运算判定
reg isSign;
Add32 testadd32 (
Overflow,
result,
A,
B,
isSub,
isSign
);
initial begin
isSub = 1'b0;
isSign = 1'b0;
A = 100;
B... | 7.504399 |
module testbench_adder_32bit;
reg [31:0] num1, num2;
wire [31:0] sum;
wire cfinal;
wire cin;
assign cin = 0;
adder_32bit add1 (
cfinal,
sum,
num1,
num2,
cin
);
initial
$monitor(
, $time, "sum=%b, cfinal = %b, num1=%b, num2=%b, cin = %b", sum, cfinal, num1, num... | 7.504399 |
module testbench_adder_8bit;
reg [7:0] num1, num2;
wire [7:0] sum;
wire cfinal;
wire cin;
assign cin = 0;
ADDER_8bit fl (
cfinal,
sum,
num1,
num2,
cin
);
initial
$monitor(
, $time, "sum=%b, cfinal = %b, num1=%b, num2=%b, cin = %b", sum, cfinal, num1, num2, cin... | 7.504399 |
module: ADSR_mngt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_ADSR;
// Inputs
reg clk;
reg rst;
reg new_sample;
reg new_note_pulse;
reg release_note_pulse;
reg ... | 6.550976 |
module testbench_all (
output wire completed
);
wire [5:0] completion;
assign completed = &completion;
testbench_arith p_arith (completion[0]);
testbench_cpu p_cpu (completion[1]);
testbench_extcall p_extcall (completion[2]);
testbench_ram p_ram (completion[3]);
testbench_top p_top (completion[4]);
... | 7.451523 |
module TestBench ();
reg [1:0] x;
wire y;
and_behavioral_level behavioral_level_module (
y,
x
);
reg [1:0] index;
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, y, x);
index = 0;
repeat (6) begin
x = index;
index = index + 1;
#20;
end
$... | 7.747207 |
module testbench_tricomp0_sync (
output reg completed
);
`include "../utils.h"
integer ii;
reg [17:0] in;
wire p;
wire z;
wire n;
wire [2:0] pzn = {p, z, n};
tricomp0_sync comp0 (
.in (in),
.pos (p),
.zero(z),
.neg (n)
);
initial begin
completed = 0;
for (ii... | 7.180779 |
module testbench_trisfcomp_sync (
output reg completed
);
`include "../utils.h"
integer ii;
reg [17:0] in;
wire signed [1:0] sf;
trisfcomp_sync sfcomp (
.in(in),
.sf(sf)
);
initial begin
completed = 0;
for (ii = -9841; ii <= 9841; ii = ii + 1) begin
in = util_int_to_tryt... | 7.180779 |
module testbench_tricomp_sync (
output reg completed
);
`include "../utils.h"
integer ii;
integer ij;
reg [17:0] lhs;
reg neg_rhs;
reg [17:0] rhs;
wire gt;
wire eq;
wire lt;
wire [2:0] gel = {gt, eq, lt};
tricomp_sync comp (
.lhs(lhs),
.neg_rhs(neg_rhs),
.rhs(rhs),
.... | 7.180779 |
module testbench_triinc_sync (
output reg completed
);
`include "../utils.h"
integer ii;
integer ires;
reg [17:0] inc_in;
wire [17:0] inc_res;
wire signed [1:0] inc_cf;
wire signed [1:0] inc_sf;
triinc_sync inc (
.in(inc_in),
.res(inc_res),
.cf (inc_cf),
.sf (inc_sf)
);
... | 7.180779 |
module testbench_tridec_sync (
output reg completed
);
`include "../utils.h"
integer ii;
integer ires;
reg [17:0] dec_in;
wire [17:0] dec_res;
wire signed [1:0] dec_cf;
wire signed [1:0] dec_sf;
tridec_sync dec (
.in(dec_in),
.res(dec_res),
.cf (dec_cf),
.sf (dec_sf)
);
... | 7.180779 |
module testbench_triaddtri_sync (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ils;
integer ilhsi;
integer ilhs;
integer ims;
integer imhsi;
integer imhs;
integer irs;
integer irhsi;
integer irhs;
integer ires;
reg lsub;
reg [17:0] lhs;
reg msub;
reg [... | 7.180779 |
module testbench_triaddtri (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ils;
integer ilhsi;
integer ilhs;
integer ims;
integer imhsi;
integer imhs;
integer irs;
integer irhsi;
integer irhs;
integer ires;
reg clk;
initial clk = 0;
always #5 if (!complet... | 7.180779 |
module testbench_trimul (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ilhsi;
integer ilhs;
integer irhsi;
integer irhs;
integer ires;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
reg enable;
reg [17:0] lhs;
reg [17:0] rhs;
w... | 7.180779 |
module testbench_trishl_sync (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ilhsi;
integer ilhs;
integer irs;
integer irhs;
reg [17:0] exp_res;
reg [17:0] lhs;
reg neg_rhs;
reg [5:0] rhs;
wire [17:0] res;
wire signed [1:0] cf;
wire signed [1:0] sf;
trishl... | 7.180779 |
module testbench_arith (
output wire completed
);
wire [10:0] completion;
assign completed = &completion;
testbench_tricomp0_sync p_tricomp0_sync (completion[0]);
testbench_trisfcomp_sync p_trisfcomp_sync (completion[1]);
testbench_tricomp_sync p_tricomp_sync (completion[2]);
testbench_triadd_sync p_tr... | 7.212422 |
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EW = 8;
parameter SW = 26;
//inputs
reg clk;
reg rst;
reg ctrl_a_i;
reg [EW-1:0] Shift_Value_0_i;
reg [EW-1:0] Shift_Value_1_i;
reg [SW-1:0] Shift_Data_0_i;
reg [SW-1:0] Shift_Data_1_i;
reg FSM_left_right_i;
reg FSM_select_C... | 7.839439 |
module bcd_tb ();
reg [3:0] tb_A;
reg [3:0] tb_B;
reg tb_cin;
wire [3:0] tb_sum;
wire tb_cout;
reg [7:0] tb_E = 8'b00000000;
wire [2:0] tb_F;
reg clk;
initial clk = 0;
always #10 clk = ~clk;
reg [31:0] tb_mem[0:13];
lab6_2circuits bcd_ins (
.A(tb_A),
.B(tb_B),
.cin(tb_cin),
... | 6.696849 |
module TestBench_BF_Dec;
wire [7:0] D;
reg [3:0] I;
reg [1:0] E;
BF_decoder_3_bit D0 (
D,
I,
E[0]
);
initial begin
for (E = 2'b00; E <= 2'b01; E = E + 2'b01) for (I = 4'b0000; I <= 4'b0111; I = I + 4'b0001) #50;
end
initial $monitor($time, "\t I=%b D=%b E=%b", I, D, E);
end... | 7.106562 |
module testbench_bintogray ();
parameter CLK_PERIOD = 10;
reg clk;
reg rst;
reg [3:0] data;
wire [3:0] gray_data;
// Ӳģ
bin_to_Gray bin_to_Gray_test (
.clk (clk),
.rst (rst),
.data (data),
.gray_data(gray_data)
);
// ʼʱӺλ
initial begin
cl... | 6.718156 |
module TB_booth;
parameter multiplier_width = 8;
parameter multiplicand_width = 8;
wire [multiplicand_width-1 : 0] AC;
wire [ multiplier_width-1 : 0] QR;
reg [multiplicand_width-1 : 0] multiplicand;
reg [ multiplier_width-1 : 0] multiplier;
booth_algo booth (
AC,
QR,
multiplicand,
... | 6.612465 |
module TestBench_brush ();
parameter SLOWNESS = 8, //number of position of counter clock divider
RESOLUTION_H = 640, RESOLUTION_V = 480, HPOS_WIDTH = 0, //coordinate wires width
VPOS_WIDTH=0,
V_TOP = 10,
V_SYNC = 2,
V_BOTTOM =33,
H_FRONT = 16,
H_SYNC = 96,
H_BACK = 48,
BRUSH_SIZE=10,
... | 6.842661 |
module TestBench_BtoG;
wire [3:0] Y;
reg [4:0] I;
Bin2Gray B (
Y[3:0],
I[3:0]
);
initial begin
for (I = 5'b00000; I <= 5'b01111; I = I + 5'b00001) #50;
end
initial $monitor($time, "\t I = %b, Y = %b", I, Y);
endmodule
| 6.695215 |
module testbench_carry_select_adder ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
carry_select_adder uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
C... | 7.061901 |
module testbench_cbpa ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
cbpa uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum... | 6.888891 |
module tb_channel;
logic [0:0] clk;
logic [1:0] count;
logic [0:0] reset;
logic [0:0] recv__en;
CGRAData_32_1_1 recv__msg;
logic [0:0] recv__rdy;
logic [0:0] send__en;
CGRAData_32_1_1 send__msg;
logic [0:0] send__rdy;
ChannelRTL__DataType_CGRAData_32_1_1__latency_1 dut (
.clk(clk),
.co... | 6.532607 |
module testbench_CIA ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
CarryIncrementAdder uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#1... | 6.771059 |
module TestBench_CLA;
wire [3:0] S;
wire C;
reg [4:0] A, B;
reg [1:0] K;
carryLookaheadAdder_4_bit CLA (
S,
C,
A[3:0],
B[3:0],
K[0]
);
initial begin
for (A = 5'b00000; A <= 5'b01111; A = A + 5'b00001)
for (B = 5'b00000; B <= 5'b01111; B = B + 5'b00001)
for (K =... | 6.648325 |
module testbench_CLA_adder ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
CLA_adder uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
... | 6.707837 |
module: Clock_screen_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestBench_Clock_screen_top;
// Inputs
reg clk;
reg reset;
// Outputs
wire hsync;
wire vsync;
wire [1... | 7.868932 |
module testbench_color;
parameter size = 110592, rows = 192, cols = 192;
color #(
.infile("rahul_in_hex.hex"),
.outfile("rahul_out_3_hex.hex"),
.size(size),
.rows(rows),
.cols(cols),
.ksize(3)
) k3 (); //instantiating module color which will give output hex file for kernel s... | 8.065258 |
module Testbench;
reg reset, clk;
wire rw;
wire [15:0] data_proc, data_mem;
wire [15:0] mem_addr;
Processor mARC ( //marcee
data_mem, //data or instructions coming from the main memory
mem_addr, //Data comming from the bus A of the datapath
data_proc, //Data comming from the bus B of ... | 7.339781 |
module: Contol_RTC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_contro_RTC;
// Inputs
reg clk;
reg reset;
reg sw0;
reg sw1;
reg sw2;
reg enUP;
reg enDOWN;
reg ... | 8.101144 |
module testbench_first_instrs (
output reg completed
);
`include "../utils.h"
integer ii;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
tricpu #(
.P_LOGLEVEL(-1)
) cpu (
.clk(clk),
.rst(rst),
.stepping(1'b0),
.s_axis_tvalid(1'b0),
... | 6.516488 |
module testbench_cpu_calls_hypercall_log (
output reg completed
);
`include "../utils.h"
integer ii;
integer msg[0:32] = "";
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
wire [31:0] m_axis_tdata;
wire m_axis_tlast;
reg m_axis_tready;
wire m_axis_tvalid;
tricpu ... | 7.776549 |
module testbench_inf_loop (
output reg completed
);
`include "../utils.h"
integer ii;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
tricpu #(
.BIN_FILENAME("zzz_test_inf_loop.bin")
) cpu (
.clk(clk),
.rst(rst),
.stepping(1'b0),
.s_axis_tv... | 6.547391 |
module testbench_cpu (
output wire completed
);
wire [2:0] completion;
assign completed = &completion;
testbench_first_instrs p_first_instrs (completion[0]);
testbench_cpu_calls_hypercall_log p_cpu_calls_hypercall_log (completion[1]);
testbench_inf_loop p_inf_loop (completion[2]);
initial begin
#1... | 7.776549 |
module tb_crossbar;
logic [0:0] clk;
logic [0:0] reset;
logic [0:0] recv_data__en[0:5];
CGRAData_32_1_1 recv_data__msg[0:5];
logic [0:0] recv_data__rdy[0:5];
logic [0:0] recv_opt__en;
CGRAConfig_6_4_6_8 recv_opt__msg;
logic [0:0] recv_opt__rdy;
logic [0:0] send_data__en[0:7];
CGRAData_32_1_1 send_d... | 6.866425 |
module testbench_CSA ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
CSA uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum =... | 6.68794 |
module testbench_csa32 ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
csa32 uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (s... | 6.605262 |
module TestBench_debouncer #(
parameter DEBOUNCE_TIMER = 3
) ();
reg clk, reset;
reg [3:0] RAW_BTN;
button_debouncer #(
.DEBOUNCE_TIMER(DEBOUNCE_TIMER)
) DUT (
.clk(clk),
.reset(reset),
.RAW_BTN(RAW_BTN)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 0;
... | 6.923197 |
module test_decoder;
reg [1:0] in;
wire [3:0] out;
decoder_dataflow U0 (
out,
in
);
// test할 module (decoder_dataflow, decoder_structural, decoder_behavioral)
initial begin
#100 // 딜레이
in = 2'b00; // 입력 00
#100 in = 2'b01; // 입력 01
#100 in = 2'b10; // 입력 10
#100 in = ... | 6.703022 |
module TestBench ();
reg [1:0] X;
wire [3:0] Y;
decoder_2_4 decoder_2_4_test (
Y,
X
);
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, Y, X);
X = 2'b00;
#20;
X = 2'b01;
#20;
X = 2'b10;
#20;
X = 2'b11;
#20;
X = 2'b11;
#20;
$finish... | 7.747207 |
module TestBench_decoder_4_bit;
wire [15:0] Y;
reg [ 4:0] D;
Decoder_4_bit D0 (
Y,
D[3:0]
);
initial begin
for (D = 5'b00000; D <= 5'b01111; D = D + 5'b00001) #100;
end
initial $monitor($time, "\t D=%b Y=%b", D[3:0], Y);
endmodule
| 7.299579 |
module testbench_dtrig ();
parameter CLK_PERIOD = 10;
reg clk;
reg rst;
reg [3:0] d;
wire [3:0] q;
// Ӳģ
dtrig dtrig_test (
.clk(clk),
.rst(rst),
.d (d),
.q (q)
);
// ʼʱӡλź
initial begin
clk <= 0;
rst <= 0;
#1000;
rst <= 1;
@(posedge ... | 7.255235 |
module testbench_sumfour ();
parameter CLK_PERIORD = 10;
reg clk;
reg rst;
wire [3:0] o_cnt_1;
wire [3:0] o_cnt_2;
// ģ
sumfour sumfour_test (
.clk (clk),
.rst (rst),
.o_cnt_1(o_cnt_1),
.o_cnt_2(o_cnt_2)
);
// ʼʱ
initial begin
clk <= 0;
rst <= ... | 7.503826 |
module testbench_edge_detector ( /*AUTOARG*/);
//---------------------------------------------------------------------------
//
// Free Running Clock
//
//---------------------------------------------------------------------------
wire CLK;
free_running_clk CLK_50MHZ (.CLK(CLK));
//------------------... | 6.866457 |
module enc_tb ();
reg [3:0] tb_A = 4'b0000;
reg [3:0] tb_B = 4'b0000;
reg tb_cin = 1'b0;
wire [3:0] tb_sum = 4'b0000;
wire tb_cout = 4'b0000;
reg [7:0] tb_E;
wire [2:0] tb_F;
reg clk;
initial clk = 0;
always #10 clk = ~clk;
reg [31:0] tb_mem[0:2];
lab6_2circuits enc_ins (
.A(tb_A),
... | 7.185917 |
module testbench_encender_lucesLED;
//Entradas
reg [3:0] bin = 0;
//Salidas
wire [3:0] led;
//Unidad Bajo Prueba (UUT)
encender_lucesLED uut (
.bin(bin),
.led(led)
);
//Variable para hacer las pruebas
reg [4:0] k = 0;
initial begin
bin = 0;
for (k = 0; k < 16; k = k + 1) #1... | 6.783584 |
module testbench_exemplo ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para... | 7.476841 |
module testbench_exemplo1 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping par... | 7.476841 |
module testbench_exemplo2 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping par... | 7.476841 |
module testbench_exemplo3 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping par... | 7.476841 |
module testbench_exemplo4 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping par... | 7.476841 |
module testbench_exemplo5 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping par... | 7.476841 |
module testbench_extcall (
output wire completed
);
wire [3:0] completion;
assign completed = &completion;
testbench_termcall_beep p_termcall_beep (completion[0]);
testbench_termcall_putc p_termcall_putc (completion[1]);
testbench_hypercall_exit p_hypercall_exit (completion[2]);
testbench_hypercall_log... | 7.606883 |
module TB;
wire ss, cy;
reg aa, bb, cc;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end
gate newGate (
.a (aa),
.b (bb),
.c (cc),
.s (ss),
.ca(cy)
);
initial begin
aa = 1'b0;
bb = 1'b0;
#5 aa = 1'b0;
bb = 1'b1;
#5 aa = 1'b1;
bb =... | 6.522363 |
module testbench_fetcher #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //j
parameter ARRAY_L = 4
); //i
localparam ARRAY_SIZE = ARRAY_L * ARRAY_W;
reg [ DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] parameters_test;
reg [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] inputs_test;
wire [2*DATA_WIDTH*ARRAY_W*ARRAY_... | 8.040859 |
module address_mux_tb #(
parameter WIDTH = 5
) ();
reg [WIDTH - 1 : 0] in0, in1;
reg sel;
wire [WIDTH - 1 : 0] out;
initial begin
in0 = {WIDTH{1'b0}};
in1 = {WIDTH{1'b0}};
sel = 0;
end
// DUT
address_mux adm0 (
.in0(in0),
.in1(in1),
.sel(sel),
.out(out)
);
... | 7.411159 |
module tss_tb;
reg CLK, BUS_CON, STROBE_DATA, STROBE_MODE, RESET;
wire [7:0] IN_VAL;
wire [7:0] BUS;
reg [7:0] OUT_VAL;
reg OUT_VALID;
test_just_2 T1 (
.clk(CLK),
.bus(BUS),
.bus_con(BUS_CON),
.strobe_data(STROBE_DATA),
.strobe_mode(STROBE_MODE),
.reset(RESET)
);
assi... | 6.649286 |
module test_for_P2RV ();
reg clk = 1;
reg resetn = 0;
/** clk */
always #5 clk = ~clk;
/** reset */
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
`ifdef MODELSIM
reg [1023:0] firmware_file, instr_file, data_file;
initial begin
// instr_file = "instr.hex";
// $readmemh(in... | 6.964132 |
module tb;
// logic [0:0] clk;
// logic [1:0] count;
// logic [0:0] reset;
// logic [0:0] recv__en;
// CGRAData_32_1_1 recv__msg;
// logic [0:0] recv__rdy;
// logic [0:0] send__en;
// CGRAData_32_1_1 send__msg;
// logic [0:0] send__rdy;
// ChannelRTL__DataType_CGRAData_32_1_1__latency_1 dut (
// .clk(clk),
// ... | 6.640745 |
module TestBench_FullRangeFFFF ();
reg CLK;
reg Reset;
reg [7:0] A;
reg [15:0] B;
wire [7:0] Q;
wire [7:0] R;
wire Done;
integer j;
reg [7:0] tempQ, tempR;
Top UUT (
.CLK(CLK),
.Reset(Reset),
.A(A),
.B(B),
.Q(Q),
.R(R),
.Done(Done)
);
always #10 CLK <= ... | 6.602917 |
module TestBench_GL_Dec;
wire [7:0] D;
reg [3:0] I;
reg [1:0] E;
GL_decoder_3_bit D0 (
D,
I[2:0],
E[0]
);
initial begin
for (E = 2'b00; E <= 2'b01; E = E + 2'b01) for (I = 4'b0000; I <= 4'b0111; I = I + 4'b0001) #50;
end
initial $monitor($time, "\t I=%b D=%b E=%b", I, D, E);... | 6.515183 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$d... | 6.640835 |
module TB;
wire ss, cc;
reg aa, bb;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end
gate newGate (
.a(aa),
.b(bb),
.s(ss),
.c(cc)
);
initial begin
aa = 1'b0;
bb = 1'b0;
#5 aa = 1'b0;
bb = 1'b1;
#5 aa = 1'b1;
bb = 1'b0;
#5 aa = 1'b1... | 6.522363 |
module testbench_int; //testbench y probador de DAT
reg [ 3:0] card_in = 0;
reg [31:0] buffer_in = 0;
wire [31:0] buffer_out;
wire [ 3:0] card_out;
reg clock, host_clk;
reg new_trans;
reg enable_write, enable_read, Clear_in, reset;
parameter n = 32;
parameter vector_width = 10; //reg_vector has i... | 6.68599 |
module: logica_para_Escribir_Leer_Mux
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_IO_datos;
// Inputs
reg clk;
reg reset;
reg in_flag_dato;
reg in_direccion_dato;... | 6.901575 |
module testbench_lectura_codigoGray;
//Entradas
reg [3:0] a = 0;
//Salidas
wire [3:0] bin;
//Unidad Bajo Prueba (UUT)
lectura_codigoGray uut (
.a (a),
.bin(bin)
);
//Variable para hacer las pruebas
reg [4:0] k = 0;
initial begin
a = 0;
for (k = 0; k < 16; k = k + 1) #10 a ... | 6.506838 |
module: logica_generador_pulsos_RTC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_logica_generador_pulsos_rtc;
// Inputs
reg clk;
reg rst;
reg [1:0] funcion;
reg [7... | 6.693355 |
module Testbench_logic ();
reg [31:0] tb_mem[0:2];
reg [ 3:0] sbin;
reg rin1, rin2, rin3, rin4, rin5, clk;
wire wout;
wire [3:0] sbout;
initial clk = 0;
always #10 clk = ~clk;
logic_tile inst_logic_tile (
.in1 (rin1),
.in2 (rin2),
.in3 (rin3),
.in4 (rin4),
.in5 (rin5... | 8.338779 |
module testbench;
//outputs
wire [15:0] busA, busB;
wire rw;
//inputs
reg [15:0] dataIn;
reg reset, clk;
Processor mARC ( //marcee
dataIn, //data or instructions comming from the main memory
busA, //Data comming from the bus A of the datapath
busB, //Data comming from the bus B of... | 7.015571 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$d... | 6.640835 |
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_... | 6.647596 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$d... | 6.640835 |
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