code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_... | 6.647596 |
module TestBench ();
reg [3:0] X;
reg [1:0] S;
wire Y;
mux_4_1 mux_4_1_test (
Y,
X,
S
);
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, Y, X, S);
X = 4'b0111;
S = 2'b00;
#20;
X = 4'b0101;
S = 2'b01;
#20;
X = 4'b0101;
S = 2'b10;
#2... | 7.747207 |
module TB;
wire yy;
reg aa;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end
gate newGate(.a(aa), .y(yy));
initial
begin
aa = 1'b0;
#5
aa = 1'b0;
#5
aa = 1'b1;
#5
aa = 1'b1;
#5
end
endmodule
| 7.168566 |
module dram #(
parameter AWIDTH = 10,
parameter DWIDTH = 80
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
initial begin
$readmemh("/home/tanmay/Koios++ - Copy/Multi_tile_design/dram_d... | 8.142541 |
module instruction_mem #(
parameter AWIDTH = `INSTR_MEM_AWIDTH,
parameter DWIDTH = `INSTR_WIDTH
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
/... | 7.714331 |
module tb ();
reg [7:0] testcase0[1:0];
reg [7:0] testcase1[1:0];
reg [7:0] testcase2[1:0];
reg [7:0] testcase3[1:0];
reg [7:0] testcase4[1:0];
reg [7:0] testcase5[1:0];
reg [7:0] testcase6[1:0];
reg [7:0] testcase7[1:0];
wire [15:0] result[7:0];
reg [7:0] binary_result;
reg dummy;
csmulti_full... | 7.002324 |
module PianoTest ();
//输出信号
wire [7:0] ROW, COL_RED, COL_GREEN;
wire Beep;
wire [6:0] SEG;
wire [7:0] SEG_Neg;
//输入信号
reg CLK;
reg [3:0] Switch;
reg [6:0] Key;
//初始化
initial begin
CLK = 1'b0;
Switch = 4'b0000;
Key = 7'b0000000;
end
//实例化程序
Piano m1 (
.ROW(ROW),
.C... | 9.20466 |
module testbench_posenege ();
parameter CLK_PERIOD = 10;
reg clk;
reg rst;
reg pulse;
wire rise_edge;
wire fall_edge;
posenege posenege_test (
.clk (clk),
.rst (rst),
.pulse (pulse),
.rise_edge(rise_edge),
.fall_edge(fall_edge)
);
// ʼλʱ
initial begi... | 7.314512 |
module testbench;
parameter width = 3;
reg clk, rst;
reg [width-1:0] a, b, c;
reg [width-1:0] ans_no1, ans_no2, ans_no3;
wire [width-1:0] no1, no2, no3;
integer i, j, k, l, error, num;
reg [width*3-1:0] ans[0:511];
pplsort sort (
.no1(no1),
.no2(no2),
.no3(no3),
.a (a),
... | 7.015571 |
module testbench_ram_direct_read (
output reg completed
);
`include "../utils.h"
integer ipt;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
reg [17:0] psw;
reg enable;
reg signed [1:0] pt;
reg [17:0] addr;
wire ready;
wire pagefault;
wire [17:0] out;
triram ... | 7.112385 |
module testbench_ram (
output wire completed
);
wire [0:0] completion;
assign completed = &completion;
testbench_ram_direct_read p_ram_direct_read (completion[0]);
initial begin
#10;
while (!completed) #10;
$display("[ram] Test group completed.");
end
endmodule
| 7.112385 |
module TestBench_RC;
wire [3:0] S;
wire C;
reg [4:0] A, B;
reg [1:0] K;
rippleCarryAdder_4_bit RC (
S,
C,
A[3:0],
B[3:0],
K[0]
);
initial begin
for (A = 5'b00000; A <= 5'b01111; A = A + 5'b00001)
for (B = 5'b00000; B <= 5'b01111; B = B + 5'b00001)
for (K = 2'b0... | 6.950823 |
module i2c_tb ();
reg clk, rst, enable, read_write;
reg [7:0] data_write;
wire scl;
wire sda;
//reg SDA;
//wire direction=1;
//assign sda=direction?SDA:1'bZ;
wire [7:0] data;
wire [7:0] data_received;
reg scl_in;
//tri1 sda_in;
i2c_master master1 (
clk,
rst,
enable,
read_... | 7.143885 |
module Testbench_reg;
// Inputs
wire clk_in;
// Outputs
wire clk_out_f, clk_out_2f, clk_out_4f;
// Instantiate the Unit Under Test (UUT)
// Test the clock divider in Verilog
Gen_relojes #(
.DIVISOR(32'd6)
) clk_4f (
.clk_in (clk_in),
.clk_out(clk_out_4f)
);
Gen_relojes clk_2f (
... | 6.631497 |
module TestBench_SEG;
wire [7:0] Y;
reg [4:0] I;
Binary_to_7Seg S0 (
Y[6:0],
I[3:0]
);
initial begin
for (I = 5'b00000; I < 5'b01111; I = I + 5'b00001) #50;
end
initial $monitor($time, "\t I=%b Y=%b", I[3:0], Y[6:0]);
endmodule
| 7.072886 |
module testbench_shift_reg #(
parameter DATA_WIDTH = 8,
parameter LENGTH = 4
);
reg [DATA_WIDTH*LENGTH-1:0] parameters_test;
reg [DATA_WIDTH-1:0] inputs_test;
wire [DATA_WIDTH*LENGTH-1:0] data_test;
wire [DATA_WIDTH-1:0] outputs_test;
reg [1:0] control;
reg clk, reset_n;
shift_reg #(
.DATA... | 8.087461 |
module testbench_sigma;
reg [3:0] a;
reg [3:0] b;
reg [3:0] s;
reg m;
reg cin_re;
reg clock;
wire cout_re;
wire [3:0] y;
alu_4bit uut (
.a(a),
.b(b),
.s(s),
.m(m),
.cin_re(cin_re),
.cout_re(cout_re),
.y(y)
);
initial begin
a = 0;
b = 0;
s =... | 6.747363 |
module testbench_signed_cmp;
reg clk;
reg [15:0] a, b;
wire [15:0] less;
signed_cmp comparator (
.clk(clk),
.a(a),
.b(b),
.less(less)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
initial begin
a <= 16'h0012;
b <= 16'h0014;
#4... | 6.747363 |
module testbench();
//DEFINE PARAMETER
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 16;
wire write_read;
wire error;
wire force_terminate;
wire complete;
wire [ADDR_WIDTH-1:0] address;
wire [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH-1:0] rdata;
reg [2:0]memory_sel;
reg [4:0]memtype;
reg [2:0]operation;
reg clk, r... | 7.864579 |
module testbench_soc ();
reg clk, reset;
wire [3 : 0] KEY;
wire [3 : 0] LEDG;
wire [6 : 0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [2:0] ext_int;
SoC_IP_top IP (
.CLOCK_50 (clk),
.KEY (KEY),
.LEDG (LEDG),
.HEX0 (HEX0),
.HEX1 (HEX1),
.HEX2 (HEX2),
... | 7.030992 |
module Testbench_SramTest;
reg clock;
reg wren;
reg [14:0] address;
reg [7:0] data;
wire [7:0] read;
always begin
#50 clock = ~clock;
$display($time, "%d : %b : %h", read, read, read);
end
always @(posedge clock) address <= address + 1;
SRAM sram (
.clock(clock),
.address(addres... | 6.585527 |
module testbench_sum_nmax #(
parameter DATA_WIDTH = 8,
parameter LENGTH = 10
);
reg [2*DATA_WIDTH*LENGTH-1:0] inputs_test;
wire [LENGTH-1:0] outputs_test;
reg [DATA_WIDTH*LENGTH-1:0] biases_test;
reg clk, reset_n, ready;
sum_and_max #(
.DATA_WIDTH(DATA_WIDTH),
.LENGTH(LENGTH)
) dut (
... | 7.503826 |
module testbench_switch ();
reg clk;
always begin
#50 clk = 0;
#50 clk = 1;
end
reg HSEL;
//reg HCLK;
reg HRESETn;
reg HREADY;
reg [31:0] HADDR;
reg [1:0] HTRANS;
reg HWRITE;
reg [2:0] HSIZE;
reg [31:0] HWDATA;
wire HREADYOUT;
reg [14:0] switch;
wire irq;
SWITCH_INPUT peri (
... | 6.628471 |
module testbench;
//
// Free Running 50 MHz clock
//
parameter _clk_50mhz_high = 10,
_clk_50mhz_low = 10,
_clk_50mhz_period = _clk_50mhz_high + _clk_50mhz_low;
reg clk_tb;
initial begin
clk_tb <= 'b0;
forever begin
#(_clk_50mhz_low) clk_tb = 1;
#(_clk_50mhz_high) clk_tb = 0;
... | 7.015571 |
module testbench_sys_array #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //j
parameter ARRAY_L = 4
); //i
reg [DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] parameters_test;
reg [DATA_WIDTH*ARRAY_L-1:0] inputs_test;
wire [2*DATA_WIDTH*ARRAY_W-1:0] outputs_test;
reg clk, reset_n, param_load;
sys_array_... | 6.885036 |
module TestBench ();
reg [3:0] X;
reg [1:0] S;
wire [3:0] Y;
TestMuxDecoder TestMuxDecoderTest (
Y,
X,
S
);
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, Y, X, S);
X = 4'b0111;
S = 2'b00;
#20;
X = 4'b0101;
S = 2'b01;
#20;
X = 4'b0101;
... | 7.747207 |
module: timing_generator_VGA
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestBench_timing_generator_VGA;
// Inputs
reg clk;
reg reset;
// Outputs
wire hsync;
wire vsync;
... | 7.401997 |
module testbench #(
parameter TARGET = "DEFAULT", // pass through variable for hard macro
parameter TIMEOUT = 5000 // timeout value (cycles)
) (
input clk
);
parameter integer PERIOD_CLK = 10;
parameter integer TCW = 8;
parameter integer IOW = 64;
parameter integer NUMI = 2;
// Local pa... | 6.640835 |
module testbench_util_trit_m1 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_m1(2'b11) !== 1'b1) $error("[util_trit_m1] #-");
if (util_trit_m1(2'b00) !== 1'b0) $error("[util_trit_m1] #0");
if (util_trit_m1(2'b01) !== 1'b0) $error("[util_trit_m1] #+")... | 8.105787 |
module testbench_util_trit_0 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_0(2'b11) !== 1'b0) $error("[util_trit_0] #-");
if (util_trit_0(2'b00) !== 1'b1) $error("[util_trit_0] #0");
if (util_trit_0(2'b01) !== 1'b0) $error("[util_trit_0] #+");
... | 8.105787 |
module testbench_util_trit_1 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_1(2'b11) !== 1'b0) $error("[util_trit_1] #-");
if (util_trit_1(2'b00) !== 1'b0) $error("[util_trit_1] #0");
if (util_trit_1(2'b01) !== 1'b1) $error("[util_trit_1] #+");
... | 8.105787 |
module testbench_util_tryte_check (
output reg completed
);
`include "../utils.h"
integer ii;
reg [17:0] tryte;
initial begin
completed = 0;
for (ii = -9841; ii <= 9841; ii = ii + 1) begin
tryte = util_int_to_tryte(tryte);
if (util_tryte_check(tryte) !== tryte) $error("[util_tryte_ch... | 8.105787 |
module testbench_util_trit_neg (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_neg(2'b11) !== 2'b01) $error("[util_trit_neg] #-");
if (util_trit_neg(2'b00) !== 2'b00) $error("[util_trit_neg] #0");
if (util_trit_neg(2'b01) !== 2'b11) $error("[util_trit... | 8.105787 |
module testbench_util_trit_neg_cond (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_neg_cond(1'b0, 2'b11) !== 2'b11) $error("[util_trit_neg_cond] 0 #-");
if (util_trit_neg_cond(1'b0, 2'b00) !== 2'b00) $error("[util_trit_neg_cond] 0 #0");
if (util_trit... | 8.105787 |
module testbench_util_halfadder (
output reg completed
);
`include "../utils.h"
function [1:0] trunc2(input integer n);
begin
trunc2 = n[1:0];
end
endfunction
function [3:0] trunc4(input integer n);
begin
trunc4 = n[3:0];
end
endfunction
integer ii0;
integer ii1;
intege... | 8.105787 |
module testbench_util_5trits_to_8bits (
output reg completed
);
`include "../utils.h"
function [9:0] trunc10(input integer n);
begin
trunc10 = n[5:0];
end
endfunction
integer ii;
initial begin
completed = 0;
for (ii = -13; ii <= 13; ii = ii + 1) begin
if (ii !== util_5trits... | 8.105787 |
module testbench_util_int_to_tryte (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_int_to_tryte(-29524) !== 18'b111111111111111111) $error("[util_int_to_tryte] -29524");
if (util_int_to_tryte(-29523) !== 18'b111111111111111100) $error("[util_int_to_tryte] -295... | 8.105787 |
module testbench_util_int_to_trits10 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_int_to_trits10(-29524) !== 20'b11111111111111111111)
$error("[util_int_to_trits10] -29524");
if (util_int_to_trits10(-29523) !== 20'b11111111111111111100)
$error("... | 8.105787 |
module testbench_utils (
output wire completed
);
wire [8:0] completion;
assign completed = &completion;
testbench_util_trit_m1 p_util_trit_m1 (completion[0]);
testbench_util_trit_0 p_util_trit_0 (completion[1]);
testbench_util_trit_1 p_util_trit_1 (completion[2]);
testbench_util_tryte_check p_util_try... | 8.105787 |
module testbench #(
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 1;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 0;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
en... | 6.640835 |
module picorv32_wrapper #(
parameter VERBOSE = 0
) (
input wb_clk,
input wb_rst,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
wire mem_instr;
reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycl... | 6.647596 |
module wb_ram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output... | 6.893135 |
module vsdmemsoc_tb;
// Inputs
supply0 vgnd;
supply1 vpwr;
reg ext_clk, reset;
reg wb_clk_i;
reg wb_rst_i;
reg wbs_stb_i;
reg wbs_cyc_i;
reg wbs_we_i;
reg [3:0] wbs_sel_i;
reg [31:0] wbs_dat_i;
reg [7:0] wbs_adr_i;
// Outputs
wire [9:0] OUT;
wire [31:0] wbs_dat_o;
wire wbs_ack_o;
//... | 7.032941 |
module testbench_width; //testbench y probador de DAT
reg [3:0] card_in = 0;
reg [31:0] buffer_in = 0;
wire [31:0] buffer_out;
wire [3:0] card_out;
reg clock;
reg new_trans;
reg enable_write, enable_read, Clear_in, reset;
parameter n = 32;
parameter vector_width = 10; //reg_vector has inputs with i... | 7.203513 |
module count_tb;
03 localparam DELY=100;
04 reg clk,reset; //测试输入信号,定义为reg 型
05 wire[3:0] cnt; //测试输出信号,定义为wire型
06
07 always#(DELY/2) clk = ~clk; //产生时钟波形
08 initial
09 begin //激励信号定义
10 clk =0; reset=0;
11 #DELY reset=1;
12 #DELY reset=0;
13 #(DELY*100) $finish(2);
14 end
15 //定义结果... | 6.703937 |
module 连续赋值模块名 (
// I/O端口列表说明
input 输入端口列表
output 输出端口列表
);
// 数据类型说明
wire 结果信号名；
// 逻辑功能定义
assign <结果信号名> =逻辑表达式 ；
…
assign <结果信号名n>=逻辑表达式n；
endmodule
| 6.634401 |
module 行为描述模块名 (
// I/O端口列表说明
input 输入端口列表
output reg 输出端口列表
);
// 数据类型说明
reg 中间变量
// 逻辑功能定义
always @(敏感事件列表) //行为描述1
begin
if-else、case、for等行为语句
end
.........
always @(敏感事件列表) //行为描述n
begin
if-else、case、for等行为语句
end
endmodule
| 7.098176 |
module testbench_wrapper #(
parameter DATA_WIDTH = 16,
parameter ARRAY_W = 10, //j
parameter ARRAY_L = 784, //i
parameter CLOCK_DIVIDE = 2
);
reg clk, reset_n, param_load, start_comp;
wire [7:0] hex_output;
sys_array_wrapper #(
.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W(ARRAY_W),
.ARR... | 8.139825 |
module i2c_slave1 ();
reg clk, rst, enable, read_write;
reg [7:0] data_write;
wire scl;
wire sda;
//reg SDA;
//wire direction=1;
//assign sda=direction?SDA:1'bZ;
wire [7:0] data;
wire [7:0] data_received;
reg scl_in;
//tri1 sda_in;
i2c_master master2 (
clk,
rst,
enable,
r... | 7.302179 |
module TestBench_Zero_Detector;
reg X, clk, rst;
wire Y;
Zero_Detector ZD (
Y,
X,
clk,
rst
);
initial #200 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
rst = 0;
#2 rst = 1;
#87 rst = 0;
#89 rst = 1;
#10 X = 1;
#30 ... | 6.655457 |
module for CRC generators *
* ------------------------------------------------ */
module testboard(
input clk,
input rst,
input RsRx,
output [1:0] led,
output [3:0] an,
output [6:0] seg);
wire [15:0] crc1, crc0;
wire uart_en, clk_uart, uart_newdata;
wire [7:0] uart_data;
wire serial, serial_work... | 6.830467 |
module buffer (
s,
p
);
output s;
input p;
assign s = p;
endmodule
| 6.861394 |
module testbuffer;
reg a;
wire s;
// instancia
buffer BF1 (
s,
a
);
initial begin : start
a = 0;
end
// parte principal
initial begin : main
$display("Exemplo 00 - xxx yyy zzz - 999999");
$display("Test buffer");
$display("\na = s\n");
$monitor("%b = %b", a, s);
... | 7.153545 |
module testcache ();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache, readmissdata;
wire hit, miss, dirty;
// test
memory_system DUT (
clk,
re,
we,
we2,
we3,
address,
writedata,
readdatacache,
hit,
miss,
... | 6.753808 |
module testcase8_tb ();
reg sys_clk_n;
reg sys_clk_p;
reg reset;
reg requestDatafromDAC;
wire start_DAC;
wire chip_reset_n;
wire sys_clk;
wire needToLoadData;
wire detectRequestData;
testcase8_start_DAC_2 tb7_uut (
.sys_clk_n(sys_clk_n),
.sys_clk_p(sys_clk_p),
.reset(reset),
... | 6.567459 |
module
*
*
* MIT License
*/
module TestClaAdder;
// Inputs
reg [7:0] InputA;
reg [7:0] InputB;
reg InputCarry;
// Outputs
wire [7:0] Sum;
wire OutputCarry;
// Instantiate the Unit Under Test (UUT)
ClaAdder uut (
.InputA(InputA),
.InputB(InputB),
.InputCarry(InputCarry),
.Sum(Sum),
.Output... | 7.860622 |
module pulse2 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(posedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
end
endmodule
| 6.524618 |
module pulse3 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(negedge clock) begin
signal = 1'b1;
#15 signal = 1'b0;
#15 signal = 1'b1;
end
endmodule
| 6.545395 |
module TestCodeA (
input wire px_clk, // Pixel clock.
input wire [25:0] RGBStr_i, // Input RGB stream.
input wire [ 7:0] sprite, // Sprite data.
output reg [11:0] addr, // Address ROM where pixel sprites are.
output reg [25:0] RGBStr_o // Output RGB stream.
);
`define YC... | 7.821935 |
module testcontroller (
input wire clk,
input wire secure_mode,
input wire test_mode,
input wire reset_n,
output wire enableScanIn,
output wire enableScanOut,
output wire loadkey,
output wire scan_mode
);
wire FFin;
wire FFout;
DFF register (
.reset_n(reset_n),
.cl... | 6.773203 |
module DFF (
input wire clk,
input wire reset_n,
input wire D,
output reg Q
);
always @(posedge clk) begin
if (reset_n == 1) begin
Q <= D;
end else begin
Q <= 1'b0;
end
end
endmodule
| 7.464833 |
module testCPUController;
reg clk;
reg rst;
reg [15:0] opcode;
cpuController cpuCTRL (
.clk(clk),
.rst(rst),
.opcode(opcode)
);
initial begin
$dumpfile("../test.vcd");
$dumpvars;
end
always #5 clk = !clk;
initial begin
clk = 0;
rst = 1;
opcode = 0;
#10 rst... | 6.817465 |
module testdata (
clk,
dataout,
wrsig
);
input clk;
output [7:0] dataout;
output wrsig;
reg [7:0] dataout;
reg wrsig;
reg [7:0] cnt;
reg [4:0] i;
reg [7:0] volt [8:0]; //存储字符voltage:
initial begin
//定义发送的字符
volt[0] <= 118; //存储字符v
volt[1] ... | 6.806681 |
module: DataMemoryPipline
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDataMemory;
// Inputs
reg zero;
reg branch;
reg memRead;
reg memWrite;
reg [31:0] readData2Reg;
... | 6.628923 |
module
*
*
* MIT License
*/
module TestDebouncer;
// Inputs
`defClock(Clk, 2);
reg Input;
// Outputs
wire Output;
// Instantiate the Unit Under Test (UUT)
Debouncer #(
.DEBOUNCER_COUNTER_WIDTH(3)
) uut (
.Clk(Clk),
.Input(Input),
.Output(Output)
);
`startTest("Debou... | 7.860622 |
module: decode
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testdecode1;
// Inputs
reg [31:0] instruction;
reg [4:0] writeReg;
reg [31:0] writeData;
reg regWrite;
reg clk;
... | 6.50658 |
module testDec_flow_control_loop_pipe_sequential_init (
ap_clk,
ap_rst,
ap_start,
ap_ready,
ap_done,
ap_start_int,
ap_ready_int,
ap_done_int,
ap_continue_int,
ap_loop_init,
ap_loop_exit_ready,
ap_loop_exit_done
);
input ap_clk;
input ap_rst;
//Block level handshak... | 7.489365 |
module testdesign (
`ifdef USE_POWER_PINS
inout vdda,
inout vssa,
inout vccd,
inout vssd,
`endif
input wire clk,
input wire reset,
input wire [7:0] in,
output reg [7:0] out,
output reg [15:0] oeb
);
always @(posedge clk) begin
out <= in;
oeb[15:8] <= 1;
oeb[7:0] ... | 7.837218 |
module testDFlipFlop ();
reg clock, nreset, d;
DFlipFlop D1 (
q,
clock,
nreset,
d
);
always #10 clock = ~clock;
initial begin
//$dumpfile("testDFlipFlop.dump");
//$dumpvars(1,D1);
#0 d = 0;
clock = 0;
nreset = 1;
#55 nreset = 0;
#10 d = 0;
clock = 0;
... | 6.697297 |
module: qdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestDiv;
// Inputs
reg [31:0] i_dividend;
reg [31:0] i_divisor;
reg i_start;
reg i_clk;
// Outputs
wire [31:0] o... | 6.558319 |
module: qdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestDiv;
// Inputs
reg [63:0] i_dividend;
reg [63:0] i_divisor;
reg i_start;
reg i_clk;
reg [13:0] count;
reg [... | 6.558319 |
module TestDriver;
reg clock = 1'b0;
reg reset = 1'b1;
always #(`CLOCK_PERIOD / 2.0) clock = ~clock;
initial #(`RESET_DELAY) reset = 0;
// Read input arguments and initialize
reg verbose = 1'b0;
wire printf_cond = verbose && !reset;
reg [63:0] max_cycles = 0;
reg [63:0] dump_start = 0;
reg [63:0]... | 7.441403 |
module egate (
s,
p,
q
);
output s;
input p, q;
assign s = p & q;
endmodule
| 6.731803 |
module testegate;
reg a, b;
wire s;
egate AND1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
$display("Guia02 exercicio 02");
$display("tabela-verdade para porta AND\n");
$display("a & b = s");
$monitor("%b & %b = %b", a, b, s);
#... | 6.673264 |
module testnorgate;
reg a, b, c;
wire s;
nor (s, a, b, c);
endmodule
| 6.695863 |
module testeio_MemAddr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:... | 6.599329 |
module testeio_MemOut (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0... | 6.656136 |
module testeio_mem_ack_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0... | 6.612318 |
module testeio_mem_addr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [15:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3... | 6.612318 |
module testeio_mem_data (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [7:0] in_port;
input reset_n;
wire clk_en;
wire [ 7:0] data_in;
wire [ 7:0] read_mux_out;
reg [31:0] readda... | 6.742045 |
module testeio_mem_data_ready (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readda... | 6.742045 |
module testeio_onchip_memory2_0 (
// inputs:
address,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "testeio_onchip_memory2_0.hex";
output [7:0] readdata;
input [7:0] address;
input chipselect... | 6.755947 |
module testeio_two_port_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipsel... | 7.88217 |
module testeio_two_port_mem_correct (
// inputs:
address,
address2,
byteenable,
byteenable2,
... | 7.88217 |
module testEnc_flow_control_loop_pipe_sequential_init (
ap_clk,
ap_rst,
ap_start,
ap_ready,
ap_done,
ap_start_int,
ap_ready_int,
ap_done_int,
ap_continue_int,
ap_loop_init,
ap_loop_exit_ready,
ap_loop_exit_done
);
input ap_clk;
input ap_rst;
//Block level handshak... | 7.774457 |
module testEnc_mux_134_128_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 6.958718 |
module testEnc_mux_144_128_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 6.958718 |
module testEnc_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [D... | 6.565231 |
module testEnc_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg ... | 6.565231 |
module testEnc_updateKey_Rcon_ROM_AUTO_1R (
address0,
ce0,
q0,
reset,
clk
);
parameter DataWidth = 8;
parameter AddressWidth = 4;
parameter AddressRange = 10;
input [AddressWidth-1:0] address0;
input ce0;
output reg [DataWidth-1:0] q0;
input reset;
input clk;
reg [DataWidth-1:0]... | 6.583559 |
module tester ();
reg [3:0] screen[HEIGHT-1:0][WIDTH-1:0][2:0];
parameter WIDTH = 640;
parameter HEIGHT = 480;
parameter LINE = 800;
parameter SCREEN = 525;
parameter N_CASES = 1;
parameter AFTER_HSYNC = 47;
parameter AFTER_VSYNC = 31;
integer i;
integer j;
integer ... | 6.846651 |
module tester_ctrl #(
parameter ADDR_WIDTH = 24
) (
input clk,
input rst_n,
output rd_enable_o,
output wr_enable_o,
input busy_i,
input rd_ready_i,
input [ 15:0] rd_data_i,
output ... | 6.93984 |
module tester_gmii #(
parameter NUM_OF_HSR_NODE = 4
, HSR_ID = 0
, TX_ENABLE = 0
) (
input wire reset
, output reg gmii_gtxc = 1'b1
, output reg [ 7:0] gmii_txd = 8'h0
, output reg gmii_txen = 1'b0
, output reg gmii_txer = 1'b0
, input wire ... | 6.700421 |
module tester_gtx_chk #(
parameter IDLE = 16'h02bc
) (
input [15:0] rx_data,
input [ 1:0] rx_char,
input usrclk,
input usrrst_n,
output err_flag, //data error flag
output [15:0] der //data error rate
);
reg [15:0] rx_data_r;
reg data_err_flag... | 7.275511 |
module tester_gtx_gen #(
parameter IDLE = 16'h02bc
) (
input usrclk,
input usrrst_n,
input [7:0] test_len_ctrl, // interval length of each set of data
input test_run_ctrl, // control signal to generate data
output [15:0] txdata, // generate data for gtx
output [ 1:0] tx... | 8.496655 |
module tester_pulse_gen;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/**********************************************************... | 7.414258 |
module tester_pulse_sync;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/*********************************************************... | 7.414258 |
module tester_reset_sync;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/*********************************************************... | 8.020631 |
module tester_signal_sync;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/********************************************************... | 8.001525 |
module tester_toggle_gen;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/*********************************************************... | 8.039183 |
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