code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module pc #(
parameter integer DATA_W = 16
) (
input wire clk,
input wire arst_n,
input wire enable,
input wire [DATA_W-1:0] branch_pc,
input wire [DATA_W-1:0] jump_pc,
input wire zero_flag,
input wire branch,
in... | 8.050335 |
module testeMemoria(
input CLOCK_50,
input [3:0] KEY,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS,
output [7:0]LEDG,
output [17:0] SRAM_ADDR,
inout [15:0] SRAM_DQ,
output SRAM_WE_N,
output SRAM_OE_N,
output SRAM_UB_N,
... | 7.523251 |
module: Experiment
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestExperiment;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0]x;
wire write;
wire final;
// Insta... | 7.882602 |
module: Experiment2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestExperiment2;
parameter N=16;
parameter nBits=32;
parameter B=2;
parameter M=2;
// Inputs
reg clk;
... | 6.898896 |
module TestExtremaValueEn (
input iclk,
input irst_n,
input iBig_en1,
input iBig_en2,
input iBig_en3,
output reg oBig_en
);
always @(posedge iclk or negedge irst_n) begin
if (!irst_n) begin
oBig_en <= 0;
end else begin
if (iBig_en1 & iBig_en2 & iBi... | 7.804649 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module teste_guia_11;
reg clk, reset, x;
wire m1, m2, m3, m4, m5;
guia11_ex01.v EX1 (
m1,
x,
clk,
reset
);
guia11_ex02.v EX2 (
m2,
x,
clk,
reset
);
guia11_ex03.v EX3 (
m3,
x,
clk,
reset
);
guia11_ex04.v EX4 (
m4,
x,
... | 6.698242 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1... | 7.237842 |
module soma_completa_3bit (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
// operador de soma completa de 3 bits
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire sa1, sa2;
// instancia
soma_completa_1bit SC1 (
s0,
sa1,
a0,
b0,
0... | 7.237842 |
module subt_comp_1b (
s0,
s1,
a,
b,
c
);
// operador de diferena completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_subt SUBT1 (
sa1,
sa2,
a,
b
);
meia_subt SUBT2 (
s0,
sa3,
sa1,
c
);
or OR1 (... | 7.03597 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1... | 7.237842 |
module prod_comp_2bits (
s0,
s1,
s2,
s3,
a0,
a1,
b0,
b1
);
// operador de produto completo de 2 bits
input a0, a1, b0, b1;
output s0, s1, s2, s3;
wire sa1, sa2, sa3, sa4;
// instancia
and AND1 (s0, a0, b0);
and AND2 (sa1, a0, b1);
and ADN3 (sa2, a1, b0);
and AND4 (... | 6.82542 |
module subt_comp_1bit (
s0,
s1,
a,
b,
c
);
// operador de diferena completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3, sa4;
// instancia
meia_subt SUBT1 (
sa1,
sa2,
a,
b
);
meia_subt SUBT2 (
s0,
sa3,
sa1,
c
);
n... | 7.152747 |
module subt_comp_2bit (
s0,
s1,
s2,
a0,
a1,
b0,
b1
);
// operador de diferena completa de 2 bit
input a0, a1, b0, b1;
output s0, s1, s2;
wire sa1;
// instancia
subt_comp_1bit SUBT1 (
s0,
sa1,
a0,
b0,
0
);
subt_comp_1bit SUBT2 (
s1,
... | 7.422042 |
module soma_comp_1bit (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3, sa4, sa5;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
nand NAND1 (sa4, sa2, sa2);
nand NAND2 ... | 7.023876 |
module soma_comp_2bit (
s0,
s1,
s2,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1, s2;
wire sa1;
// instancia
soma_comp_1bit SC1 (
s0,
sa1,
a0,
b0,
0
);
soma_comp_1bit SC2 (
s1,
s2,
a1,
b1,
sa1
);
endmodu... | 7.012556 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1... | 7.237842 |
module soma_completa_4bit (
s0,
s1,
s2,
s3,
auxCR,
auxOVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, auxCR, auxOVR;
wire sa1, sa2, sa3;
// instancia
soma_c... | 7.237842 |
module soma_ovr_cr (
s0,
s1,
s2,
s3,
CR,
OVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits, detector de carry e de overflow
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, OVR, CR;
wire auxOVR;
// instancia
... | 6.972168 |
module comparador_log (
s,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
input a0, a1, a2, a3, b0, b1, b2, b3;
output s;
wire sa1, sa2, sa3, sa4;
xor XOR1 (sa1, a0, b0);
xor XOR2 (sa2, a1, b1);
xor XOR3 (sa3, a2, b2);
xor XOR4 (sa4, a3, b3);
or OR1 (s, sa1, sa2, sa3, sa4);
e... | 6.729621 |
module meiaDiferenca (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire sa1;
xor XOR1 (s0, a, b);
not NOT1 (sa1, a);
and AND1 (s1, sa1, b);
endmodule
| 8.132121 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1... | 7.237842 |
module soma_completa_4bit (
s0,
s1,
s2,
s3,
auxCR,
auxOVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, auxCR, auxOVR;
wire sa1, sa2, sa3;
// instancia
soma_c... | 7.237842 |
module soma_ovr_cr (
s0,
s1,
s2,
s3,
CR,
OVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits, detector de carry e de overflow
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, OVR, CR;
wire auxOVR;
// instancia
... | 6.972168 |
module comparador_log (
s,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
input a0, a1, a2, a3, b0, b1, b2, b3;
output s;
wire sa1, sa2, sa3, sa4;
xor XOR1 (sa1, a0, b0);
xor XOR2 (sa2, a1, b1);
xor XOR3 (sa3, a2, b2);
xor XOR4 (sa4, a3, b3);
or OR1 (s, sa1, sa2, sa3, sa4);
e... | 6.729621 |
module complemento_2 (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
a3
);
input a0, a1, a2, a3;
output s0, s1, s2, s3;
wire sa0, sa1, sa2, sa3, CR, OVR;
complemento_1 COMP1 (
sa0,
sa1,
sa2,
sa3,
a0,
a1,
a2,
a3
);
soma_ovr_cr SOMA1 (
s0,... | 6.625481 |
module meiaDiferenca (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire sa1;
xor XOR1 (s0, a, b);
not NOT1 (sa1, a);
and AND1 (s1, sa1, b);
endmodule
| 8.132121 |
module incremento (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
a3
);
input a0, a1, a2, a3;
output s0, s1, s2, s3;
wire CR, OVR;
soma_ovr_cr SOMA1 (
s0,
s1,
s2,
s3,
CR,
OVR,
a0,
a1,
a2,
a3,
1,
0,
0,
0
);
e... | 6.976155 |
module produto (
s,
erro,
x
);
input [3:0] x;
output [3:0] s;
output erro;
assign s[0] = 0;
assign s[1] = x[0];
assign s[2] = x[1];
assign s[3] = x[2];
xor XOR1 (erro, x[3], x[2]);
endmodule
| 7.220624 |
module numero_01 (
s,
a,
b,
c,
d
);
input a, b, c, d;
output s;
wire sa1, sa2, sa3, sa4, sa5, sa6;
// instancia
not NOT1 (sa1, d);
not NOT2 (sa2, a);
not NOT3 (sa3, b);
and AND1 (sa4, a, b, sa1);
and AND2 (sa5, sa2, c);
and AND3 (sa6, sa3, c);
or OR1 (s, sa4, sa5, sa6);
... | 6.633437 |
module exercicio_01 (
qL,
q,
s,
r
);
// latch sr com portas nor
output q, qL;
input s, r;
nor NOR1 (qL, s, q);
nor NOR2 (q, r, qL);
endmodule
| 6.88485 |
module exercicio_02 (
qL,
q,
s,
r
);
// latch sr com portas nand
output q, qL;
input s, r;
nand NAND1 (q, s, qL);
nand NAND2 (qL, r, q);
endmodule
| 7.495124 |
module exercicio_03 (
qL,
q,
d,
pr,
cl
);
// latch d com portas nand, preset e clear
output q, qL;
input d, pr, cl;
wire dL;
not NOT1 (dL, d);
nand NAND1 (q, d, qL, pr);
nand NAND2 (qL, dL, q, cl);
endmodule
| 7.149001 |
module exercicio_04 (
qL,
q,
s,
r,
pr,
cl
);
// latch sr com portas nand, preset e clear
output q, qL;
input s, r, pr, cl;
nand NAND1 (q, s, qL, pr);
nand NAND2 (qL, r, q, cl);
endmodule
| 7.294467 |
module exercicio_05 (
qL,
q,
d
);
// latch d a partir de sr, sem preset e clear
output q, qL;
input d;
wire dL;
// negar o d
not NOT1 (dL, d);
// metodo com latch do tipo sr
exercicio_01 SR (
qL,
q,
d,
dL
);
endmodule
| 7.10458 |
module teste_guia_11;
reg clk, reset, x;
wire m1, m2, m3, m4, m5;
numero01_seq101_mealy NUM1 (
m1,
x,
clk,
reset
);
numero02_seq0101_moore NUM2 (
m2,
x,
clk,
reset
);
numero03_seq1001_mealy NUM3 (
m3,
x,
clk,
reset
);
numero04_s... | 6.698242 |
module flipflopD (
q,
d,
clk
);
output q;
input d;
input clk;
reg q = 0;
always @(posedge clk) begin
q <= d;
end // always borda de subida do clock
endmodule
| 7.073663 |
module teste_numero01;
reg clk, x;
wire q1, q2, q3, q4, q5;
// definir flipflops
flipflopD FLIP1 (
q1,
x,
clk
);
flipflopD FLIP2 (
q2,
q1,
clk
);
flipflopD FLIP3 (
q3,
q2,
clk
);
flipflopD FLIP4 (
q4,
q3,
clk
);
flipflopD ... | 7.187823 |
module flipflopD (
q,
d,
clk,
pr
);
output q;
input d;
input clk;
input pr;
reg q = 0;
always @(posedge clk or pr) begin
if (pr) q <= 1;
else q <= d;
end // always borda de subida do clock
endmodule
| 7.073663 |
module teste_numero02;
reg clk, load, d4, d3, d2, d1, d0;
wire q1, q2, q3, q4, q5, pr1, pr2, pr3, pr4, pr5;
//definir presets
and AND1 (pr1, load, d4);
and AND2 (pr2, load, d3);
and AND3 (pr3, load, d2);
and AND4 (pr4, load, d1);
and AND5 (pr5, load, d0);
// definir flipflops
flipflopD FLIP1 (
... | 7.187823 |
module flipflopD (
q,
d,
clk
);
output q;
input d;
input clk;
reg q = 0;
always @(posedge clk) begin
q <= d;
end // always borda de subida do clock
endmodule
| 7.073663 |
module teste_numero04;
reg clk, x;
wire q1, q2, q3, q4, q5;
// definir flipflops
flipflopD FLIP1 (
q5,
x,
clk
);
flipflopD FLIP2 (
q4,
q5,
clk
);
flipflopD FLIP3 (
q3,
q4,
clk
);
flipflopD FLIP4 (
q2,
q3,
clk
);
flipflopD ... | 7.187823 |
module teste_Program_conter_module (
input clock,
input reset_geral,
input modo_preemptivo,
input reset_cont_preempcao,
input [4:0] quantum,
input halt,
input [1:0] jump_prog,
output [31:0] PC,
output [31:0] PC_mais_1,
output flag_faz_preempcao,
output [31:0] salva_PC
);
... | 8.160279 |
module teste_s (
input iCLK_50,
input [17:0] iSW,
input [3:0] iKEY,
output [17:0] oLEDR,
output [8:0] oLEDG,
output [6:0] oHEX0_D,
oHEX1_D,
oHEX2_D,
oHEX3_D,
oHEX4_D,
oHEX5_D,
oHEX6_D,
oHEX7_D,
output oHEX0_DP,
oHEX1_DP,
oHEX2_DP,
oHEX3_DP,
oHEX4_D... | 7.293189 |
module testfixture1;
reg clk;
reg reset;
reg fft_en;
wire fir_valid;
wire fin;
reg [15:0] fir_d; // 8 integer + 8 fraction
wire [31:0] fft_d;
wire [3:0] freq;
wire [15:0] fft_real = fft_d[31:16];
wire [15:0] fft_imag = fft_d[15:0];
reg en;
reg [15:0] fir_mem[0:1023];
initial $readmemh("FFT_... | 6.530037 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testForFuck;
// Inputs
reg data_ready;
reg tsre;
reg tbre;
reg Clk0;
reg Rst;
// Outputs
wire data_ready_out;
w... | 7.115105 |
module: Parse32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testforparse;
// Inputs
reg clk;
reg [31:0] data;
// Outputs
wire [63:0] odata;
// Instantiate the Unit Under... | 6.764872 |
module testForPC;
wire [31:0] nowPc;
wire [31:0] instruct;
wire [31:0] nextPc;
reg clk;
reg rstn;
reg clear;
reg jump;
reg [31:0] imm;
initial begin
clk = 0;
rstn = 0;
jump = 0;
#10 rstn = 1'b1;
clear = 1'b1;
#10 jump = 1'b1;
imm = 32'b0000_0000_0000_0000_0000_0000_0000_... | 7.113817 |
module testForregFile;
reg clk;
reg rstn;
reg [4:0] Wadd;
reg [31:0] Wdata;
reg isWreg;
reg [4:0] Radd1;
wire [31:0] Rdata1;
reg [4:0] Radd2;
wire [31:0] Rdata2;
reg [5:0] ALUctr;
wire [31:0] result;
regFile regFile0 (
.clk(clk),
.rstn(rstn),
.Wadd(Wadd),
.Wdata(Wda... | 7.096511 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testforwhole;
// Inputs
reg CCLK;
reg BTN2;
reg BTN1;
reg BTN3;
reg [3:0] SW;
// Outputs
wire LCDRS;
wire LCDRW... | 7.115105 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testforwholen;
// Inputs
reg CCLK;
reg BTN1;
reg BTN2;
reg BTN3;
reg [3:0] SW;
// Outputs
wire LCDRS;
wire LCDR... | 7.115105 |
module testFU ();
reg [31:0] rs_data, rt_data, memwb_data;
reg [4:0] rs_addr, rt_addr, exmem_rd_addr, memwb_rd_addr;
reg [3:0] exmem_byte_en, memwb_byte_en;
wire [31:0] input_A, input_B;
wire [1:0] A_sel, B_sel;
ForwardUnit m0 (
.rs_data(rs_data),
.rt_data(rt_data),
.memwb_data(memwb_dat... | 6.712866 |
module/testfx_spi.v
// Project Name: spi_module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spi_master_4byte
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////... | 7.102711 |
module testgen;
// Inputs
reg clk;
reg [31:0] out_freq;
reg [31:0] discr_freq;
// Outputs
wire [15:0] sin;
wire [15:0] cos;
// Instantiate the Unit Under Test (UUT)
cordic_gen uut (
.clk(clk),
.out_freq(out_freq),
.discr_freq(discr_freq),
.sin(sin),
.cos(cos)
);
r... | 7.217801 |
module TestGuitarHero (
KEY,
LEDR,
CLOCK_50
);
input [3:0] KEY;
input CLOCK_50;
output [7:0] LEDR;
wire [3:0] empty_data;
assign empty_data = 4'b0000;
wire never_write;
assign never_write = 1'b0;
wire [3:0] track1_out;
ram32x4_track1 track1 (
.address(5'b00000),
.clock(CLOCK_... | 6.986991 |
module testHarness ();
// -----------------------------------
// Local Wires
// -----------------------------------
reg clk;
reg rst;
wire [8:0] adr;
wire [7:0] masterDout;
wire [7:0] masterDin;
wire [7:0] usbSlaveDout;
wire [7:0] usbHostDout;
wire stb;
wire we;
wire ack;
wire host_stb;
... | 7.129426 |
module: IFU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testIFU;
// Inputs
reg clk;
reg reset;
reg [2:0] nPC_sel;
reg [31:0] imm32;
reg [31:0] PC_jr;
reg [31:0] PC_j;
/... | 6.644283 |
module testIm_ctrl (
input clock,
input reset,
input [`SCREEN_X_BITWIDTH:0] x_coord,
input [`SCREEN_Y_BITWIDTH:0] y_coord,
output reg [9:0] test_addr
);
// shift left control
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
test_addr <= 0;
end else if( x_... | 7.14564 |
module TestIncDec ();
reg CLK;
always #25 CLK = ~CLK;
wire [15:0] AddrBus;
wire [15:0] d;
wire [15:0] nq;
Reg16 acc (
.clk(CLK),
.d (d),
.nq (nq)
);
// The value on the cbus/dbus contains a ~val of register (register `q` output inversion).
// This value is stored on the BusKeepe... | 6.584179 |
module Reg16 (
clk,
d,
q,
nq
);
input clk;
input [15:0] d;
output [15:0] q;
output [15:0] nq;
reg [15:0] val;
initial val <= 16'h0;
always @(negedge clk) begin
val <= d;
end
assign q = val;
assign nq = ~q;
endmodule
| 7.358075 |
module testbench;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, testbench, sixteenbitdecoder, SpeedClock);
$finish;
end
endmodule
| 7.015571 |
module testbench (
speedy_clock
);
input speedy_clock;
initial begin
$dumpfile("test.vcd");
$display($time, "speedy_clock changed to %d", speedy_clock);
$dumpvars(0, testbench, sixteenbitdecoder, SpeedClock, clock);
$monitor($time, "speedy_clock is now %d", speedy_clock);
#1;
$monitor(... | 6.751666 |
module testingAT;
// Inputs
reg clock;
reg reset;
reg bt_state;
reg [15:0] ep01wireIn;
reg [15:0] ep02wireIn;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
// Outputs
wire fpga_txd;
wire fpga_rxd;
wir... | 6.860844 |
module testingDS;
// Inputs
reg clock;
reg reset;
reg bt_state;
reg [15:0] ep01wireIn;
reg [15:0] ep02wireIn;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
// Outputs
wire fpga_txd;
wire fpga_rxd;
wir... | 6.617691 |
module testingFIFO_Centre;
// Inputs
reg clock;
reg reset;
reg [8:0] wr_en, rd_en;
// Outputs
wire [15:0] datastream0, datastream1, datastream2, datastream3, datastream4, datastream5, datastream6, datastream7;
wire [8:0] fifo_state_full, fifo_state_empty;
wire [5:0] DS0_rd_count, DS1_rd_count, DS2_rd_... | 6.849459 |
module testingHandleAppCommands;
// Inputs
reg clock;
reg reset;
reg start;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
wire [7:0] rx_data;
wire data_line;
wire rx_done;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
// Outputs
wire [7:0] stream... | 7.336225 |
module testingHandleATResponse;
// Inputs
reg clock;
reg reset;
reg start;
reg RFIFO_rd_en;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
wire [7:0] rx_data;
wire data_line;
wire rx_done;
wire rx_collecting_data;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing... | 7.336225 |
module testingISR;
// Inputs
reg clock;
reg resetn;
reg [7:0] stream_active;
// Outputs
wire [7:0] i_s_request;
// Instantiate the Unit Under Test (UUT)
ion_sensor_requester uut (
.clock(clock),
.resetn(resetn),
.stream_active(stream_active),
.i_s_request(i_s_request)
);
... | 6.799413 |
module TestingKeyboard;
// Inputs
reg CLK;
reg PS2_CLK;
reg PS2_DATA;
// Outputs
wire scan_err;
wire [10:0] scan_code;
wire [3:0] COUNT;
wire TRIG_ARR;
wire [7:0] CODEWORD;
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
Keyboard uut (
.CLK(CLK),
.PS2_CLK(PS2_CLK),
... | 6.639893 |
module testingRC;
// Inputs
reg clock;
reg reset;
reg [7:0] tx_data;
reg start;
reg want_at;
reg RFIFO_rd_en;
parameter cpd = 10'd50;
parameter rc_timer_cap = 10'd12;
wire data_line;
// Outputs
wire byte_sent;
wire at_response_flag;
wire [15:0] RFIFO_out;
wire [7:0] RFIFO_wr_count;
wi... | 6.699752 |
module testingTimer;
// Inputs
reg clock;
reg l_timer;
reg resetn_timer;
parameter timer_cap = 10'd12;
// Outputs
wire timer_done;
// Instantiate the Unit Under Test (UUT)
timer_10bit uut (
.clock(clock),
.resetn_timer(resetn_timer),
.timer_active(l_timer),
.timer_final_val... | 7.474451 |
module testingUARTrx;
// Inputs
reg clock;
reg reset;
reg start;
reg [7:0] tx_data;
// Outputs
wire [7:0] rx_data;
wire data_line;
wire collecting_data;
wire rx_data_valid;
wire tx_done;
wire [3:0] i, n_i;
// parameter cpd = 10'd50;
// parameter timer_cap = 10'd12;
parameter cpd = 10'd1... | 7.386238 |
module testingUARTtx;
// Inputs
reg clock;
reg resetn;
reg start;
reg [7:0] ep01wireIn;
reg [9:0] cpd;
// Outputs
wire fpga_txd;
wire done;
wire l_tx_timer, rn_tx_timer;
wire [2:0] c;
wire [2:0] n;
// Instantiate the Unit Under Test (UUT)
UART_tx uut (
.clk(clock),
.resetn(res... | 7.857074 |
module testingUART_sender_for_testing;
// Inputs
reg clock;
reg reset;
reg user_data_on_line;
reg user_data_done;
reg [15:0] half_word;
// Outputs
wire tx_done;
wire tx_line;
// wire [2:0] fbc_curr, fbc_next;
// Instantiate the Unit Under Test (UUT)
UART_sender_for_testing uut (
// .fb... | 7.960251 |
module test_interface (
clk,
priv_sda,
priv_scl,
parallel_out,
byte_ready,
sop,
eot
);
input clk, priv_sda, priv_scl;
output [7:0] parallel_out;
wire [8:0] sda_out;
output byte_ready, sop, eot;
i2c_listen priv (
priv_sda,
sda_out,
priv_scl,
clk,
byt... | 6.515982 |
module testing_life ();
localparam N = 8;
reg clk;
reg nrst;
reg [(N*N)-1:0] seeds;
wire [(N*N)-1:0] cells;
wire [N-1:0] wcells[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
assign wcells[i] = cells[(N*(N-i))-1 : N*(N-1-i)];
end
endgenerate
GameOfLife #(
.N(N)
... | 6.568681 |
module testing_pc ();
wire [31:0] PC, PCNext, PCPlus4;
reg [31:0] PCTarget;
reg clk, reset, PCSrc;
mux2 #(32) pcnext (
PCNext,
PCPlus4,
PCTarget,
PCSrc
);
pc pc_inst (
PC,
clk,
reset,
PCNext
);
adder pc_plus4 (
PCPlus4,
PC,
32'd4
);
... | 6.947718 |
module testing_reg (
input wire clk,
reset,
input wire a,
b,
output wire c,
output wire seq_reg_tb,
seq_next_tb,
//TestBench signals below
output wire [1:0] state_tb,
output wire [1:0] testing_reg2_tb
//TestBench signals above
);
//state declaration
localparam [1:0] t... | 8.333389 |
module testing_reg_tb ();
//---------------------------------------------------------
// inputs to the DUT are reg type
reg CLOCK_50, reset, a, b;
//--------------------------------------------------------
// outputs from the DUT are wire type
wire testing_reg1;
wire [1:0] state_tb;
wire [1:0] testing_... | 6.833693 |
module TestInitializer #(
parameter WAIT_TIME = 100, // How long to wait after reset is deassereted.
parameter V_WAIT_TIME = WAIT_TIME // How long to wait after reset is deassereted.
) (
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous lo... | 7.433451 |
module key_gen (
in_key,
rcon,
out_key
);
input [0:127] in_key;
input [0:31] rcon;
output [0:127] out_key;
wire [0:127] out_key;
//shifting operation
wire [0:127] key, key2;
assign key[96:103] = in_key[104:111];
assign key[104:111] = in_key[112:119];
assign key[112:119] = in_key[120:12... | 8.515486 |
module testLcd_controller;
// Inputs
reg rst;
reg clk;
reg rs_in;
reg [7:0] data_in;
reg strobe_in;
reg [7:0] period_clk_ns;
// Outputs
wire lcd_e;
wire [3:0] lcd_nibble;
wire lcd_rs;
wire lcd_rw;
wire disable_flash;
wire done;
// Instantiate the Unit Under Test (UUT)
lcd_controller u... | 7.059745 |
module
*
*
* MIT License
*/
module LUATest;
// Inputs
reg [15:0] InputX;
reg [15:0] InputY;
reg Start;
// Outputs
wire [31:0] Address;
wire Ready;
`defClock(Clk, 2);
// Instantiate the Unit Under Test (UUT)
LUA #(
.DATA_WIDTH(16),
.BLOCK_SIZE(10)
) uut (
.Clk(Clk),
... | 7.860622 |
module: MapGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestMapGen;
// Inputs
reg clk;
reg reset;
// Outputs
wire finishedGen;
wire [47:0] logicMap;
// Instantiate t... | 7.298786 |
module debouncer (
O_reg_0,
PS2Clk_IBUF,
CLK50MHZ_BUFG
);
output O_reg_0;
input PS2Clk_IBUF;
input CLK50MHZ_BUFG;
wire CLK50MHZ_BUFG;
wire Iv;
wire O_i_1_n_0;
wire O_i_2_n_0;
wire O_reg_0;
wire PS2Clk_IBUF;
wire clear;
wire \count[0]_i_1_n_0 ;
wire \count[1]_i_1_n_0 ;
wire \count[... | 6.564102 |
module game_logic (
\state_reg[0]_0 ,
Q,
D,
E
);
output \state_reg[0]_0 ;
output [0:0] Q;
input [2:0] D;
input [0:0] E;
wire [2:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [2:0] state;
wire \state_reg[0]_0 ;
LUT2 #(
.INIT(4'hE)
) \data[7]_i_4 (
.I0(state[2]),
.I1(sta... | 6.517449 |
module: MatchingGame
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestMatchingGame;
// Inputs
reg clk;
reg rst;
reg btnU;
reg btnD;
reg btnL;
reg btnR;
reg btnS;
// Out... | 7.932909 |
module testmealy (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output reg z;
reg y, Y;
parameter A = 0, B = 1;
//Define the next state and output combinational circuits
always @(w, y)
case (y)
A:
if (w) begin
z = 0;
Y = B;
end else begin
z = ... | 6.591325 |
module
*
* MIT License
*/
module TestMiniCalc
#(
parameter INPUT_BIT_WIDTH = 8,
parameter INSTR_BIT_WIDTH = 4,
parameter CODE_INSTR_NOP = 4'b1111,
parameter CODE_INSTR_ADD_SUB = 4'b0111,
parameter CODE_INSTR_MIN_MAX = 4'b1011,
parameter CODE_INSTR_MUL = 4'b1101,
parameter C... | 7.131449 |
module
*
*
* MIT License
*/
module TestMinMax
#(
parameter INPUT_BIT_WIDTH = 32
);
// Inputs
`defClock(Clk, 2);
reg [INPUT_BIT_WIDTH-1:0] InputA;
reg [INPUT_BIT_WIDTH-1:0] InputB;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Max;
wire [INPUT_BIT_WIDTH-1:0] Min;
// Instantiate the Unit Under Test (UUT)
Min... | 7.860622 |
module PPR_Sim (
Clk,
Starter,
Aout,
Zout
);
input Clk, Starter;
output Aout, Zout;
wire Start;
sigLatch TestStart0 (
Clk,
Starter,
Start
);
reg mode = 0;
reg [15:0] Ctr = 0;
reg [4:0] TimeDiv = 0;
reg A = 0;
reg Z = 0;
assign Aout = A;
assign Zout = Z;
... | 7.397908 |
module is used to check the data flow in and out of the RX FIFO in Ozy_Janus.v,
through the NWire_xmit in Ozy to the NWire_rcv in Mercury. It should match the
defined FPGA Test Mode data stream. If not it generates
an error called tmc_err which can then be used to flash a code on an LED
*/
`timescale 1 ns/100 ... | 6.563484 |
module TestModule (
RSTb,
CLK,
REb,
OEb,
CEb,
ADDR,
USER_DATA
);
input RSTb, CLK, REb, OEb, CEb;
input [21:0] ADDR;
output [63:0] USER_DATA;
reg [63:0] internal_data;
wire [15:0] xxx;
assign USER_DATA = (CEb == 0 && OEb == 0) ? {xxx, swap_bits(xxx), ~swap_bits(xxx), ~xxx} : 64... | 6.575788 |
module testmoore (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
//Define the next state combinational circuit
always @(w, y)
case (y)
A:
if (w) Y = B;
else Y = A;
B:
if (w) Y = C;... | 6.845855 |
module TestMotherboard;
integer clock_count;
reg clk;
reg rst;
reg ps2_clk;
reg ps2_data;
wire hsync;
wire vsync;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;
Motherboard #(
.CLOCK_DIVIDER(1)
) motherboard (
//// input 100 MHz clock
.clk100Mhz(clk),
.rst(rst),
.ps2_... | 7.213054 |
module TestMPR #(
parameter bits = 32
) ();
reg clk, we_a, we_b;
reg [2:0] addr_a, addr_b;
reg [bits-1:0] d_in_a, d_in_b;
wire [bits-1:0] q_out_a, q_out_b;
integer i;
MPR #(bits) test (
clk,
we_a,
we_b,
addr_a,
addr_b,
d_in_a,
d_in_b,
q_out_a,
q_... | 6.762207 |
module: mul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testmul;
// Inputs
reg [31:0] data_a;
reg [31:0] data_b;
reg sign;
// Outputs
wire [63:0] data_c;
// Instantiate... | 6.736081 |
module
*
*
* MIT License
*/
module TestClaAdder;
// Inputs
reg [15:0] InputA;
reg [15:0] InputB;
reg Start;
// Outputs
wire [31:0] Product;
wire Ready;
`defClock(Clk, 2);
// Instantiate the Unit Under Test (UUT)
Multiplier #(
.DATA_WIDTH(16)
) uut (
.Clk(Clk),
.InputA(Inp... | 7.860622 |
module: mux2x32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testmux32;
// Inputs
reg [31:0] a0;
reg [31:0] a1;
reg s;
// Outputs
wire [31:0] y;
// Instantiate the Unit ... | 6.518985 |
module: mux4x32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testmux432;
// Inputs
reg [31:0] a0;
reg [31:0] a1;
reg [31:0] a2;
reg [31:0] a3;
reg [1:0] s;
// Outputs
wi... | 6.598578 |
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