code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TestMuxDecoder (
output [3:0] Y,
input [3:0] X,
input [1:0] S
);
wire w0, w1;
mux_4_1 mux_4_1_test (
w0,
X,
S
);
and (w1, w0, 1'b0);
decoder_2_4 decoder_2_4_test (
Y,
{w1, 1'b0}
);
endmodule
| 7.398303 |
module testmux_16;
reg[0:15] in;
reg[0:3] sel;
wire out;
mux16to1 mux(out, in sel)l
initial
begin
$monitor("in = %b| sel = %b | out = %b", in, sel, out);
end
initial
begin
in=16'b1000000000000000; sel=4'b0000;
end
endmodule
| 6.523727 |
module nandgate (
output s,
input a,
input b
);
assign s = ~(a & b);
endmodule
| 7.298658 |
module testNeuron (
input clk,
input reset
);
// Parameters
// Wires
wire [30:0] d_index; // <31,0>
// Registers
reg [31:0] bias_mem [0:1000]; // <32,0>
reg [31:0] counter; // <32,0>
reg [31:0] data_mem [0:1000]; // <32,0>
reg ... | 6.747162 |
module TestNewSituation1 ();
reg [23:0] Minisys_Switches;
wire [23:0] Minisys_Lights;
reg Minisys_Clock;
reg [4:0] Minisys_Button;
always begin
#1 Minisys_Clock = ~Minisys_Clock; //ⲿclock
end
TopAll use_main (
Minisys_Switches,
Minisys_Lights,
Minisys_Clock,
Minisys_Button
... | 6.676423 |
module testnorgate;
// ---------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end
... | 6.695863 |
module notgate (
s,
p
);
output [3:0] s;
input [3:0] p;
assign s[0] = ~p[0];
assign s[1] = ~p[1];
assign s[3:2] = ~p[3:2];
endmodule
| 7.575943 |
module testnotgate;
reg [3:0] a;
wire [3:0] s;
// instancia
notgate NOT1 (
s,
a
);
// parte principal
initial begin
$display("Exemplo 04_02 - xxx yyy zzz - 999999");
$display("Test NOT gate");
$display("\n~a = s\n");
a = 0000;
#1 $display("~%4b = %4b", a, s);
a = 1001... | 7.480879 |
module or3gate (
output s,
input a,
input b,
input c
);
assign s = (a | b | c);
endmodule
| 7.416224 |
module testor3entgate;
// ---------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
or3gate OR1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0;
... | 7.712876 |
module ougate (
s,
p,
q
);
output s;
input p, q;
assign s = p | q;
endmodule
| 6.763244 |
module nandgate (
s1,
p1,
q1,
r1
);
output s1;
input p1, q1, r1;
assign s = ~(p1 & q1 & r1);
endmodule
| 7.298658 |
module testPal ();
reg clk;
reg [7:0] data;
wire [11:0] rgb;
paletteROM #(
.PALETTEFILE("pal24bit.mem"),
.DEPTH(192)
) pal (
.clk (clk),
.data (data),
.color(rgb)
);
always #1 clk = !clk;
always begin
#4;
data <= data + 1;
end
initial begin
clk = 0;
da... | 6.801587 |
module debouncer (
O_reg_0,
PS2Clk_IBUF,
CLK50MHZ_BUFG
);
output O_reg_0;
input PS2Clk_IBUF;
input CLK50MHZ_BUFG;
wire CLK50MHZ_BUFG;
wire Iv;
wire O_i_1_n_1;
wire O_i_2_n_1;
wire O_reg_0;
wire PS2Clk_IBUF;
wire clear;
wire \count[0]_i_1_n_1 ;
wire \count[1]_i_1_n_1 ;
wire \count[... | 6.564102 |
module TEST_PATTERN #(
parameter addr_width = 14,
data_width = 4
) (
input wire clk,
input wire [addr_width-1:0] addr,
output reg [data_width-1:0] dout
);
`ifdef WITH_64K
(* ram_style = "distributed" *) reg [data_width-1:0] pattern[2**addr_width-1:0];
`else
(* ram_style = "block" *) reg [data_w... | 7.021295 |
module Sync_To_Count (
input i_Clk,
input rst,
input i_HSync,
input i_VSync,
output reg o_HSync = 0,
output reg o_VSync = 0,
output reg [10:0] o_Col_Count = 0,
output reg [10:0] o_Row_Count = 0
);
wire w_Frame_Start;
// ... | 7.118986 |
module testPC (
clock,
jumpValue,
branch,
imPC,
thisPC,
nextPC
);
input jumpValue, branch, clock;
input [31:0] imPC;
output [31:0] thisPC, nextPC;
//initialize PC
wire PCSrc;
// wire [31:0] nextJumpPC; //you could directly save it into latch input
wire [31:0] NextPC; //thisPC,
... | 6.841887 |
module testpc4_sim ();
reg clk, clrn, e;
wire [31:0] pc;
wire [31:0] pc4;
TextPC4 test (
clk,
clrn,
e,
pc,
pc4
);
reg [31:0] i;
always begin
clk = 0;
e = 0;
clrn = 1;
#5;
clrn = 0;
#5;
clrn = 1;
clk = 1;
#20;
clk = 0;
#5;
c... | 7.415504 |
module TestPIC16C57 ();
reg clk;
reg rst;
wire [`IO_A_WIDTH - 1:0] portAIO;
wire [`IO_B_WIDTH - 1:0] portBIO;
wire [`IO_C_WIDTH - 1:0] portCIO;
reg [3:0] stage;
reg [`IO_B_WIDTH - 1:0] value1;
reg [`IO_C_WIDTH - 1:0] value2;
assign portBIO = (stage == `STAGE_RESULTH || stage == `STAGE_RESULTV) ? 8... | 6.921519 |
module testProject (
input wire [3:0] a,
input wire [3:0] b,
output [3:0] z
);
assign z[0] = a[0] & b[0];
assign z[1] = a[1] | b[1];
assign z[2] = ~(a[2] & b[2]);
assign z[3] = a[3] ^ b[3];
endmodule
| 6.716973 |
module testqflop;
reg data, rst;
wire clk, ack, out;
reg expected;
q_flop qf (
.rst (rst),
.clk (clk),
.data(data),
.ack (ack),
.out (out)
);
q_clock qc (
.rst(rst),
.clk(clk),
.ack(ack)
);
initial begin
$dumpfile("testqflop.vcd");
$dumpvars(0, t... | 6.688958 |
module vc_TestRandDelaySink #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Max delay input
input logic [31:0] max_delay,
// Sink message interface
input logic val,
output logic rdy,
in... | 7.617553 |
module vc_TestRandDelaySource #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Max delay input
input logic [31:0] max_delay,
// Source message interface
output logic val,
input logic rdy,
... | 7.617553 |
module vc_TestRandDelayUnorderedSink #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Max delay input
input logic [31:0] max_delay,
// Sink message interface
input logic val,
output logic rd... | 7.617553 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
com... | 7.639545 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
com... | 7.639545 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
com... | 7.639545 |
module TestRegbit ();
reg CLK;
always #25 CLK = ~CLK;
wire q1;
wire q2;
wire [7:0] full_q;
reg reg_d;
reg [7:0] regFull_d;
reg Load;
regbit reg1 (
.clk(CLK),
.cclk(~CLK),
.d(reg_d),
.ld(Load),
.q(q1)
);
regbit regFull[7:0] (
.clk(CLK),
.cclk(~CLK),
... | 7.440739 |
module testRegfile ();
wire [31:0] now_pc;
wire [31:0] instruction;
wire [31:0] next_pc;
wire MemtoReg, RegWrite;
wire [2:0] MemRead;
wire [1:0] MemWrite;
wire [4:0] Aluop;
wire jalr;
wire Alusrc1, Alusrc2;
wire Add4;
reg clk, rstn;
wire [31:0] imm;
wire Branch;
wire [4:0] reg1 = instructi... | 7.117988 |
module testRegister;
reg clk;
reg rst;
reg en;
reg [15:0] in;
wire [15:0] out;
register reg1 (
.clk(clk),
.en (en),
.in (in),
.out(out),
.rst(rst)
);
always #5 clk = !clk;
initial begin
$dumpfile("../test.vcd");
$dumpvars;
end
initial begin
rst = 0;
... | 7.28777 |
module
*
*
* MIT License
*/
module TestRegMux4
#(
parameter INPUT_BIT_WIDTH = 8,
parameter BUS_WIDTH = 2
);
// Inputs
reg [INPUT_BIT_WIDTH-1:0] InputA;
reg [INPUT_BIT_WIDTH-1:0] InputB;
reg [INPUT_BIT_WIDTH-1:0] InputC;
reg [INPUT_BIT_WIDTH-1:0] InputD;
reg [BUS_WIDTH-1:0] Select;
// O... | 7.860622 |
module TESTROM #(
parameter length = 32,
parameter DATA_LENGTH = 256,
parameter ROMFILE = "TESTDATA.txt"
) (
input i_clk,
input [9:0] i_addr,
output reg [2*length-1:0] o_data
);
reg [2*length-1:0] mem[0:DATA_LENGTH-1];
initial begin
$readmemh(ROMFILE, mem);
end
always @(posedge i_clk... | 7.440455 |
module testrotor ();
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b... | 6.886134 |
module writer
# (parameter WIDTH=32)
(input clk,
input reset,
input full,
input almost_full,
input [1:0] id,
input [1:0] to,
input disableme,
output reg [WIDTH-1:0] dataOut,
output reg write);
//dataOut from writer is dataIn for fifo
//[disableme] disable =1, do not write.
reg [10:0] count;
reg [2:0] east;
reg [2:0... | 6.99624 |
module writer
# (parameter WIDTH=32)
(input clk,
input reset,
input full,
input almost_full,
input [1:0] id,
input [1:0] to,
input disableme,
output reg [WIDTH-1:0] dataOut,
output reg write);
//dataOut from writer is dataIn for fifo
//[disableme] disable =1, do not write.
reg [10:0] count;
reg [2:0] east;
reg [2:0... | 6.99624 |
module testSAPone;
wire [ 7:0] SAP_out;
wire [11:0] con;
wire [ 7:0] bus;
// wire clk_out, clr_out;
reg clk, clr_;
always #5 clk = ~clk;
SAPone sapone1 (
.SAP_out(SAP_out),
.con(con),
.bus(bus),
// .clk_out(clk_out),
// .clr_out(clr_out),
.clk(clk),
.clr_(clr... | 6.731384 |
module/SinglePulser.v"
`include "../module/SevenSegment.v"
module testSegment(
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output numsl0,
output numsl1,
output numsl2,
output numsl3,
input clk,
input dp1_raw);
wire dp1;
reg [3:0] num;
reg [9:0] clkcount;
wire clk... | 6.714526 |
module TestSegmentLedHexDecoder;
// Inputs
reg [3:0] HexDigit;
// Outputs
wire SegmentA;
wire SegmentB;
wire SegmentC;
wire SegmentD;
wire SegmentE;
wire SegmentF;
wire SegmentG;
reg [3:0] HexDigitOutput;
// Instantiate the Unit Under Test (UUT)
SegmentLedHexDecoder uu... | 6.832008 |
module testShift ();
wire [1:0] q1, q2;
reg clock, d;
shiftA s1 (
q1,
clock,
d
);
shiftB s2 (
q2,
clock,
d
);
always #10 clock = ~clock;
initial begin
#0 clock = 0;
d = 0;
#5 d = 1;
#35 d = 0;
#50 $finish;
end
always #8 d = ~d;
endmodule
| 6.545942 |
module
*
*
* MIT License
*/
module TestSignAddSub
#(
parameter INPUT_BIT_WIDTH = 8
);
// Inputs
`defClock(Clk, 2);
reg signed [INPUT_BIT_WIDTH-1:0] InputA;
reg signed [INPUT_BIT_WIDTH-1:0] InputB;
reg AddSubMode;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Result;
// Instantiate the Unit Under Test (UUT)
... | 7.860622 |
module
*
*
* MIT License
*/
module TestSignDivider
#(
parameter INPUT_BIT_WIDTH = 8
);
// Inputs
`defClock(Clk, 2);
reg [INPUT_BIT_WIDTH-1:0] Dividend;
reg [INPUT_BIT_WIDTH-1:0] Divider;
reg Sign;
// Outputs
wire Ready;
wire [INPUT_BIT_WIDTH-1:0] Quotient;
wire [INPUT_BIT_WIDTH-1:0] Remainder;
// ... | 7.860622 |
module
*
*
* MIT License
*/
module TestSimpleALU
#(
parameter INPUT_BIT_WIDTH = 8,
parameter INSTR_BIT_WIDTH = 5,
parameter FLAGS_COUNT = 1,
parameter CODE_INSTR_NOP = 5'b00000,
parameter CODE_INSTR_ADD = 5'b00001,
parameter CODE_INSTR_SUB = 5'b00010,
parameter CODE_INSTR_M... | 7.860622 |
module TestSituation1 ();
reg [23:0] Minisys_Switches;
wire [23:0] Minisys_Lights;
reg Minisys_Clock;
reg [4:0] Minisys_Button;
TopAll use_main (
Minisys_Switches,
Minisys_Lights,
Minisys_Clock,
Minisys_Button
);
initial begin
Minisys_Clock = 1'b0;
Minisys_Button = 5'b0000... | 6.510336 |
module vc_TestSource #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Source message interface
output logic val,
input logic rdy,
output logic [p_msg_nbits-1:0] msg,
// Goes high once all sou... | 8.859833 |
module testSPWMGenerator;
reg CLK, RST, CP, CCW;
reg [ 3:0] SubLevel;
wire [11:0] PWM;
initial begin
RST = 0;
#1 RST = 1;
end
initial begin
CLK = 0;
forever #1 CLK = !CLK;
end
initial begin
CP = 0;
forever #200 CP = !CP;
end
initial begin
CCW = 1;
end
initial be... | 7.134926 |
module: fibonacci_lfsr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testsss;
// Inputs
reg clk;
reg rst_n;
// Outputs
wire [4:0] data;
// Instantiate the Unit Under Test ... | 6.790868 |
module TestStagesTB;
reg clk;
reg signed [15:0] sample;
reg read_file;
integer infile, i, fout, fout2;
integer cycles;
always begin
#0 clk = 0;
#10 clk = 1;
cycles = cycles + 1;
#10;
end
reg valid;
reg s1_ena, s1_rst, s3_rst;
wire signed [15:0] s1_dsample;
wire s1_dvalid;
w... | 6.626433 |
module TestStepModule #(
parameter WORD_SIZE = 16,
ADDRESS_SIZE = 16
) (
input clk,
rst,
init,
start,
read_step,
input [WORD_SIZE-1:0] step_in,
input [ADDRESS_SIZE-1:0] x0_address,
x1_address,
output done,
proceed,
error,
output [WORD_SIZE-1:0] step_out
);
wire ... | 7.051862 |
module testSyncs ();
// Inputs
reg btnC, btnD, btnU, btnL, btnR;
reg [15:0] sw;
reg clkin;
// Output
wire [3:0] an;
wire dp;
wire [6:0] seg;
wire [15:0] led;
wire HS;
wire [3:0] vgaBlue;
wire [3:0] vgaGreen;
wire [3:0] vgaRed;
wire VS;
wire oops;
wire rgb_oops;
// You may need to r... | 6.882479 |
module check_the_sync_signals (
input myHS,
input myVS,
input correct_HS,
input correct_VS,
input clk,
input btnR,
output sync_error
);
// sync_error is high when actual and expected sync signals differ
assign sync_error = (myHS ^ correct_HS) | (myVS ^ correct_VS);
// SERRORS i... | 7.356019 |
module check_the_rgb_signals (
VB,
VG,
VR,
activeH,
activeV,
clk,
btnR,
rgb_error
);
input [3:0] VB, VG, VR;
input activeH, activeV;
input clk, btnR;
output rgb_error;
// rgb_error is high when any RGB output is high outside the active region
assign rgb_error = ((|VR) | (|V... | 6.912731 |
module __primitive_eq #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 == in1;
endmodule
| 7.008191 |
module __primitive_neq #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 != in1;
endmodule
| 7.979335 |
module __primitive_mod #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 % in1;
endmodule
| 7.339096 |
module __primitive_div #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 / in1;
endmodule
| 7.228843 |
module __primitive_not #(
parameter in0N = 1,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
output wire [out0N-1:0] out0
);
assign out0 = !in0;
endmodule
| 7.979335 |
module __primitive_mul #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 * in1;
endmodule
| 7.339096 |
module __primitive_add #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 + in1;
endmodule
| 7.439769 |
module __primitive_sub #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 - in1;
endmodule
| 7.686847 |
module __primitive_shiftl #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 << in1;
endmodule
| 7.686847 |
module __primitive_shiftr #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 >> in1;
endmodule
| 7.686847 |
module __primitive_gt #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 > in1;
endmodule
| 6.836738 |
module __primitive_gte #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 >= in1;
endmodule
| 6.836738 |
module __primitive_lt #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 < in1;
endmodule
| 7.145377 |
module __primitive_lte #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 <= in1;
endmodule
| 7.145377 |
module __primitive_complement #(
parameter in0N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
output wire [out0N-1:0] out0
);
assign out0 = ~in0;
endmodule
| 7.597658 |
module __primitive_bitand #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 & in1;
endmodule
| 7.206703 |
module __primitive_bitor #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 | in1;
endmodule
| 7.206703 |
module __primitive_bitxor #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 ^ in1;
endmodule
| 7.206703 |
module __primitive_ap01 #(
parameter in0N = 32,
parameter out1N = 32,
parameter out0N = 0
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire in0_valid,
output... | 7.439769 |
module __primitive_ap02 #(
parameter in0N = 32,
parameter out1N = 32,
parameter out2N = 32,
parameter out0N = 0
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input ... | 7.439769 |
module __primitive_ap20 #(
parameter in0N = 32,
parameter in1N = 32,
parameter in2N = 32,
parameter out0N = in0N + in1N + in2N
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0... | 7.439769 |
module __primitive_pushr1 #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire in0_valid,
out... | 7.068804 |
module __primitive_pushr2 #(
parameter in0N = 32,
parameter in1N = 32,
parameter in2N = 32,
parameter out0N = in0N + in1N + in2N
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1... | 7.068804 |
module transparent_buffer #(
parameter N = 32
) (
input wire clk,
input wire nrst,
input wire [N-1:0] in0,
input wire in0_valid,
output wire in0_ready,
output wire [N-1:0] out0,
output wire out0_valid,
input wire out0_ready
);
reg [N-1:0] data;
reg data_valid;
assign i... | 7.056174 |
module __primitive_write_array #(
parameter in0AN = 9,
parameter in0DN = 32,
parameter in1N = 32,
parameter in2N = 32,
parameter out0AN = 9,
parameter out0DN = 32
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
... | 7.019726 |
module __primitive_dup_array #(
parameter in0AN = 9,
parameter in0DN = 32,
parameter out0AN = 9,
parameter out0DN = 32,
parameter out1AN = 9,
parameter out1DN = 32
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
... | 7.228843 |
module tests_axil_map_w_r0 (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [32-1:0] in0,
input wire in0_valid,
output wire in0_ready,
output wire [33-1:0] out0,
output wire out0_valid,
... | 6.519507 |
module testTimePulseGen;
reg CLK, RST;
reg [4:0] SW;
initial begin
RST = 0;
#1 RST = 1;
end
initial begin
CLK = 0;
forever #1 CLK = !CLK;
end
initial begin
SW = 5'b00000;
#2000 SW = 5'b00010;
#2000 SW = 5'b00100;
#2000 SW = 5'b01000;
#2000 SW = 5'b10000;
end
wir... | 7.262232 |
module top (
input SCK, // arduino 13
input MOSI, // arduino 11
inout MISO, // arduino 12
input SSEL, // arduino 9
output flashMOSI,
input flashMISO,
output flashSCK,
output flashSSEL
);
assign flashMOSI = MOSI;
assign MISO = flashMISO;
assign flashSCK = SCK;
assign flas... | 7.233807 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testTop1;
// Inputs
reg Clk;
// Outputs
wire Ram2_EN;
wire Ram2_OE;
wire Ram2_WE;
wire [17:0] Ram2_address;
wire... | 7.115105 |
module TestTransmit ();
reg clk, TxD_start, Rst;
reg [7:0] TxD_data;
wire TxD, TxD_busy;
async_transmitter ts (
.clk(clk),
.TxD_start(TxD_start),
.TxD_data(TxD_data),
.Rst(Rst),
.TxD(TxD),
.TxD_busy(TxD_busy)
);
initial repeat (10000) #20 clk = ~clk;
initial begin... | 7.34831 |
module TestTriangle #(
parameter SIZE = 8'd108
) (
input clk100,
input nextFrame,
output reg [7:0] index,
input VertexBuffer_PreCalc_pop,
output reg VertexBuffer_PreCalc_empty,
output [7:0] count,
input [7:0] sin,
input [223:0] testdata,
output [223:0] VertexBuffer_PreCalc_ReadDa... | 6.782869 |
module TestTriangle (
input clk100,
input nextFrame,
output reg [223:0] PreCalc_TriangleFIFO_WriteData,
output reg PreCalc_TriangleFIFO_push,
input PreCalc_TriangleFIFO_wait
);
parameter RESET = 2'd0, PUSH1 = 2'd1, PUSH2 = 2'd2, DONE = 2'd3;
reg [1:0] State = 0;
reg [1:0] Next;
always @(po... | 6.782869 |
module testTubeControl ();
reg Sys_CLK;
reg Sys_RST;
reg [1:0] Key;
wire [7:0] SEG;
wire [1:0] COM;
wire [3:0] LED;
tubeControl U1 (
.Sys_CLK(Sys_CLK),
.Sys_RST(Sys_RST),
.Key(Key),
.SEG(SEG),
.COM(COM),
.LED(LED)
);
initial begin
Sys_CLK = 0;
Sys_RST = 1;
... | 6.752898 |
module
// Module Name: C:/Users/Rodrigo/Desktop/Universidad/Cuarto/Project/RecLeastSquares/RLS/testUART.v
// Project Name: RLS
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UARTmodule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created... | 6.999332 |
module
*
*
* MIT License
*/
module TestUnsignDividerComb
#(
parameter INPUT_BIT_WIDTH = 8
);
// Inputs
`defClock(Clk, 2);
reg [INPUT_BIT_WIDTH-1:0] Dividend;
reg [INPUT_BIT_WIDTH-1:0] Divider;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Quotient;
wire [INPUT_BIT_WIDTH-1:0] Remainder;
// Instantiate the Un... | 7.860622 |
module HVSync (
pixelClk,
HSync,
VSync,
R,
G,
B,
LY,
LineBuffer0,
LineBuffer1,
updateBufferSignal
);
input pixelClk;
output HSync;
output VSync;
output [3:0] R;
output [3:0] G;
output [3:0] B;
input [7:0] LY;
input [159:0] LineBuffer0;
input [159:0] LineBuffer1... | 6.979848 |
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