code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testVGAOutput1 (
input clk,
input reset,
input sw0,
input sw1,
input sw2,
output reg R,
output reg G,
output reg B,
output reg HSync,
output reg VSync
);
wire HSync0;
wire VSync0;
wire [9:0] Col;
wire [8:0] Row;
wire Col0;
wire Row0;
wire screen_active;
wi... | 7.445325 |
module xnorgate (
output s,
input a,
input b
);
assign s = ~(a ^ b);
endmodule
| 6.74222 |
module testxnorgate;
// ---------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
e... | 7.028584 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_01 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2;
assign temp1 = ~p & q;
assign temp2 = p & ~q;
assign s = temp1 | temp2;
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_02 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2;
and AND1 (temp1, ~p, q);
and AND2 (temp2, p, ~q);
assign s = temp1 | temp2;
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_03 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2;
and AND1 (temp1, ~p, q);
and AND2 (temp2, p, ~q);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xor XOR1 (s, a, b);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_04 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b"... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2, temp3;
not NOT1 (temp3, p);
not NOT2 (temp4, q);
and AND1 (temp1, temp3, q);
and AND2 (temp2, p, temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xor XOR1 (s, a, b);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_05 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b"... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p);
not NOT2 (temp4, q);
and AND1 (temp1, temp3, q);
and AND2 (temp2, p, temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a[0],
a[1]
);
initial begin : start
a[0] = 0;
a[1] = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_06 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na... | 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p[0]);
not NOT2 (temp4, p[1]);
and AND1 (temp1, temp3, p[1]);
and AND2 (temp2, p[0], temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a[0] = 0;
a[1] = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_07 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
... | 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire [0:3] temp;
not NOT1 (temp[2], p[0]);
not NOT2 (temp[3], p[1]);
and AND1 (temp[0], temp[2], p[1]);
and AND2 (temp[1], p[0], temp[3]);
or OR1 (s, temp[0], temp[1]);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a[0] = 0;
a[1] = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_08 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
... | 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p[0]);
not NOT2 (temp4, p[1]);
and AND1 (temp1, temp3, p[1]);
and AND2 (temp2, p[0], temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a = 2'b00;
end
// parte principal
initial begin : main
$display("Exemplo 05_09 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("... | 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p[0]);
not NOT2 (temp4, p[1]);
and AND1 (temp1, temp3, p[1]);
and AND2 (temp2, p[0], temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a = 0; // decimal
end
// parte principal
initial begin : main
$display("Exemplo 05_10 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$m... | 6.716539 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0011;... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
assign s = ((~a & b) | (a & ~b));
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Guia-01 - Pedro Tronbin - 410473");
$display("Test XOR gate");
$display("\n( (~a&b) | (a&~b) ) ... | 6.716539 |
module test_ly_2257_4 ();
reg clk_in; //输入
reg rst_n;
reg sel;
wire clk_out; //输出
parameter T = 20;
initial begin //初始化 系统复位
clk_in = 0;
rst_n = 0;
sel = 1;
#50 //等待50ns
rst_n = 1;
#400000 sel = 0;
end
always #(T / 2) clk_in = ~clk_in;
ly_2257_4 divider ( //例化
... | 7.423298 |
module top (
ena,
rst,
Tsync,
Tgdel,
Tgate,
Tlen,
Sync,
Gate,
Done,
prev_state,
prev_cnt,
prev_cnt_len
);
input ena, rst;
input [7:0] Tsync, Tgdel;
input [15:0] Tgate, Tlen, prev_cnt, prev_cnt_len;
input [4:0] prev_state;
output Sync, Gate, Done;
wire ena, rst... | 6.617164 |
module place_holder (
input CLK,
input RST,
output out
);
wire out_wire;
always @(posedge CLK) begin
if (RST) begin
out <= 0;
end else begin
out <= out + 1 + out_wire;
end
end
place_holder_2 test_1 (
.CLK(CLK),
.RST(RST),
.out(out_wire)
);
endmodule
... | 7.375365 |
module place_holder_2 (
input CLK,
input RST,
output out
);
always @(posedge CLK) begin
if (RST) begin
out <= 0;
end else begin
out <= out + 2;
end
end
endmodule
| 7.492135 |
module test_3bitAdder;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
reg [2:0] sum;
wire cy;
// Instantiate the Unit Under Test (UUT)
Adder3bit uut (
.A (A),
.B (B),
.sum(sum),
.cy (cy)
);
initial begin
// Initialize Inputs
A = 3'b000;
B = 3'b000;
#100 ... | 7.588542 |
module top (
ena,
rst,
Tsync,
Tgdel,
Tgate,
Tlen,
Sync,
Gate,
Done,
prev_state,
prev_cnt,
prev_cnt_len
);
input ena, rst;
input [7:0] Tsync, Tgdel;
input [15:0] Tgate, Tlen, prev_cnt, prev_cnt_len;
input [4:0] prev_state;
output Sync, Gate, Done;
wire ena, rst... | 6.617164 |
module segments_to_bitmap (
segments,
line,
bits
);
input [6:0] segments;
input [2:0] line;
output reg [4:0] bits;
always @(*)
case (line)
0:
bits = (segments[6]?5'b11111:0)
^ (segments[5]?5'b00001:0)
^ (segments[1]?5'b10000:0);
1: bits = (segments... | 7.160964 |
module test_7segment_top (
clk,
reset,
hsync,
vsync,
rgb
);
input clk, reset;
output hsync, vsync;
output [2:0] rgb;
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
video_sync_generator hvsync_gen (
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
... | 7.2367 |
module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UU... | 7.550078 |
module test_add16 ();
reg [15:0] a;
reg [15:0] b;
reg [15:0] ex_c;
wire [15:0] c;
add16 u1 (
c,
a,
b
);
initial begin
a = 16'b0000000000000000;
b = 16'b0000000000000000;
ex_c = 16'b0000000000000000;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
... | 6.886557 |
module test_add1bit ();
parameter CLOCK_CYCLE = 100;
parameter COUNTER_BIT_NUM = 3;
parameter SIMULATION_PERIOD = 500;
// signal defenition
reg clk;
reg reset;
reg [COUNTER_BIT_NUM -1:0] counter;
wire A;
wire B;
wire C_i;
wire O;
wire C_o;
assign A = counter[0];
assign B = counter[1];
... | 6.840184 |
module testbench_add32 ();
reg [31:0] A;
reg [31:0] B;
wire Overflow; //溢出判定
wire [31:0] result; //输出结果
reg isSub; //运算判定
reg isSign;
Add32 testadd32 (
Overflow,
result,
A,
B,
isSub,
isSign
);
initial begin
isSub = 1'b0;
isSign = 1'b1;
A = -100;
... | 7.504399 |
module test_add8;
parameter WIRE = 8;
reg [7:0] a, b;
reg cin, sub;
wire [7:0] s;
wire cout;
add_sub #(
.WIRE(WIRE)
) test_addX (
a,
b,
cin,
sub,
s,
cout
);
initial begin
$dumpfile("signal_add8.vcd");
$dumpvars;
$display("\t\ttime,\ta,\tb, ... | 7.211015 |
module TOP;
//ALU inputs
reg [15:0] a, b;
reg carry_in;
wire [15:0] sum;
wire [15:0] carry_out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 16'hfffe;
b = 16'h0001;
#`cycle //1
if(sum != (a +... | 7.259416 |
module: mux_16to1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_adder2bits();
// Inputs
reg [2:0] A, B; //
// Outputs
wire Co;
wire [1:0] S;
// Instantiate the Unit... | 7.639724 |
module test_adder_32bit;
reg [31:0] in_1;
reg [31:0] in_2;
wire [31:0] out_put;
wire carry_out;
adder_32bit adder (
in_1,
in_2,
out_put,
carry_out
);
initial begin
$monitor("in1 :%b | in2 :%b | out :%b | cout :%b", in_1, in_2, out_put, carry_out);
end
initial begin
... | 6.692392 |
module: mux_16to1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_adder_cascaded32();
// Inputs
reg [31:0] A, B;
// Outputs
wire Ov;
wire [31:0] S;
// Instantiate the ... | 7.639724 |
module Test_Addr_MUX;
// Inputs
reg CLK;
reg RST;
reg [15:0] HADDR_1;
reg [15:0] HADDR_2;
reg [1:0] SEL;
// Outputs
wire [15:0] HADDR;
// Instantiate the Unit Under Test (UUT)
Addr_MUX uut (
.CLK(CLK),
.RST(RST),
.HADDR(HADDR),
.HADDR_1(HADDR_1),
.HADDR_2(HADDR_2),
... | 6.878543 |
module test_addX;
parameter WIRE = 8;
reg [WIRE-1:0] a, b;
reg cin;
wire [WIRE-1:0] out;
wire cout;
addX #(
.WIRE(WIRE)
) addX_inst (
a,
b,
cin,
out,
cout
);
initial begin
$dumpfile("signal_addX.vcd");
$dumpvars;
$display("\t\tti... | 6.945899 |
module test_add_4;
reg [3:0] a0; // add oprand
reg [3:0] a1;
reg carry_in;
wire [3:0] sum; // the sum of a0 and a1
wire carry_out;
add_4 instance_add_4 (
.in_0(a0),
.in_1(a1),
.cin (carry_in),
.out (sum),
.cout(carry_out)
);
initial begin
a0 = 4'b000... | 6.655923 |
module test_add_mul16 (
input [15:0] a,
input [15:0] b,
input [15:0] c,
output [15:0] out
);
assign out = (a + b) * c;
endmodule
| 6.581066 |
module test_aes_16;
// Inputs
reg clk;
reg [15:0] state;
reg [15:0] key;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
aes_16 uut (
.clk (clk),
.state(state),
.key (key),
.out (out)
);
initial begin
$dumpfile("aes_16.vcd"); // name of the d... | 6.596262 |
module test_ahb_lite_mem;
`include "sdr_parameters.vh"
`include "ahb_lite.vh"
ahb_lite_mem mem (
.HCLK (HCLK),
.HRESETn(HRESETn),
.HADDR (HADDR),
.HBURST (HBURST),
.HSEL (HSEL),
.HSIZE (HSIZE),
.HTRANS (HTRANS),
.HWDATA (HWDATA),
.HWRITE (HWRITE),
... | 6.737862 |
module test_ahb_lite_sdram;
`include "sdr_parameters.vh"
`include "ahb_lite.vh"
wire CKE;
wire CSn;
wire RASn;
wire CASn;
wire WEn;
wire [ADDR_BITS - 1 : 0] ADDR;
wire [ BA_BITS - 1 : 0] BA;
wire [... | 6.737862 |
module Test_DADDA_8bit_All_Input;
//Parameters
parameter in_size = 15;
parameter [in_size:0] zero = 0;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg [6:0] M;
//reg app;
reg clk = 0;
reg [in_size:0] MUL_exact;
reg [in_size:0] MUL_apprx;
integer RepFile;
real error = 0;
real error_distance = 0;
... | 7.889401 |
module test_alucontrol;
// Inputs
reg [5:0] instruction_function;
reg [1:0] ALUOp;
// Outputs
wire [3:0] alu_control;
// Instantiate the Unit Under Test (UUT)
ALUControl_32 uut (
.instruction_function(instruction_function),
.ALUOp(ALUOp),
.alu_control(alu_control)
);
initial be... | 6.6455 |
module: alu_control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_alu_control;
// Inputs
reg [3:0] AluOp1;
reg [1:0] Flag1;
// Outputs
wire [2:0] AluCtrl1;
// Instant... | 6.672598 |
module test_ALU_reg (
data_in,
mux_sel,
seg_reg,
adr_reg_a,
adr_reg_b,
op_in,
we,
clk,
a_reset_l,
valid_o,
data_o
);
parameter seg_reg_wl = 4; // segment register width
parameter adr_reg_wl = 4; // address register width
parameter op_wl = 8;
input [15:0] data_in;... | 6.776816 |
module test_amoa_8x8p1_rt8_apx2;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
amoa_8x8p1_rt8_apx2 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1... | 7.831084 |
module test_amoa_8x8p2_rt8_apx2;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
amoa_8x8p2_rt8_apx2 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1... | 7.831084 |
module test_amoa_8x8p2_rt8_apxe4;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
amoa_8x8p2_rt8_apxe4 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(... | 7.831084 |
module test_mux_2x1;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
wire [4:0] Y; //Las salidas deben ser tipo wire
reg S;
parameter sim_time = 100;
amount_selector sel (
Y,
S,
I0
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simu... | 6.929887 |
module test_and (
input A,
input B,
output C
);
assign C = A & B;
endmodule
| 7.005269 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire in1_buf;
wire in2_buf;
sky130_fd_sc_hd__and2_1 icg (
.A(in1_buf),
.B(in2_buf),
.X(out)
);
sky130_fd_sc_hd__buf_1 gin1 (
... | 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire in1_buf, in1_not;
wire in2_buf, in2_not;
wire out_not;
sky130_fd_sc_hd__inv_1 inv1 (
.A(in1),
.Y(in1_not)
);
sky130_fd_sc_hd__in... | 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire x, y;
wire z0, z1;
wire z;
wire in1_buf;
wire in2_buf;
sky130_fd_sc_hd__inv_1 inv1 (
.A(in1),
.Y(in1_buf)
);
sky130_fd_sc_hd... | 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire x, y;
wire z0, z1, z2, z3, z4, z5, z6, z7, z8, z9, z10;
wire out1, out2, out3, out4, out5;
wire in1_buf;
wire in2_buf;
// Compute x = NOT(inp... | 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire x, y;
wire z0, z1, z2, z3, z4, z5, z6, z7, z8, z9, z10;
wire out1, out2, out3, out4, out5;
wire in1_buf;
wire in2_buf;
// Compute x = NOT(inp... | 6.705495 |
module: approx_mul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_approx;
// Inputs
reg clk;
reg reset;
reg [15:0] in_a;
reg [15:0] in_b;
// Outputs
wire [4:0] shift_a... | 6.677602 |
module test_arbiter_rr;
// Parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire ... | 6.979721 |
module test_ariSHIFT;
reg [15:0] IN;
reg RIGHT;
wire [15:0] OUT;
ari_SHIFT shift0 (
OUT,
IN,
RIGHT
);
initial begin
IN = 16'b1000000000000010;
RIGHT = 1;
#100 RIGHT = 0;
#100 IN = 16'b0000000111000010;
#100 RIGHT = 1;
end
endmodule
| 6.828039 |
module test_arp_cache;
// Parameters
parameter CACHE_ADDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg query_request_valid = 0;
reg [31:0] query_request_ip = 0;
reg query_response_ready = 0;
reg write_request_valid = 0;
reg [31:0] write_request_ip = 0;
reg ... | 7.894332 |
module testfixture;
//`define direction_matrix "../dat/compare.dat"
//`define H_matrix "../dat/H.dat"
`define sequence "../dat/BinaryInput.dat"
`define data_size "../dat/data_size.dat"
reg clk_i = 0;
reg rst_n;
reg [`BP_WIDTH-1:0] S;
reg [`BP_WIDTH-1:0] T;
reg s_update;
wire [`CALC_WIDTH-1:0] max_... | 6.999147 |
module datamemory (
write,
addr,
datain,
dataout,
clk,
reset
);
input [31:0] datain;
input [15:0] addr;
input write, clk, reset;
output [31:0] dataout;
reg [31:0] mem[63:0];
assign dataout = mem[addr];
always @(posedge clk) begin
if (reset) begin
mem[0] <= 32'b0000000... | 7.533611 |
module test_asm18 (
input clk_50M,
output reg [7:0] ledout,
input uart_rx_pin,
output reg uart_tx_pin,
input key_86,
input key_87
);
localparam WORD_SIZE = 18;
wire clock_proc;
logic [17:0] data_address_a = 0;
logic [17:0] data_address_b = 0;
logic [17:0] data_write_a = 0;
logic ... | 7.135502 |
module comp (
A1,
A2,
Z
);
//ports
input A1;
input A2;
output Z;
//wires
wire A1;
wire A2;
wire Z;
wire [7:0] A_buss2;
wire [1:0] A_buss;
wire B1;
wire B2;
//assignments
assign Z = A2;
assign {Z, B1} = {A2, A1};
assign A_buss = {A2, A1};
assign A_buss = {2{B1}};
assig... | 6.646188 |
module TEST_ASYNC_FIFO ();
reg wclk, rclk, rst;
localparam [32-1:0] WINT = 514, // 20,// 97,
RINT = 500, //100,//101,
RSTWIDTH = (WINT > RINT ? WINT : RINT) * 2 * 10;
initial begin
$display("WINT:%d, RINT:%d, RSTWIDTH:%d", WINT, RINT, RSTWIDTH);
end
initial begin
wclk = 1'b1;
forever #WIN... | 6.673306 |
module test_axil_cdc;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter STRB_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg s_clk = 0;
reg s_rst = 0;
reg m_clk = 0;
reg m_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] s_axil_awaddr = 0;
reg [2:0] s_axil_awprot ... | 6.989709 |
module test_axil_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter STRB_WIDTH = DATA_WIDTH / 8;
parameter PIPELINE_OUTPUT = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] s_axil_awaddr = 0;
reg [2:0] s_axil_awprot = 0;
... | 7.467084 |
module test_axis_adapter_64_8;
// Parameters
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 8;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE... | 8.183024 |
module test_axis_adapter_8_64;
// Parameters
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE... | 8.183024 |
module test_axis_arb_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE =... | 7.982128 |
module test_axis_arb_mux_4_64;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENAB... | 7.982128 |
module test_axis_async_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = ... | 8.12555 |
module test_axis_async_fifo_64;
// Parameters
parameter DEPTH = 32;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WID... | 8.12555 |
module test_axis_async_fifo_adapter_64_8;
// Parameters
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 8;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DAT... | 8.12555 |
module test_axis_async_fifo_adapter_8_64;
// Parameters
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DAT... | 8.12555 |
module test_axis_async_frame_fifo;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_... | 8.12555 |
module test_axis_async_frame_fifo_64;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter D... | 8.12555 |
module test_axis_baser_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter USER_WIDTH = (PTP_TS_ENABLE... | 6.902249 |
module test_axis_baser_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
para... | 6.902249 |
module test_axis_broadcast_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH... | 7.078718 |
module test_axis_crosspoint_4x4;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE... | 7.920432 |
module test_axis_crosspoint_4x4_64;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_EN... | 7.920432 |
module test_axis_demux_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1... | 8.270314 |
module test_axis_demux_4_64;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE... | 8.270314 |
module test_axis_eth_fcs;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg ... | 8.161317 |
module test_axis_eth_fcs_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0... | 8.161317 |
module test_axis_eth_fcs_check;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire... | 8.161317 |
module test_axis_eth_fcs_check_64;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;... | 8.161317 |
module test_axis_eth_fcs_insert;
// Parameters
parameter ENABLE_PADDING = 0;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
... | 8.161317 |
module test_axis_eth_fcs_insert_64;
// Parameters
parameter ENABLE_PADDING = 0;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tus... | 8.161317 |
module test_axis_eth_fcs_insert_64_pad;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis... | 8.161317 |
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