code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_card_simple #(
H_RES = 640
) (
input wire signed [15:0] i_x,
output wire [7:0] o_red,
output wire [7:0] o_green,
output wire [7:0] o_blue
);
localparam HW = H_RES >> 3; // horizontal colour width = H_RES / 8
// Bands
wire b0 = (i_x >= 0) & (i_x < HW);
wire b1 = (i_x >= HW) & (... | 8.417137 |
module test_card_squares #(
H_RES = 640,
V_RES = 480
) (
input wire signed [15:0] i_x,
input wire signed [15:0] i_y,
output wire [7:0] o_red,
output wire [7:0] o_green,
output wire [7:0] o_blue
);
localparam HR = H_RES; // horizontal resolution (pixels)
localparam VR = V_RES; // verti... | 7.855842 |
module test_case ( /*AUTOARG*/);
/*
`define TB testbench_axi_master_bfm
`define MASTER `TB.master
`define SLAVE `TB.slave
`define MEMORY `SLAVE.memory
*/
`define TB testbench_my_slave
`define MASTER `TB.master
`define SLAVE `TB.slave
`define MEMORY `SLAVE.my_full_ip_v1_0_S00_AXI_inst.mem_data_out
initial... | 6.939549 |
module test_case_alu (
output reg clock,
output reg enable,
output reg [ 2:0] funct3,
output reg [ 6:0] funct7,
output reg [31:0] register_data_1,
output reg [31:0] register_data_2,
input [31:0] register_data_out
);
parameter CLOCK_PERIOD = 1;
always begin
#CLOCK... | 7.296998 |
module test_alu_base (
output reg clock,
output reg enable,
output reg [ 2:0] funct3,
output reg [31:0] register_data_1,
output reg [31:0] register_data_2,
input [31:0] register_data_out
);
parameter CLOCK_PERIOD = 1;
always begin
#CLOCK_PERIOD clock = !clock;
end... | 7.310016 |
module test_case_memory (
output reg clock,
output reg read_enable,
output reg [31:0] read_address,
input [31:0] read_value,
output reg write_enable,
output reg [31:0] write_address,
output reg [31:0] write_value
);
reg clock2;
initial begin
clock = 0;
clock2 = 0;
read_enab... | 6.789641 |
module test_register_file (
output reg clock,
output reg reset,
output reg write_enable,
output reg [4:0] rs1,
output reg [4:0] rs2,
output reg [4:0] register_write_select,
output reg [31:0] register_data_write,
input [31:0] register_data_1,
input [31:0] register_data_2
);
paramet... | 7.267008 |
module test_case_rv32 (
output reg clock,
output reg enable
);
parameter CLOCK_HALF_PERIOD = 1;
parameter CLOCK_PERIOD = 2;
reg [31:0] cycle_counter;
initial begin
$dumpfile("test_case_rv32.vcd");
$dumpvars();
$monitorh(
"counter=%04d,pc=%08x,instruction=%08x,r0=%08x,r1=%08x,r2=%0... | 6.531752 |
module: pet2001cass232
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cass232;
// Inputs
reg rx232;
reg cass_motor_n;
reg cass_write;
reg clk;
reg re... | 6.529996 |
module test_cbc_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CBC_dec e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("cbc_enc.txt", msg);
//$... | 7.350289 |
module test_cbc_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CBC_enc e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("binary.txt", msg);
//$d... | 7.771286 |
module test_pa2_fsm;
// DUT I/O
logic clock;
logic reset;
logic valid;
logic [3:0] num;
logic [3:0] seq;
logic hit;
logic [3:0] cnt, n_cnt;
STATE state, n_state;
// Testbench variables
logic [3:0] int_cnt; // Keeps track of # hits on input
logic [3:0] hit_cnt; // Used ... | 7.709212 |
module top;
wire [63:0] x = 64'hDEADBEEFBAADF00D;
wire [31:0] k = 64'h01234567;
wire [63:0] y;
fcell fc (
.IN (x),
.KEY(k),
.OUT(y)
);
initial begin
$display("x = %h", x);
$display("k = %h", k);
end
wire [63:0] x_dec;
ifcell ifc (
.IN (y),
.KEY(k),
.O... | 6.919222 |
module test_cfb_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CFB_enc e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("binary.txt", msg);
//$d... | 7.437826 |
module test_cfb_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CFB_dec e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("cfb_enc.txt", msg);
//$... | 7.121331 |
module test_char_send (
input clk,
input rst_n,
input [23:0] send_str,
output RsTx
);
reg [30:0] time_cnt;
reg [ 7:0] tx_data_in;
reg tx_en;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) time_cnt <= 'b0;
else if (time_cnt == 50_000_000) //time is 3s
time_cnt <= '... | 6.740264 |
module test_cla_8bits;
reg [7:0] m, n;
reg cin;
wire [7:0] sum;
wire cout;
cla_8bits tt (
m,
n,
cin,
cout,
sum
);
initial begin
#40 cin = 1;
m = 8'b10101100;
n = 8'b11010101;
#40 cin = 1;
m = 8'b10001111;
n = 8'b10001111;
#40 cin... | 7.384118 |
module: cla_adder_16bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cla_adder_16bit;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg C0;
// Outputs
wire [15:0] S;
wire C1... | 6.812775 |
module: cla_adder_4bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cla_adder_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg C0;
// Outputs
wire [3:0] S;
wire C4, Pg,... | 7.376897 |
module: normClkGenerator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`default_nettype none
module test_clk;
// Inputs
reg clk_in;
reg reset_n;
// Outputs
wire... | 6.502821 |
module: clk_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_clk_divider;
localparam T = 10;
// Inputs
reg clk_in;
reg rst;
// Outputs
wire clk_out;
// Instantia... | 6.64719 |
module test_clock_tb;
wire clk;
test_clock uut (clk);
initial begin
$dumpfile("test_clock_tb.vcd");
$dumpvars(0, test_clock_tb);
#10 $finish;
$display("Test Complete");
end
endmodule
| 7.479708 |
module test_cmera (
input wire CLK_IN, //ϵͳʱ
input wire RST_N, //λ,Ĭ
//camera
input wire CSI_PCLK, //CSIʱ
output wire CSI_XCLK, //CSIϵͳʱ
input wire CSI_HREF, //ͬ
input wire CSI_VSYNC, //֡ͬ
output wire CSI_PWDN, //ģʽ
output wire CSI_RST, //λ
output wire CSI_SOIC, //SCCB,ʱ... | 6.936452 |
module test_cmp8;
reg [7:0] a, b;
wire eq, less, more;
cmp #(
.WIRE(8)
) test_cmp (
a,
b,
eq,
more,
less
);
initial begin
$dumpfile("signal_cmp.vcd");
$dumpvars;
$display("\t\ttime, \ta, \tb, \teq, \tmore, \tless\n");
$monitor("%d \t%d \t%d \t%b \t%b \t... | 7.668232 |
module test_comb (
input clk,
resetn,
load,
go,
input [2:0] color_in,
input [6:0] coordinate,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
wire ld_x, ld_y, ld_color, writeEn;
control c0 (
.clk(clk),
.resetn(resetn),
.load(load),
.go(... | 6.882408 |
module test_combined;
// Inputs
reg sel;
reg clock;
reg reset;
reg signed [2:0] taps;
reg [7:0] normal_input;
// Outputs
wire [7:0] error;
wire [7:0] total_error;
wire [31:0] count;
// Instantiate the Unit Under Test (UUT)
test_control uut (
.sel(sel),
.clock(clock),
.reset(... | 7.243963 |
module And2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 A... | 7.022857 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Mux2x1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire Mux2_inst0_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
assign O = {Mux2_inst0_O};
endmodule
| 6.963017 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_DFF_inst1_Q)
);
assign O = {SB_DFF_inst1_Q,... | 6.626169 |
module Counter2 (output [1:0] O, input CLK);
wire [1:0] Add2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2 Add2_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_inst0_O));
Register2 Register2_inst0 (.I(Add2_inst0_O), .O(Register2_inst0_O), .CLK(CLK));
assign O = Register2_inst0_O;
endmodule
| 7.166421 |
module Counter1 (output [0:0] O, input CLK);
wire [0:0] Add1_inst0_O;
wire [0:0] Register1_inst0_O;
Add1 Add1_inst0 (.I0(Register1_inst0_O), .I1(1'd1'), .O(Add1_inst0_O));
Register1 Register1_inst0 (.I(Add1_inst0_O), .O(Register1_inst0_O), .CLK(CLK));
assign O = Register1_inst0_O;
endmodule
| 6.856271 |
module Decode_0_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.171146 |
module Decode_1_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h2)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.999049 |
module Decode_2_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h4)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.241425 |
module Decode_3_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.911161 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 A... | 7.022857 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire Mux2_inst0_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
assign O = {Mux2_inst0_O};
endmodule
| 6.963017 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module Counter2 (output [1:0] O, input CLK);
wire [1:0] Add2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2 Add2_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_inst0_O));
Register2 Register2_inst0 (.I(Add2_inst0_O), .O(Register2_inst0_O), .CLK(CLK));
assign O = Register2_inst0_O;
endmodule
| 7.166421 |
module Counter1 (output [0:0] O, input CLK);
wire [0:0] Add1_inst0_O;
wire [0:0] Register1_inst0_O;
Add1 Add1_inst0 (.I0(Register1_inst0_O), .I1(1'd1'), .O(Add1_inst0_O));
Register1 Register1_inst0 (.I(Add1_inst0_O), .O(Register1_inst0_O), .CLK(CLK));
assign O = Register1_inst0_O;
endmodule
| 6.856271 |
module Decode_0_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.171146 |
module Decode_1_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h2)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.999049 |
module Decode_2_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h4)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.241425 |
module Decode_3_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.911161 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 A... | 7.022857 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire Mux2_inst0_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
assign O = {Mux2_inst0_O};
endmodule
| 6.963017 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module Counter2 (output [1:0] O, input CLK);
wire [1:0] Add2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2 Add2_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_inst0_O));
Register2 Register2_inst0 (.I(Add2_inst0_O), .O(Register2_inst0_O), .CLK(CLK));
assign O = Register2_inst0_O;
endmodule
| 7.166421 |
module Counter1 (output [0:0] O, input CLK);
wire [0:0] Add1_inst0_O;
wire [0:0] Register1_inst0_O;
Add1 Add1_inst0 (.I0(Register1_inst0_O), .I1(1'd1'), .O(Add1_inst0_O));
Register1 Register1_inst0 (.I(Add1_inst0_O), .O(Register1_inst0_O), .CLK(CLK));
assign O = Register1_inst0_O;
endmodule
| 6.856271 |
module test_complex_gate;
reg e1, e2, e3;
wire out_aoi, out_ao;
gate_aoi aoi_inst (
out_aoi,
{e3, e2, e1}
);
gate_ao ao_inst (
out_ao,
{e3, e2, e1}
);
initial begin
$dumpfile("signal_test_serial_gate.vcd");
$dumpvars;
$monitor("time %d\ne1\t%b\ne2\t%b\ne3\t%b\naoi\t%b... | 7.497789 |
module test_contador4;
wire [3:0] cuenta, cuenta1;
wire enext, enext1;
reg e;
reg nr, ck;
cont4 dut (
.Cuenta(cuenta),
.Enext(enext),
.nR(nr),
.E(e),
.CK(ck)
);
cont4 dut1 (
.Cuenta(cuenta1),
.Enext(enext1),
.nR(nr),
.E(enext),
.CK(ck)
);
i... | 6.891576 |
module test_control ();
event error_detected;
integer error_count;
reg verbose_msg;
// initialize debug variables
initial begin
error_count = 0;
verbose_msg = 0;
end
// count the number error
always @(error_detected) begin
error_count = error_count + 1;
end
// enabling/disabl... | 6.84566 |
module: controlclk
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_controlclk;
// Inputs
reg Clk;
// Outputs
wire clk_out;
// Instantiate the Unit Under Test (UUT)
cont... | 6.885783 |
module test_Controle;
reg [2:0] OPcode;
reg bit_menos_sig;
wire halt;
wire addi;
wire jump;
wire beq;
wire dadoEscrito;
wire acessarMemoria;
wire imediato;
wire escreveMemoria;
wire leMemoria;
wire [1:0] operacaoULA;
wire escreveRegistrador;
wire lw;
initial begin
$display("add");
... | 6.967645 |
module test_Control_Unit ();
parameter word_size = 10, op_size = 4, state_size = 4;
parameter address_size = 8, data_size = 8;
parameter src0_size = 2, src1_size = 2, dest_size = 2, Sel1_size = 3, Sel2_size = 3;
// State Codes
// parameter S_idle = 0, S_fet1 = 1, S_fet2 = 2, S_dec = 3;
// parameter S_ex1 ... | 7.937864 |
modules for testbench
// notes :
//
// Copyright Illinois Institute of Technology
//
// Top level stimulus module
module stimulus;
reg [15:0] endangle;
reg [3:0] addr;
reg load;
reg clock;
reg Clk;
wire [15:0] sin, cos;
wire [15:0] data, currentangle;
... | 6.862012 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width2 (
input [1:0] in_data[1:0],
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
wire [1:0] coreir_commonlib_mux2x2_inst0_in_data[1:0];
assign coreir_commonlib_mux2x2_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x2_inst0_in_data[0] = I0;
com... | 7.816223 |
module Mux2xOutBit (
input I0,
input I1,
input S,
output O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__... | 8.564631 |
module test_correct_io (
G1,
G2,
G3,
G4,
G5_0,
G5_1,
G17,
G18,
G19,
G20,
G21,
G22_0,
G22_1
);
// Comments Inside Module
input G1, G2, G3, G4;
/* Comments Inside Module */
input G5_0, G5_1;
output G17, G18, G19, G20, G21;
output G22_0, G22_1;
wire G8_0, ... | 6.559825 |
module test_timer;
// Inputs
reg clk;
reg clrn;
reg loadn;
reg enable;
reg [3:0] data;
// Output
wire [3:0] out;
wire tc;
wire zero;
// Instantiate the Timer
counter_mod10 uut (
.clock (clk),
.clrn (clrn),
.loadn (loadn),
.enable(enable),
.data (data),
.one... | 7.012348 |
module test_timer;
// Inputs
reg clk;
reg clrn;
reg loadn;
reg enable;
reg [3:0] data;
// Output
wire [3:0] out;
wire tc;
wire zero;
// Instantiate the Timer
counter_mod6 uut (
.clock (clk),
.clrn (clrn),
.loadn (loadn),
.enable(enable),
.data (data),
.ones... | 7.012348 |
module: counters
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_counters;
// Inputs
reg clk;
reg reset;
reg uart_REC_dataH;
// Outputs
wire [7:0] cntb;
wire uart_XMIT_... | 7.236042 |
module test_counter_4;
reg clk;
reg rst_n;
wire [3:0] q;
counter_4 U0 (
q,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.546598 |
module test_counter_47 ();
reg clk = 0, en = 1, clear = 0, set = 0, add = 1;
reg [5:0] num_i = 1;
wire [5:0] num_o;
counter_47 c47 (
clk,
en,
clear,
set,
add,
num_i,
num_o
);
initial
fork
#23 clear = 1;
#33 clear = 0;
#43 en = 0;
#53 en = 1;
... | 6.546598 |
module test_counter_4_1hz;
wire [3:0] b;
reg clk, rst_n;
counter_4_1hz U0 (
b,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.546598 |
module test_counter_down_30;
wire [7:0] cnt;
reg clk;
reg rst_n;
counter_down_30 U0 (
cnt,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.546598 |
module stream_gen (
input i_clk,
input i_enable,
input i_send_esc,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = i_send_esc ? 8'd27 : d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_vali... | 6.890266 |
module test_cpstr_desc;
reg clk = 0;
reg rst = 0;
reg en = 0;
wire [7:0] src_data;
wire src_valid;
wire src_ready;
wire [7:0] dst_data;
wire dst_valid;
reg dst_ready = 0;
wire [7:0] esc_data;
wire esc_valid;
reg esc_ready = 0;
reg send_esc = 0;
stream_gen gen (
.i_clk(clk),
... | 6.951511 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = (d[2:0] < 5) ? (d + 1) : 8'd27;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) b... | 6.890266 |
module test_cpstr_esc;
reg clk = 0;
reg rst = 0;
reg en = 0;
wire [7:0] src_data;
wire src_valid;
wire src_ready;
wire [7:0] dst_data;
wire dst_valid;
reg dst_ready = 0;
reg [7:0] esc_data = 0;
reg esc_valid = 0;
wire esc_ready;
stream_gen gen (
.i_clk(clk),
.i_enable(en),
... | 7.697817 |
module stream_gen (
input i_clk,
input i_enable,
input i_send_esc,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = i_send_esc ? 8'd27 : d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_vali... | 6.890266 |
module: crc16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_crc16;
// Inputs
reg clk;
reg rst;
reg en;
reg data;
// Outputs
wire [15:0] crc;
// Instantiate the Unit... | 6.832425 |
module test_crc1632p8;
// Inputs
reg iocs;
reg [2:0] ioaddr;
reg [15:0] din;
reg iowr;
reg iord;
reg clk;
reg clk2x;
reg rst;
// Outputs
wire [15:0] dout0, dout1;
// Instantiate the Units Under Test (UUT)
crc1632p8 uut0 (
.iocs(iocs),
.ioaddr(ioaddr),
.din(din),
.iow... | 6.502039 |
module: control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ctrl;
// Inputs
reg [5:0] op;
reg [5:0] funct;
// Outputs
wire RegDst;
wire RegWrite;
wire ALUSrc;
wire... | 7.090636 |
module TOP;
//ALU inputs
reg [31:0] a, b;
reg [2:0] op;
reg CF_dataforwarded;
reg AF_dataforwarded;
wire [31:0] out;
wire [31:0] flags;
reg error;
reg error_free;
initial
begin
CF_dataforwarded = 0;
AF_dataforwarded = 0;
error_free = 1;
... | 7.259416 |
module test_dac8551;
reg clk = 0;
reg rst = 0;
reg wr = 0;
reg [23:0] wr_data = 0;
wire dac_sclk, dac_mosi, dac_sync_n, busy;
dac8551 #(
.CLK_DIV(2)
) dut (
.i_clk(clk),
.i_rst(rst),
.i_wr(wr),
.i_wr_data(wr_data),
.o_dac_sclk(dac_sclk),
.o_dac_mosi(dac_mosi),
... | 6.807932 |
module test_data_join ();
reg clk;
reg rstn;
reg input_valid;
wire input_enable;
wire output_valid;
reg output_enable;
reg [3 : 0] data_in;
wire [7 : 0] data_out;
reg [7 : 0] joined_data;
data_join obj_data_join (
.clk(clk),
.rstn(rstn),
.input_valid(input_valid),
.input_ena... | 7.274198 |
module test_data_mem
(
clk_i,
rst_i,
Addr_i,
Read_en_i,
Read_data_o,
Write_en_i,
Wr_data_i
);
input clk_i, rst_i, Read_en_i, Write_en_i;
input [4:0] Addr_i;
input [`dw-1:0] Wr_data_i;
output [`dw-1:0] Read_data_o;
reg [`dw-1:0] Read_data_o;
reg [`dw-1:0] rf_reg [0:`dw-1];
integer i;
al... | 7.234184 |
module top ();
parameter STEP = 10;
reg [1:0] SEL;
reg [3:0] C0, C1, C2, C3;
wire [3:0] Y;
data_selector data_selector_instance (
.sel(SEL),
.c0 (C0),
.c1 (C1),
.c2 (C2),
.c3 (C3),
.y (Y)
);
initial begin
$dumpfile("test_data_selector.vcd");
$dumpvars(0, dat... | 6.832792 |
module test_data_size_sel;
parameter sim_time = 15;
wire [ 1:0] DataSize;
reg [31:0] IR;
reg [ 1:0] DSS;
reg [ 3:0] counter;
data_size_selector dss (
DataSize,
IR,
DSS
);
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
counter = 0;
repea... | 6.931936 |
module TEST_DCT_COSTABLE #(
parameter PERIOD = 1000
) ();
reg clk = 0;
initial begin
clk = #PERIOD 1;
forever clk = #(PERIOD / 2) ~clk;
end
reg rst = 0;
initial begin
@(posedge clk);
rst <= 1;
repeat (5) @(posedge clk);
rst <= 0;
end
reg [4-1:0] r;
reg [4-1:0] c;
wire ... | 6.504284 |
module test_ddos #(
parameter TIME_WIDTH = 25,
parameter CNT_WIDTH = 10,
parameter HASH_BITS = 16
) (
input wire clk,
input wire rst,
input [ 15:0] len_thresh,
input [TIME_WIDTH-1:0] time_thresh,
input alert,
input [31:0] dst_ip,
input [15:0] paylo... | 8.191907 |
module test_dds2k19;
// Inputs
reg dclk;
reg iq;
reg rst;
reg [31:0] frq;
// Outputs
wire [18:0] doxy;
reg [18:0] x0, x, y;
// Instantiate the Unit Under Test (UUT)
dds2k19 uut (
.doxy(doxy),
.dclk(dclk),
.iq (iq),
.rst (rst),
.frq (frq)
);
always @(posedge dclk... | 6.692283 |
module: debounce
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_debounce;
// Inputs
reg clk;
reg reset;
reg sig_in;
reg unlock;
reg [31:0] pos_in;
reg [31:0] timeout;
... | 6.908371 |
module test_dec;
wire [7:0] D;
reg [2:0] IN;
reg EN;
dec U0 (
.d (D),
.in(IN),
.en(EN)
);
initial begin
IN = 3'b000;
EN = 1'b0;
#5 IN = 3'b001;
EN = 1'b0;
#5 IN = 3'b010;
EN = 1'b0;
#5 IN = 3'b011;
EN = 1'b0;
#5 IN = 3'b100;
EN = 1'b0;
#5 IN =... | 7.203479 |
module Test_Decoder;
// Inputs
reg RST;
reg CLK;
reg [14:0] HADDR;
// Outputs
wire SEL_1;
wire SEL_2;
wire SEL_3;
wire [1:0] SELR;
// Instantiate the Unit Under Test (UUT)
Decoder uut (
.RST (RST),
.CLK (CLK),
.HADDR(HADDR),
.SEL_1(SEL_1),
.SEL_2(SEL_2),
.S... | 7.397423 |
module test_demux;
localparam SIZE_CTRL = 2;
parameter WIRE = 1;
wire [((2 ** SIZE_CTRL) * WIRE) - 1 : 0] out;
reg [WIRE - 1 : 0] in;
reg [SIZE_CTRL-1 : 0] ctrl;
demux #(
.SIZE_CTRL(SIZE_CTRL),
.WIRE(WIRE)
) demux0 (
ctrl,
in,
out
);
initial begin
$dumpfile("signal... | 7.324994 |
module test_demux8;
parameter SIZE_CTRL = 2;
parameter WIRE = 8;
wire [((2**SIZE_CTRL) * WIRE) - 1 : 0] out;
reg [ WIRE - 1 : 0] in;
reg [ SIZE_CTRL-1 : 0] ctrl;
integer cpt;
reg xin;
d... | 6.856134 |
module demux_TB ();
reg in;
reg [1:0] select;
wire out3, out2, out1, out0;
Demux_1_4 my_demux (
in,
select,
{out3, out2, out1, out0}
);
always #3 in = ~in;
initial begin
$dumpfile("out.vcd");
$dumpvars(1, demux_TB);
in = 0;
select = 2'b00;
#20 select = 2'b01;
#... | 7.176189 |
module demux_TB ();
reg in;
reg [1:0] select;
wire out3, out2, out1, out0;
Demux_1_4 my_demux (
in,
select,
{out3, out2, out1, out0}
);
always #3 in = ~in;
initial begin
$dumpfile("out.vcd");
$dumpvars(1, demux_TB);
in = 0;
select = 2'b00;
#20 select = 2'b01;
#... | 7.176189 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.