code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_deserializer;
reg reset = 0;
reg enable = 1;
wire complete;
reg in = 0; //serialized input
reg [7:0] framesize = 11; //serialized input
wire [135:0] out; //deserialized data
reg [135:0] input_values = 136'b10101010101010110101001001001010101001001010101011010101010101001010110100101011011... | 6.908859 |
module Test_DET_FSK_tf;
// Inputs
reg clk;
reg st;
reg [7:0] dat;
reg [7:0] Mamp;
// Outputs
wire [11:0] FSK_SH;
wire S;
wire ce_SIN;
wire en_tx;
wire TX_bit;
wire ce_tx_bit;
wire [11:0] DFSK_SH;
wire OCD;
wire [11:0] AMP;
wire [12:0] bf_SH;
wire FSK_tact;
wire [6:0] cb_tact;
wir... | 7.017777 |
module DFFI (
input I,
input CLK,
output O
);
wire GP_DFFI_inst0_nQ;
GP_DFFI GP_DFFI_inst0 (
.D (I),
.CLK(CLK),
.nQ (GP_DFFI_inst0_nQ)
);
assign O = GP_DFFI_inst0_nQ;
endmodule
| 6.611138 |
module test_dff_sync;
reg d, clk, rst;
wire q;
always @(posedge clk) begin
$monitor("d = %b, clk = %b, rst = %b, q = %b", d, clk, rst, q);
end
initial begin
forever begin
clk = 0;
#5 clk = 1;
#5 clk = 0;
end
end
initial begin
d = 0;
rst = 1;
#4 d = 1;
rst ... | 6.584259 |
module Test_DFTn (
output wire S, //
input clk,
output wire [11:0] SIN, //
input st,
output wire ce_tact, // DFT
input [7:0] M,
output wire ce_sd, //
output wire ce_SIN, //
output wire ce_bit, //
output wire [10:0] modY, //
output wire [6:0] k, // , k=|k*n|mod... | 7.05426 |
module test_direct;
reg CLK;
reg [255:0] memData;
reg [31:0] nextAddr;
wire [7:0] dataReturn;
wire hit;
wire [255:0] toMemData;
GT_direct_map map (
.CLK(CLK),
.memData(memData),
.nextAddr(nextAddr),
.dataReturn(dataReturn),
.hit(hit),
.toMemData(toMemData)
);
init... | 6.647316 |
modules for testbench
// notes :
//
// Copyright Illinois Institute of Technology
//
// Top level stimulus module
module stimulus;
reg [7:0] op1, op2;
reg clock, state0;
reg Clk;
wire [3:0] qj, qjn;
wire [10:0] Sum1, Carry1;
wire [10:0] Sum2, Carry2;
integer ... | 6.862012 |
modules for testbench
// notes :
//
// Copyright Illinois Institute of Technology
//
// Top level stimulus module
module stimulus;
reg [7:0] N;
reg [7:0] D;
reg state0, clock;
reg Clk;
wire [9:0] w;
wire [1:0] q;
integer handle3;
integer desc3;
... | 6.862012 |
module: div_steps
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_div_steps;
// Inputs
reg [31:0] dividend;
reg [31:0] divisor;
reg clk;
reg clk_en;
reg divide;
reg rese... | 7.153916 |
module testfixture;
//`define direction_matrix "../dat/compare.dat"
//`define H_matrix "../dat/H.dat"
`define sequence "../dat/BinaryInput.dat"
`define data_size "../dat/data_size.dat"
reg clk = 0;
reg rst_n;
reg [`BP_WIDTH-1:0] S;
reg [`BP_WIDTH-1:0] T;
reg s_update;
wire [`CALC_WIDTH-1:0] max_o;... | 6.999147 |
module test_dqs (
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
input set,
input ld_dly_data,
input ld_dly_tri,
input [7:0] dly_data,
input [3:0] data_in,
input [3:0] tri_in,
in... | 6.983332 |
module test_dqs01 (
input [1:0] dqs_data,
inout [1:0] dqs,
inout [1:0] ndqs,
output [1:0] dqs_received,
input [1:0] dqs_tri
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i0 (
.O (dqs_received[0])... | 6.804808 |
module test_dqs02 (
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
// input set,
// input ld_dly_data,
// input ld_dly_tri,
// input [7:0] dly_data,
input [3:0] data_in,
// input [3:0] tri_i... | 6.768085 |
module test_dram;
parameter CYCLE = 10; // use "CYCLE" to represent the period
parameter DRAM_DATA_WIDTH = 32;
parameter DRAM_ADDR_WIDTH = 13;
///// declare input(reg) and output(wire) /////
reg clk;
reg rst_n;
reg DRAM_enable;
wire DRAM_data_valid;
wire [DRAM_DATA_WIDTH-1:0] DRAM_data_out;
// d... | 8.3701 |
module: dut_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_dut_top;
// Inputs
reg clk;
reg nrst;
reg enable;
reg fifo_full;
// Outputs
wire fifo_wr_en;
wire [7:0]... | 6.660571 |
module test_dvsd_pe;
reg en;
reg [7:0] in;
wire eno, gs;
wire [2:0] out;
dvsd_pe uut (
.in (in),
.en (en),
.out(out),
.eno(eno),
.gs (gs)
);
initial begin
$dumpfile("dvsd_pe.vcd");
$dumpvars(0, test_dvsd_pe);
in = 8'b00000000;
en = 0;
#10;
in = 8... | 7.731165 |
module test_DW_ahb;
reg hclk;
supply1 logic_1;
supply0 logic_0;
wire dummy_wire;
wire [ 63:0] addr64;
wire [ 64:0] addr65;
wire [ 15:0] zero16 = 0;
wire [ ... | 6.666869 |
module test_D_flip_flop ();
reg D = 0, en = 0, clk = 0, clear = 0, set = 0;
wire Q, NQ;
D_flip_flop dff (
D,
en,
clk,
clear,
set,
Q,
NQ
);
always begin
#5 clk = 1;
#10 clk = 0;
#5{en, clear, set, D} = {en, clear, set, D} + 1;
end
endmodule
| 6.637852 |
module test_ecb_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
//ECB_dec e(ciphertext, message, key);
ECB_dec e (
ciphertext,
message,
key
);
initial begin
#10 $readmemb("ecb_enc.txt",... | 7.232516 |
module test_ecb_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
ECB_enc e (
ciphertext,
message,
key
);
//ECB_dec e(ciphertext, message, key);
initial begin
#10 $readmemb("binary.txt", ... | 7.258174 |
module: entry_park
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_entry_park;
// Inputs
reg entry;
reg [7:0] parking_capacity;
// Outputs
wire [2:0] park_number;
// In... | 6.500393 |
module test_environment ();
parameter DATA_WIDTH = 8;
parameter CLOCK_PERIOD = 5;
parameter TRANSACTION_NR = 30; // Number of transactions for the forth test scenario
parameter RST_DELAY = 30; // Initial waiting period before reset
parameter RST_DURATION = 2; // Duration of the reset pulse
parameter TES... | 7.608497 |
module test_err_pipe (
clock,
reset,
start,
done,
out,
T0,
T0_frac,
mem_Mux1Sel,
mem_Mux2Sel,
mem_Mux3Sel,
mem_Mux4Sel,
test_write_addr,
test_read_addr,
test_write,
test_write_en
);
input clock, reset, start;
output done;
output [15:0] out;
input [15... | 6.793341 |
module test_err_tb;
`include "paramList.v"
// Inputs
reg clock;
reg reset;
reg start;
reg [15:0] T0;
reg [15:0] T0_frac;
reg mem_Mux1Sel;
reg mem_Mux2Sel;
reg mem_Mux3Sel;
reg mem_Mux4Sel;
reg [11:0] test_write_addr;
reg [11:0] test_read_addr;
reg [31:0] test_write;
reg test_write_en;
... | 7.503106 |
module test_eth_axis_rx;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s... | 7.267792 |
module test_eth_axis_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
r... | 7.267792 |
module test_eth_axis_tx;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = ... | 7.267792 |
module test_eth_axis_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_ma... | 7.267792 |
module test_eth_mac (
//inout wire tx_clk,
input wire tx_clk,
inout wire tx_rst,
inout wire [63:0] tx_axis_tdata,
inout wire [ 7:0] tx_axis_tkeep,
inout wire tx_axis_tlast,
inout wire [16:0] tx_axis_tuser,
inout wire tx_axis_tvalid,
inout wire ... | 7.16086 |
module test_eth_mac_1g_gmii;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg gtx_clk = 0;
reg gt... | 7.35377 |
module test_eth_mac_1g_rgmii;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter USE_CLK90 = "TRUE";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test ... | 7.35377 |
module test_eth_mac_mii;
// Parameters
parameter TARGET = "SIM";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_a... | 7.35377 |
module test_eth_phy_10g_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
paramet... | 7.284581 |
module test_eth_phy_10g_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parame... | 7.284581 |
module test_eth_phy_10g_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
... | 7.284581 |
module
module ram #(
parameter ADDR_WIDTH=6,
parameter DATA_WIDTH=8
) (
input [DATA_WIDTH-1:0] data,
input [ADDR_WIDTH-1:0] addr,
input we, clk,
output reg [DATA_WIDTH-1:0] q
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we)
ram... | 7.233831 |
module test_ex1;
`include "lib/helpers.vh"
// Inputs
reg reset;
reg clk;
// Outputs
wire out;
// Checker
reg [4:0] total;
// Instantiate the Unit Under Test (UUT)
ex1 uut (
.out (out),
.reset(reset),
.clk (clk)
);
reg count = 0;
initial begin
// Initialize Inputs
... | 6.861294 |
module test_ex2;
`include "lib/helpers.vh"
// Inputs
reg reset;
reg clk;
// Outputs
wire [7:0] out;
wire [3:0] state;
// Checker
reg [4:0] total;
reg [4:0] exp_state;
// Instantiate the Unit Under Test (UUT)
ex2 uut (
.out(out),
.currentState(state),
.reset(reset),
.c... | 6.898797 |
module test_ex3;
`include "lib/helpers.vh"
// Inputs
reg button;
reg reset;
reg clk;
// Outputs
wire [7:0] out;
// Checker
reg [4:0] total;
// Instantiate the Unit Under Test (UUT)
ex3 uut (
.out(out),
.button_debounced(button),
.reset(reset),
.clk(clk)
);
initial ... | 7.355491 |
module test_ex4;
`include "lib/helpers.vh"
// Inputs
reg A;
reg G;
reg C;
reg T;
reg reset;
reg clk;
// Outputs
wire mutant;
wire super_mutant;
wire [2:0] current_state;
// Checker
reg [4:0] total;
// Instantiate the Unit Under Test (UUT)
ex4 uut (
.mutant(mutant),
.super... | 6.874489 |
module test_example ();
// Inputs.
reg in;
// Outputs.
/* verilator lint_off UNUSED */
wire out;
/* verilator lint_on UNUSED */
// Initialize Unit Under Test (UUT).
example some_name (
.out(out),
.in (in)
);
initial begin
$dumpfile("waves.vcd");
$dumpvars(0, test_example);
... | 6.528766 |
module: exit_park
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_exit_park;
// Inputs
reg exit;
reg [2:0] token;
reg [2:0] pattern;
// Outputs
wire [7:0] park_location;... | 7.197993 |
module: expr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_expr;
// Inputs
reg clk;
reg clr;
reg [7:0] in;
// Outputs
wire out;
// Instantiate the Unit Under Test (U... | 7.006903 |
module: ext
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ext;
// Inputs
reg [15:0] imm;
reg [1:0] EOp;
// Outputs
wire [31:0] ext;
// Instantiate the Unit Under Test... | 7.228997 |
module test_fastcounter;
localparam NBITS = 9;
localparam NBITS_STAGE = 4;
reg clk = 0;
reg rst = 0;
reg [1:0] mode = 0;
reg dir = 0;
reg en = 0;
reg load = 0;
reg [NBITS-1:0] load_q = 0;
wire pend, nend, carry, carry_dly, epulse;
wire [NBITS-1:0] q;
reg en_gated = 0;
always @(posedge clk) ... | 6.533355 |
module: fetch
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_fetch;
// Inputs
reg pcsrc;
reg mux1;
reg clk;
// Outputs
wire adderOutput;
wire instruction;
// Instant... | 6.65392 |
module test_fetcher ();
// Inputs
reg clk;
reg rst;
reg [4:0] address;
// Outputs
/* verilator lint_off UNUSED */
wire [7:0] data;
/* verilator lint_off UNUSED */
// Instantiate the Unit Under Test (UUT)
fetcher uut (
.clk(clk),
.rst(rst),
.address(address[3:0]),
... | 6.856861 |
module test_FIFO_new ();
reg clk;
reg rstn;
reg input_valid;
wire input_enable;
wire output_valid;
reg output_enable;
reg [7:0] data_in;
wire [7:0] data_out;
FIFO_new obj_FIFO (
.clk(clk),
.rstn(rstn),
.input_valid(input_valid),
.input_enable(input_enable),
.output_enabl... | 7.146648 |
module test_FIFO_random ();
reg clk;
reg rstn;
reg input_valid;
wire input_enable;
wire output_valid;
reg output_enable;
reg [3:0] data_in;
wire [7:0] data_out;
FIFO obj_FIFO (
.clk(clk),
.rstn(rstn),
.input_valid(input_valid),
.input_enable(input_enable),
.output_enable... | 7.409369 |
module Test_FIR ();
reg [15:0] tmp_test = 0;
wire [15:0] data_out;
reg clk = 0, reset = 0;
reg signed [15:0] data_in;
FIR uut (
.clk(clk),
.data_in(data_in),
.reset(reset),
.data_out(data_out)
);
always #5 clk = ~clk;
integer in, out;
initial begin
#10 reset = 1;
... | 6.862985 |
module test_fir128x16x18;
// Inputs
reg [2:0] ioaddr;
reg iocs;
reg [15:0] din;
reg iowr;
reg iord;
reg clk;
reg rst;
// Outputs
wire [15:0] dout;
// Instantiate the Unit Under Test (UUT)
dfir128x16x18 uut (
.ioaddr(ioaddr),
.iocs(iocs),
.din(din),
.iowr(iowr),
.... | 6.862398 |
module Test_FIR;
reg [15:0] din;
reg clk, reset;
wire [15:0] dout_normal, dout_pipeline;
FIR_NORMAL n_myfir (
.reset(reset),
.clk(clk),
.data_in(din),
.data_out(dout_normal)
);
FIR_PIPELINE myfir (
.reset(reset),
.clk(clk),
.data_in(din),
.data_out(dout_pipel... | 6.803173 |
module Test_FIR ();
reg [15:0] tmp_test = 0;
wire [15:0] data_out;
reg clk = 0, reset = 0;
reg signed [15:0] data_in;
reg [5:0] counter = 0;
fir uut (
.clk(clk),
.data_in(data_in),
.reset(reset),
.data_out(data_out)
);
always #5 clk = ~clk;
integer in, out;
initial begin
... | 6.862985 |
module test_flash_sword (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// flash interfaces
output wire [1:0] flash_ce_n,
output wire flash_rst_n,
output wire flas... | 7.30317 |
module: flip_flop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_flip_flop;
// Inputs
reg clk,rst, ena;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (U... | 6.626827 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_alu;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
reg [3:0] aluCtr;
// Outputs
wire zero;
wire [31:0]... | 7.023594 |
module: aluCtr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_aluCtr;
// Inputs
reg [1:0] aluOp;
reg [5:0] funct;
// Outputs
wire [3:0] aluCtr;
// Instantiate the ... | 6.718252 |
module: Ctr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_Ctr;
// Inputs
reg [5:0] opCode;
// Outputs
wire regDst;
wire aluSrc;
wire memToReg;
wire regWrite;
wir... | 7.12312 |
module: date_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_date_memory;
// Inputs
reg clock_in;
reg [31:0] address;
reg [31:0] writeData;
reg memWrite;
reg m... | 7.241115 |
module: signext
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_signext;
// Inputs
reg [15:0] inst;
// Outputs
wire [31:0] data;
// Instantiate the Unit Under Test (... | 7.114626 |
module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_top;
// Inputs
reg CLOCK_IN;
reg RESET;
reg [3:0] SWITCH;
// Outputs
wire [3:0] LED;
// Instantiate the... | 7.357405 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_whole;
// Inputs
reg clk;
reg [7:0] sw;
reg [7:0] sww;
reg [3:0] push;
// Outputs
wire [7:0] led;
wire ... | 7.115105 |
module test_fp_ip (
input wire [31:0] a, // a.a
input wire acc, // acc.acc
input wire areset, // areset.reset
input wire [31:0] b, // b.b
input wire clk, // clk.clk
input wire [ 0:0] en, // en.en
output wire [31:0] q ... | 6.672203 |
module test_fp_ip (
input wire clk,
input wire rst,
input wire [2:0] ctrl,
input wire output_ctrl,
inout wire [31:0] data,
input wire do_act,
output [4:0] counter,
output [11:0] ArrWgt_Rd,
output [11:0] ArrWgt_Wr,
output [31:0] ArrWeights_1,
output fp_mac_acc,
output [31:... | 6.672203 |
module
// Methodology: For this to work, change the localparam max in freq_counter to match the clock cycle
// here. The testbench creates a clock signal and a test signal to use in the
// freq_counter module. To see the results, run the simulation for a little while
// longer unt... | 8.654609 |
module test_fsm;
// Inputs
reg clk;
reg reset;
reg [25:0] rom_q;
// Outputs
wire [8:0] rom_addr;
wire [5:0] ram_a_addr;
wire [5:0] ram_b_addr;
wire ram_b_w;
wire [10:0] pe;
wire done;
// Instantiate the Unit Under Test (UUT)
FSM uut (
.clk(clk),
.reset(reset),
.rom_addr(ro... | 6.638073 |
module test_fsyn;
// Inputs
reg [15:0] mag;
reg [15:0] frq;
reg fmv;
reg clk;
// Outputs
wire [15:0] avgfrq;
wire fcd;
// Instantiate the Unit Under Test (UUT)
fsyn uut (
.mag(mag),
.frq(frq),
.fmv(fmv),
.avgfrq(avgfrq),
.fcd(fcd),
.clk(clk),
.nfl(0),
... | 7.263405 |
module ALUControl (
ALUOp,
Funct,
ALUOpcode_MC
);
output reg [2:0] ALUOp;
input [2:0] ALUOpcode_MC;
input [3:0] Funct;
always @(*) begin
if (ALUOpcode_MC == 3'b100) begin
case (Funct)
4'b0001: ALUOp <= 3'b100;
4'b0010: ALUOp <= 3'b101;
4'b0011: ALUOp <= 3'b110;
... | 8.639118 |
module ALU_unit (
A,
B,
ALUOp,
out,
zero
);
input [15:0] A, B;
input [2:0] ALUOp;
output reg [15:0] out;
output zero;
integer i, count;
always @(*) begin
count = B;
if (ALUOp == 3'b000) begin
out = A + B;
end
if (ALUOp == 3'b001) begin
out = A - B;
end
... | 6.585557 |
module Register_File (
ReadReg1,
ReadReg2,
ReadReg3,
ReadReg4,
ReadReg5,
WriteReg,
WriteData,
ReadData1,
ReadData2,
ReadData3,
ReadData4,
ReadData5,
RegWrite
);
input [3:0] ReadReg1, ReadReg2, ReadReg3, ReadReg4, ReadReg5, WriteReg;
input [15:0] WriteData;
input... | 6.725474 |
module Instruction_Register (
clk,
D,
WriteEnable,
m,
n,
x,
y,
z,
b1,
b2,
b3,
b4,
b5,
opcode,
funct
);
input [15:0] D;
input WriteEnable, clk;
reg [15:0] Instr;
output [3:0] m, n, x, y, z;
output [15:0] b1, b2, b3, b4, b5;
output [3:0] funct;
out... | 6.510365 |
module Program_Counter (
CLK,
PCSource,
PCSrc0,
PCSrc1,
PCSrc2,
PCWriteInput,
PC,
PCWrite
);
input [1:0] PCSource;
input PCWrite;
input [15:0] PCSrc0, PCSrc1, PCSrc2;
input PCWriteInput, CLK;
output reg [15:0] PC = 0;
always @(posedge CLK) begin
if (PCWriteInput == 1'b1)... | 6.785422 |
module test_gate;
reg e1, e2;
wire out_not, out_nor, out_nand, out_and, out_or, out_xor, out_buf, out_xnor;
gate_not not_inst (
out_not,
e1
);
gate_nor nor_inst (
out_nor,
{e2, e1}
);
gate_nand nand_inst (
out_nand,
{e2, e1}
);
gate_and and_inst (
out_and,
... | 7.566241 |
module TOP;
//ALU inputs
reg [31:0] a, b;
wire [31:0] p;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(p != (a & b))
begin
... | 7.259416 |
module test_gmii #(
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire rst,
inout wire [DATA_WIDTH-1:0] gmii_d,
inout wire gmii_er,
inout wire gmii_en,
inout wire gmii_clk_en,
inout wire gmii_mii_sel
);
endmodule
... | 6.949965 |
module and2 (
A,
A_b_i,
A_b_o,
A_b_o2
);
//ports
input [7:0] A_b_i;
output [7:0] A_b_o;
output [7:0] A_b_o2;
input A;
//wires
wire [7:0] A_b_i;
wire [7:0] A_b_o;
wire [7:0] A_b_o2;
wire A;
endmodule
| 6.704587 |
module: Goomba
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_goomba;
// Inputs
reg clk;
reg rstn;
reg initial_show;
reg collapsion_impulse;
reg press_impulse;
// Outp... | 6.961079 |
module TOP;
//ALU inputs
reg g_in_high, p_in_high, g_in_low, p_in_low;
wire g_out, p_out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
g_in_high = 0;
p_in_high = 0;
g_in_low = 0;
p_in_low = 0;
... | 7.259416 |
module test_hexToBcd ();
reg [7:0] hex = 0;
wire [7:0] bcd;
hexToBcd h2b (
bcd,
hex
);
initial begin
#5 hex = 8'd10;
#5 hex = 8'd30;
#5 $finish;
end
endmodule
| 6.700443 |
module test_hvsync_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/*******************************************************
* ... | 7.126708 |
module test_i2c_master;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [6:0] s_axis_cmd_address = 0;
reg s_axis_cmd_start = 0;
reg s_axis_cmd_read = 0;
reg s_axis_cmd_write = 0;
reg s_axis_cmd_write_multiple = 0;
reg s_axis_cmd_stop = 0;
reg s_axis_cmd_valid... | 7.991605 |
module test_i2c_master_axil;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
... | 7.991605 |
module test_i2c_master_wbs_16;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Input... | 7.991605 |
module test_i2c_master_wbs_8;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs... | 7.991605 |
module test_i2c_slave;
// Parameters
parameter FILTER_LEN = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg release_bus = 0;
reg [7:0] s_axis_data_tdata = 0;
reg s_axis_data_tvalid = 0;
reg s_axis_data_tlast = 0;
reg m_axis_data_tready = 0;
reg scl_i = 1;
reg sda_i = ... | 7.851238 |
module test_i2c_slave_axil_master;
// Parameters
parameter FILTER_LEN = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter STRB_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg m_axil_awready = ... | 7.851238 |
module test_i2c_slave_wbm;
// Parameters
parameter FILTER_LEN = 4;
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 16;
parameter WB_SELECT_WIDTH = WB_DATA_WIDTH / 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg [WB_DATA_WIDT... | 7.851238 |
module test_i2s_top_rx;
localparam RST_DURATION = 50; //ns
localparam CLK_PERIOD = 20; //ns
localparam STIMULUS_DATA_COUNT = 10;
// Inputs
reg clk_i;
reg rst_i;
reg sdat_i;
// Outputs
wire [15:0] data_o;
wire lr_chnl_o;
wire write_o;
wire sclk_o;
wire wsel_o;
// Received data
reg [1... | 6.66221 |
module test_i2s_top_trx;
localparam RST_DURATION = 50; //ns
localparam CLKT_PERIOD = 10; //ns
localparam CLKR_PERIOD = 100; //ns
localparam STIMULUS_DATA_COUNT = 10;
// Inputs
reg clk_i_t;
reg clk_i_r;
reg rst_i;
reg [15:0] data_i_t;
// Inouts
wire sclk;
wire wsel;
wire sdat;
// Outp... | 6.66221 |
module test_i2s_top_tx;
localparam RST_DURATION = 50; //ns
localparam CLK_PERIOD = 10; //ns
localparam SCLK_PERIOD = 100; //ns
localparam STIMULUS_DATA_COUNT = 10;
// Inputs
reg clk_i;
reg rst_i;
reg [15:0] data_i;
reg sclk_i;
reg wsel_i;
// Outputs
wire lr_chnl_o;
wire write_o;
wire ... | 6.66221 |
module test2;
reg [31:0] PC;
wire [31:0] inst;
IMEM dut (
.PC (PC),
.inst(inst)
);
initial begin
PC = 32'h000_0001_0;
$monitor("inst=%0h", inst);
#20;
PC = 32'h000_0002_0;
#50;
end
endmodule
| 6.545213 |
module test_img_control #(
parameter WIDTH = 640,
parameter HEIGHT = 480,
parameter PICWIDTH = 512,
parameter PICHEIGHT = 384
) (
input clk,
input [10:0] h_cnt,
input [9:0] v_cnt,
input vsync,
input inplace,
input display_ena,
input movement_ena,
output [3:0] r,
outpu... | 7.079247 |
module test_img_feeder (
input wire rst,
input wire clk,
input wire clk_feeder,
output wire [31:0] fifoData_out,
input wire fifoRdclk,
input wire fifoRdreq,
output wire fifoRdempty,
input wire pause
);
reg [11:0] hcnt, vcnt;
wire [31:0] pixel_data;
wire sync_pixel_h;
wire sync... | 6.700963 |
module test_immediate_sign_ext;
reg [31:0] Instruction; //Las entradas del módulo deben ser tipo reg
wire [31:0] DataOut;
reg Enable;
reg [1:0] Select;
reg [2:0] counter;
parameter sim_time = 15;
immediate_sign_extension ext (
DataOut,
Instruction,
Enable,
Select
);
initial ... | 7.932534 |
module test_in (
input clk,
input rst,
input enable,
output reg finished,
input [23:0] write_count,
input [ 1:0] ready,
output reg [ 1:0] activate,
output reg [31:0] fifo_data,
input [23:0] fifo_size,
output reg strobe
);
//Parameter... | 7.063097 |
module test_part_select_inst_0 (
G1,
G2
);
input [3:0] G1;
output G2;
and AND2 (G2, G1[1:0], G1);
endmodule
| 7.104898 |
module test_part_select_inst_1 (
G1,
G2
);
input G1;
output [3:0] G2;
and AND2 (G2[1:0], G1, G1);
endmodule
| 7.104898 |
module test_part_select_assign_0 (
G1,
G2
);
input [3:0] G1;
output G2;
assign G2 = G1[1:0] & G1;
endmodule
| 7.104898 |
module test_part_select_assign_1 (
G1,
G2
);
input G1;
output [3:0] G2;
assign G2[1:0] = G1 & G1;
endmodule
| 7.104898 |
module test_concat_0 (
G1,
G2
);
input G1;
output [1:0] G2;
assign G2 = {G1, G1};
endmodule
| 6.571725 |
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