code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_logical_operator (
clk,
G1,
G2
);
input G1, G2;
output G3;
assign G3 = G1 && G2;
endmodule
| 6.608267 |
module TOP;
//ALU inputs
reg [31:0] a;
wire [31:0] out;
//wire [31:0] flags;
wire carry_out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffff_ffff;
#`cycle //1
if(out != (a + 1))
begin
... | 7.259416 |
module mux_test_inlab(
// input [9:0] SW,
// input CLOCK_50,
// input [3:0] KEY,
// output [9:0] LEDR,
// output VGA_CLK, // VGA Clock
// output VGA_HS, // VGA H_SYNC
// output VGA_VS, // VGA V_SYNC
// output VGA_BLANK_N, // VGA BLANK
// output VGA_SYNC_N, // VGA SYNC
// out... | 7.765303 |
module mux_ui_ff ( // clear_instruction need to be set with high change_instruction;
// reset to change instruction, no reset for clear
input change_instruction,
input reset_n,
input clk,
input clear_instruction,
output [2:0] color,
output [7:0] x,
output [6:0] y,
output done_signa... | 7.567331 |
module mux_instructions (
input enable,
input [3:0] instruction, // input instruction with 4 bit, [3] clear when 1
// [2:0] instruction
input clk,
input reset_n,
output reg done,
output reg writeEn,
output reg [7:0] x,
output reg [6:0] y
);
reg en_u1, en_u2, en_u3, en_u4, en_u5, ... | 7.710431 |
module mux_control (
input clear,
input enable, // corresponding to change_instruction flag, flip
input [2:0] instruction,
input reset_n,
input done,
input clk,
output reg reset_instructions,
output reg [3:0] control_instructions,
output reg [2:0] color
);
reg [5:0] CURRENT_STATE... | 9.509437 |
module instruction_shift_control (
input clk,
input reset_n,
output reg reset_random
);
// random need to be initialized with reset, but only once, we need control
reg [1:0] CURRENT_STATE, NEXT_STATE;
localparam START = 2'b01, RESET = 2'b10, DONE = 2'b11;
always @(*) begin
case (CURRENT_ST... | 8.258005 |
module instruction_shift (
input change_instruction,
input clk,
input reset_n, // reset only the control, only once by FSM
output reg [2:0] instruction
);
wire [3:0] random;
wire rst_n;
reg [3:0] ran;
wire enable_control;
// reset this machine automatically in first 2 clk
instruction_shift... | 8.258005 |
module
module dff_0(clock,reset_n,data_in,q);
input clock,reset_n,data_in;
output reg q;
always@(posedge clock)
begin
if(reset_n == 0)
q <= 1'b0;
else
q<= data_in;
end
endmodule
| 6.870045 |
module dff_1 (
clock,
reset_n,
data_in,
q
);
input clock, reset_n, data_in;
output reg q;
always @(posedge clock) begin
if (reset_n == 0) q <= 1'b1;
else q <= data_in;
end
endmodule
| 6.721609 |
module ui_UP (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
w... | 7.14537 |
module control_UI (
input clk,
input reset_n,
input enable_unit,
output reg enable,
output reg writeEn,
output reg reset_datapath
);
localparam ENABLE_STATE = 4'b0000, ENABLE_WAIT = 4'b0001, DRAW = 4'b0010, DISABLE = 4'b0011;
reg [1:0] current_state, next_state;
always @(*) begin
cas... | 6.660162 |
module datapath_up (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, f... | 6.800186 |
module test_rate_divider (
input clk,
input reset_n,
input enable,
output [3:0] frame_out
);
wire [24:0] rate_out;
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
frame_counter frame (
clk,
frame_ena... | 6.95378 |
module ui_DOWN (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
... | 7.03474 |
module datapath_down (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done,... | 6.790293 |
module ui_RIGHT (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
... | 6.687216 |
module datapath_right (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done... | 6.744548 |
module ui_LEFT (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
... | 6.847954 |
module datapath_left (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done,... | 6.965497 |
module ui_L (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
wr... | 7.193055 |
module datapath_L (input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, frame ... | 6.685861 |
module ui_R (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
wr... | 7.546963 |
module datapath_R (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3, increment4, increment5, incremen... | 6.777345 |
module counter_5 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b100) increment <= ... | 6.894743 |
module counter_6 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b101) increment <= ... | 6.768667 |
module counter_4 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b011) increment <= ... | 6.562775 |
module counter_8 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b111) increment <= ... | 7.065173 |
module frame_counter (
clk,
enable,
reset_n,
out
);
input clk, enable, reset_n;
output reg [4:0] out;
always @(posedge clk) begin
if (!reset_n) begin
out <= 5'b0;
end else if (enable) begin
if (out == 5'd15) out <= 5'b0;
else out <= out + 1'b1;
end
end
endmodule
| 6.859338 |
module rate_divider (
clk,
reset_n,
enable,
out
);
input clk;
input reset_n;
input enable;
output reg [24:0] out;
always @(posedge clk) begin
if (!reset_n) begin
out <= 25'd0;
end else if (enable) begin
if (out == 25'd3125000) begin
out <= 25'd0;
end else beg... | 7.346866 |
module test_inputs (
input loop_rst,
input LVBL,
output reg [6:0] game_joystick1,
output reg button_1p,
output reg coin_left
);
localparam FIRE = 4;
localparam DOWN = 2;
integer framecnt = 0;
always @(negedge loop_rst) $display("INFO: loop_rst over.");
... | 7.415876 |
module test_input_2;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 1;
parameter SIGNED = 1;
parameter ASCENDING = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
r... | 7.387447 |
module test_input_4;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 2;
parameter SIGNED = 1;
parameter ASCENDING = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DAT... | 7.241409 |
module test_input_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 3;
parameter SIGNED = 1;
parameter ASCENDING = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DAT... | 7.425543 |
module test;
// Clock period, ns
parameter CLOCK_PERIOD = 500;
// Pulse width, gap and break delay
parameter PWID = 500;
parameter PGAP = 500;
parameter BREAK = 25000; // 25us
// time constants
localparam USEC = 1000;
localparam MSEC = 1000000;
// Output waveform file for this test
initial be... | 7.816888 |
module.v"
`include "../src/rate_divider.v"
module test_input_module(
CLOCK_50,
KEY,
LEDR,
LEDG);
input CLOCK_50;
input [1:0] KEY;
output [2:0] LEDR;
output [3:0] LEDG;
wire [27:0] one_hz = 28'b0010111110101111000010000000;
wire clock;
rate_divider rate0(
.clock_in... | 7.259509 |
module test;
// Clock period, ns
parameter CLOCK_PERIOD = 500;
// Pulse width, gap and break delay
parameter PWID = 500;
parameter PGAP = 500;
parameter BREAK = 25000; // 25us
// time constants
localparam USEC = 1000;
localparam MSEC = 1000000;
// Output waveform file for this test
initial be... | 7.816888 |
module test_instruction;
// Inputs
reg [31:0] pc;
// Outputs
wire [31:0] instruction;
// Instantiate the Unit Under Test (UUT)
InstructionMemory_32 uut (
.pc(pc),
.instruction(instruction)
);
initial begin
// Initialize Inputs
pc = 0;
// Wait 100 ns for global reset to fini... | 7.204418 |
module test_instruction_decoder ();
reg clk, rst;
reg [31:0] instruction;
reg [31:0] men_data;
reg [31:0] alu_result;
wire jal = instruction[31:26] == 6'b000011;
wire reg_write = (
instruction[31:29] == 3'b001 ||
instruction[31:26] == 6'b100011 ||
jal |... | 7.204418 |
module test_instruction_fetch ();
// input
reg [31:0] Add_result = 32'h00000000;
reg [31:0] Read_data_1 = 32'h00000000;
reg Branch = 1'b0;
reg nBranch = 1'b0;
reg Jmp = 1'b0;
reg Jal = 1'b0;
reg Jrn = 1'b0;
reg Zero = 1'b0;
reg clock = 1'b0, reset = 1'b1;
... | 7.204418 |
module: interleave_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_interleave_top_v;
// Inputs
reg clk;
reg clk_bit;
reg rst_n;
reg [7:0] din;
reg syn_in;
// Output... | 6.629 |
module f2_test (
in1,
in2,
out
);
input in1, in2;
output reg out;
always @(in1 or in2)
if (in1 > in2) out = in1;
else out = in2;
endmodule
| 6.539927 |
module f10_MyCounter (
clock,
preset,
updown,
presetdata,
counter
);
input clock, preset, updown;
input [1:0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if (preset) counter <= presetdata;
else if (updown) counter <= counter + 1;
else counter <= counter - 1;
en... | 6.992385 |
module f12_test (
input in,
output out
);
//no buffer removal
assign out = in;
endmodule
| 7.136143 |
module f14_test (
in,
out
);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign w4 = w3;
assign out = w4;
f14_mybuf _f14_mybuf (
w2,
w3
);
endmodule
| 6.860461 |
module f14_mybuf (
in,
out
);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
| 7.333671 |
module f15_mybuf (
in,
out
);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
| 7.102453 |
module f16_test (
out,
in1,
in2,
vin1,
vin2,
vout1
);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 + in2;
assign vout1 = vin1 + vin2;
endmodule
| 6.8974 |
module f17_test (
in1,
in2,
vin1,
vin2,
out,
vout,
vin3,
vin4,
vout1
);
input in1, in2;
input [1:0] vin1;
input [3:0] vin2;
input [1:0] vin3;
input [3:0] vin4;
output vout, vout1;
output out;
assign out = in1 && in2;
assign vout = vin1 && vin2;
assign vout1 = ... | 6.503725 |
module f18_test (
output out,
input in,
output [1:0] vout,
input [1:0] vin
);
assign out = ~in;
assign vout = ~vin;
endmodule
| 7.063564 |
module f20_test (
in1,
in2,
out,
vin1,
vin2,
vin3,
vin4,
vout1,
vout2,
en1,
ven1,
ven2
);
input in1, in2, en1, ven1;
input [1:0] ven2;
output out;
input [1:0] vin1, vin2, vin3, vin4;
output [1:0] vout1, vout2;
assign out = en1 ? in1 : in2;
assign vout1 = ... | 6.798931 |
module f21_test (
in,
out,
en,
vin1,
vout1,
en1
);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule
| 6.873326 |
module f22_test (
in,
out,
vin,
vout,
vin1,
vout1,
vin2,
vout2
);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule
| 7.049654 |
module f24_test (
out,
in1,
in2,
vin1,
vin2,
vout1
);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 / in2;
assign vout1 = vin1 / vin2;
endmodule
| 6.651305 |
module f25_test (
out,
vout,
in,
vin
);
output out, vout;
input in;
input [3:0] vin;
assign out = !in;
assign vout = !vin;
endmodule
| 6.687032 |
module f28_test (
output out,
input [1:0] vin,
output out1,
input [3:0] vin1
);
assign out = &vin;
assign out1 = &vin1;
endmodule
| 6.751069 |
module f29_Reduction (
A1,
A2,
A3,
A4,
A5,
A6,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6
);
input [1:0] A1;
input [1:0] A2;
input [1:0] A3;
input [1:0] A4;
input [1:0] A5;
input [1:0] A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
//reg Y1, Y2, Y3, Y4, Y5, Y6;
assign Y1 = &A1; //red... | 6.565295 |
module f30_test (
out,
in1,
in2,
vin1,
vin2,
vout1
);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 - in2;
assign vout1 = vin1 - vin2;
endmodule
| 6.813864 |
module f31_test (
output out,
input in,
output [31:0] vout,
input [31:0] vin
);
assign out = -in;
assign vout = -vin;
endmodule
| 7.053981 |
module f32_test (
output out,
input in
);
assign out = +in;
endmodule
| 7.000614 |
module f33_test (
vin0,
vout0
);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule
| 6.579599 |
module testbench
SXP Processor
Sam Gladstone
*/
`timescale 1ns / 1ns
`include "../src/int_cont.v"
module test_int_cont();
reg clk;
reg reset_b;
reg halt;
reg int_req;
reg [15:0] int_num;
reg safe_switch;
reg nop_detect;
wire int_rdy;
wire idle;
wire int_srv_req;
wire jal_req;
wire [15:0] int_srv_num;
intege... | 7.336453 |
module INV (
input I,
output O
);
wire GP_INV_inst0_OUT;
GP_INV GP_INV_inst0 (
.IN (I),
.OUT(GP_INV_inst0_OUT)
);
assign O = GP_INV_inst0_OUT;
endmodule
| 7.585108 |
module test_inv2;
wire out;
reg in, inv;
inverter Inverter (
out,
in,
inv
);
initial begin
in <= 0;
inv <= 0;
#10 inv <= 1;
end
initial $monitor("%b %b %b", inv, in, out);
endmodule
| 6.73782 |
module
// Project Name: GVISION200
// Target Devices: Spartan-6 xc6slx150-3fg900
// Tool versions: ISE13.1
// Description:
// Revision:
// V1.0-First created
//////////////////////////////////////////////////////////////////////////////////
module test_io_module( test_in_0, test_in_1, test_in_2, test_in_3, t... | 7.088073 |
module test_is_sign ();
reg [31:0] result = 32'bz;
reg [31:0] a = 1, b = -1;
reg clk = 0;
reg [31:0] rrr = 0;
wire [31:0] www;
assign www = rrr;
initial begin
#0.1
rrr = 1;
#0.1
rrr = 2;
end
always
fork
//是无符号数比?
#1 result = a < b;
#11 result = a > b;
//可行
... | 6.723615 |
module test_jbimu;
// Inputs
reg clks;
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
83
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire... | 6.632599 |
module test_JK;
// Inputs
reg J;
reg K;
reg clk;
reg clear;
// Outputs
wire Q;
wire Qbar;
// Instantiate the Unit Under Test (UUT)
myJK uut (
.J(J),
.K(K),
.clk(clk),
.Q(Q),
.Qbar(Qbar)
);
initial begin
// Initialize Inputs
clear = 1;
J = 0;
... | 6.645279 |
module _test_JKlatchUP_rst;
reg j, k, clk, reset;
wire s1, s2;
supply1 power;
integer i;
JKlatchUP_rst test_JKlatchUP_rst (
j,
k,
clk,
reset,
s1,
s2
);
initial begin
reset = 1;
j = 1;
k = 1;
clk = 0;
i = 0;
$dumpfile("signal_JKlatchUP.vcd");
... | 6.52092 |
module test_jmp (
input wire dummy
);
reg clk, reset;
localparam IL = 17;
localparam PRG = "/mnt/data/nand2tetris/Verilog/nand2tetris/src/test/test_jmp.mif";
wire signed [15:0] regD;
wire [15:0] regA;
wire writeM;
wire [15:0] data_in, data_out;
wire [ 14:0] addressM;
wire [IL-1:0] instruction;... | 6.722315 |
module TEST_KANADE32 ();
parameter CLK = 10;
reg reset_n;
reg clk;
always begin
#(CLK) clk <= ~clk;
end
initial begin
$dumpvars(0, TEST_KANADE32);
#0;
reset_n <= 1;
clk <= 0;
#1 reset_n <= 0;
#(CLK * 4) reset_n <= 1;
#1000000 $finish;
end
KANADE32 kanade (
.... | 6.983331 |
module Test_Keyboard;
reg clk;
reg rst;
reg clr;
reg ps2_clk;
reg ps2_data;
wire [7:0] data;
wire cs;
wire ready;
assign cs = 1;
Keyboard keyboard (
.clk(clk),
.rst(rst),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.data(data),
.cs(cs),
.clr(clr),
.rea... | 6.595034 |
module TOP;
//ALU inputs
reg [31:0] a, b;
wire [31:0] p;
wire [31:0] g;
wire [31:0] c;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(c != 32'b00... | 7.259416 |
module test_KSA;
reg [15:0] x, y; // input x, y
reg c0; // carry in
wire [15:0] sum; // output sum
wire c16; // carry out
reg [16:0] check; // KoggeStoneAdder로 구한 값이 맞는지 확인
integer i, j, k;
integer num_correct; // 값이 맞을 경우 증가
integer num_wrong; // 값이 틀릴 경우 증가
KoggeStoneAdder ksa (
c16,
... | 6.733552 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mem #(
parameter has_init = 1'b0,
parameter sync_read = 1'b0,
parameter depth = 1,
parameter width = 1,
parameter [(width * depth) - 1:0] init = 0
) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output [width-1:0] rdata,
input... | 7.482949 |
module RAM256x16 (
input [7:0] RADDR,
output [15:0] RDATA,
input [7:0] WADDR,
input [15:0] WDATA,
input CLK,
input WE
);
wire [15:0] coreir_mem256x16_inst0_rdata;
wire [15:0] reg_P_inst0_out;
coreir_mem #(
.depth(256),
.has_init(1'b0),
.sync_read(1'b0),
.width(16)
... | 6.532367 |
module test_lcd (
input wire CLK_IN,
input wire RST_N,
output wire [0:7] R,
output wire [0:7] G,
output wire [0:7] B,
output wire LCD_CLK,
output wire LCD_HSYNC,
output wire LCD_VSYNC,
output wire LCD_DEN,
output wire LCD_PWM //backlight,set to high
);
wire clk_lcd;
wire clk... | 7.337433 |
module test_lecture4;
// inputs (use regs)
reg [2:0] swt;
// Outputs use wires
wire D;
integer i;
reg e_output;
// Instantiate the Device/Module Under Test (DUT)
lecture4 ttul (
.A(swt[2]),
.B(swt[1]),
.C(swt[0]),
.D(D)
);
// Define the same module functionality for the ... | 7.332089 |
module test_level;
wire [3:0] level;
reg up;
reg down;
reg clk;
reg rst_n;
level U0 (
level,
up,
down,
clk,
rst_n
);
always #5 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
up = 0;
down = 0;
#10 rst_n = 0;
#10 rst_n = 1;
#10 up = 1;
#10... | 6.73827 |
module: model_lexer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_lexer;
// Inputs
reg clk_25mhz;
reg reset;
reg [7:0] data_in;
reg [7:0] data_step;
... | 6.972625 |
module testLibrary (
input signed [15:0] signedInput,
input [15:0] unsignedInput,
output signed [ 7:0] signedSRange,
output [ 7:0] unsignedSPositive,
output [ 7:0] unsignedUPositive,
output signed [15:0] signedRountToZeroExM1
);
clampSRange #(
.INW (16),
.OUT... | 6.999229 |
module test ( //input
pulse_clk,
sys_rst_l,
Xe,
Ye,
change_readyH,
//output
X_acc,
Y_acc,
X_dec,
Y_dec,
draw_overH
);
parameter LO = 1'b0, HI = 1'b1, X = 1'bx;
parameter r_IDLE = 3'b001, r_INIT = 3'b010, r_WORK = 3'b011, r_JUDGE = 3'b100, r_0VER = 3'b101;
reg [2:0] ... | 7.204801 |
module test_ll_axis_bridge;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] ll_data_in = 0;
reg ll_sof_in_n = 1;
reg ll_eof_in_n = 1;
reg ll_src_rdy_in_n = 1;
reg m_axis_tready = 0;
// Outputs
wire ll_dst_rdy_out_... | 8.891994 |
module test_logic_shift ();
parameter CLOCK_CYCLE = 100;
parameter BIT_NUM = 8;
parameter SHIFT_BIT_NUM = 3;
parameter COUNTER_BIT_NUM = BIT_NUM + SHIFT_BIT_NUM + 1;
parameter SIMULATION_PERIOD = 500;
// signal defenition
reg clk;
reg reset;
reg [COUNT... | 7.541332 |
module test_logic_tb ();
reg [7:0] a;
reg [7:0] b;
wire out, out_a, out_b;
wire [7:0] data;
reg clk, load, rst;
test_logic TL (
a,
b,
data,
out_a,
out_b,
out,
clk,
rst,
load
);
initial begin
rst = 0;
clk = 0;
load = 0;
#20 rst... | 6.999757 |
module LUT2 (
input I0,
input I1,
output O
);
wire GP_2LUT_inst0_OUT;
GP_2LUT #(
.INIT(4'h8)
) GP_2LUT_inst0 (
.IN0(I0),
.IN1(I1),
.OUT(GP_2LUT_inst0_OUT)
);
assign O = GP_2LUT_inst0_OUT;
endmodule
| 6.567004 |
module LUT3 (
input I0,
input I1,
input I2,
output O
);
wire GP_3LUT_inst0_OUT;
GP_3LUT #(
.INIT(8'h80)
) GP_3LUT_inst0 (
.IN0(I0),
.IN1(I1),
.IN2(I2),
.OUT(GP_3LUT_inst0_OUT)
);
assign O = GP_3LUT_inst0_OUT;
endmodule
| 6.707736 |
module LUT4 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire GP_4LUT_inst0_OUT;
GP_4LUT #(
.INIT(16'h8000)
) GP_4LUT_inst0 (
.IN0(I0),
.IN1(I1),
.IN2(I2),
.IN3(I3),
.OUT(GP_4LUT_inst0_OUT)
);
assign O = GP_4LUT_inst0_OUT;
endmodule
| 6.884042 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [9:0] test_vector_idx = 0;
reg [7:0] test_vector[0:1023];
integer i;
initial begin
i = 0;
// Zero bytes
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_v... | 6.890266 |
module test_ly_2257_4 ();
reg clk_in; //输入
reg rst;
reg sel;
wire clk_out; //输出
initial //初始化
begin
clk_in = 1'b0;
sel = 1'b0;
rst = 1'b0;
#100 rst = 1'b1;
#200000 sel = 1'b1;
end
always #1 clk_in = ~clk_in; //设置clk_in频率
ly_2257_4 divider (
.clk_in (c... | 7.423298 |
module test_ly_2257_5 ();
// 输入
reg clk;
reg reset_n;
reg key;
// 输出
wire key_state;
wire [3:0] Q;
wire [6:0] codeout;
wire CO;
ly_2257_5 test (
.clk(clk),
.reset_n(reset_n),
.key(key),
.key_state(key_state),
.Q(Q),
.codeout(codeout),
.CO(CO)
);
always... | 7.423298 |
module test_ly_2257_6;
reg Ain, Bin, rst, clkin;
wire [3:0] cnt;
wire [6:0] codeout;
wire A;
wire B;
initial begin
Ain = 0;
Bin = 0;
rst = 0;
clkin = 0;
#10 rst = 1;
end
always #5 clkin <= ~clkin;
always begin
#400 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ai... | 7.423298 |
module test_ly_2257_7 ();
reg clk_in;
reg rst;
reg auto;
reg [13:0] Key;
wire clk_out;
wire clk_out2;
wire [ 7:0] codeout;
wire [ 6:0] low;
wire [ 6:0] middle;
ly_2257_7_3 play (
.clk_in(clk_in),
.rst(rst),
.auto(auto),
.Key(Key),
... | 7.423298 |
module test_mac18x25x20;
// Inputs
reg [24:0] cin;
reg [17:0] din;
reg first;
reg last;
reg clk;
reg rst;
// Outputs
wire [19:0] dout;
wire ov;
wire ovf;
// Instantiate the Unit Under Test (UUT)
mac18x25x20 uut (
.cin(cin),
.din(din),
.first(first),
.last(last),
... | 6.76066 |
module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_main;
// Inputs
reg Clk;
reg rst;
// Outputs
wire [7:0] data_RED;
wire [7:0] data_BLUE;
wire [7:0] data_GRE... | 7.089523 |
module test_main_ctrl #(
parameter CTRL_ADDR_WIDTH = 28,
parameter MEM_DQ_WIDTH = 16,
parameter MEM_SPACE_AW = 18
) (
output [CTRL_ADDR_WIDTH-1:0] random_rw_addr,
output [3:0] random_axi_id,
output [3:0] random_axi_len,
input clk,
input rst_n,
input ddrc_init_done,
output reg i... | 6.802479 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Mux2x10 (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire Mux2_inst8_O;
wire Mux2_inst9_O;
Mux2 Mux2_inst0 ... | 6.548523 |
module Test (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire [9:0] my_mux_O;
Mux2x10 my_mux (
.I0(I0),
.I1(I1),
.S (S),
.O (my_mux_O)
);
assign O = my_mux_O;
endmodule
| 7.402791 |
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