code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x10 (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire Mux2_inst8_O;
wire Mux2_inst9_O;
Mux2 Mux2_inst0 ... | 6.548523 |
module Test (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire [9:0] my_mux_O;
Mux2x10 my_mux (
.I0(I0),
.I1(I1),
.S (S),
.O (my_mux_O)
);
assign O = my_mux_O;
endmodule
| 7.402791 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x10 (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire Mux2_inst8_O;
wire Mux2_inst9_O;
Mux2 Mux2_inst0 ... | 6.548523 |
module Test (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire [9:0] my_mux_O;
Mux2x10 my_mux (
.I0(I0),
.I1(I1),
.S (S),
.O (my_mux_O)
);
assign O = my_mux_O;
endmodule
| 7.402791 |
module: Mario
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_mario;
// Inputs
reg clk;
reg clk_walk_anim;
reg clk_hero_anim;
reg rstn;
reg left;
reg right;
reg jump;
... | 9.086647 |
module test_max_finder_tree;
// Parameters
parameter DATA_WIDTH = 8;
parameter PORT_COUNT = 16;
parameter ADDR_WIDTH = $clog2(PORT_COUNT);
// Inputs
reg [PORT_COUNT*DATA_WIDTH-1:0] values;
// Outputs
wire [DATA_WIDTH-1:0] max_val;
wire [ADDR_WIDTH-1:0] max_ptr;
initial begin
// myhdl integra... | 7.491518 |
module test_Mem;
reg EscreveMemoria;
reg LeMemoria;
reg [7:0] Endereco;
reg [7:0] DadoSalvo;
reg clock;
wire [7:0] DadoCarregado;
initial begin
EscreveMemoria = 1;
LeMemoria = 0;
DadoSalvo = 10;
Endereco = 7;
clock = 0;
#1 clock = 1;
#1;
$display("Valor salvo no endereco ... | 6.80341 |
module test_Memory_Unit ();
parameter word_size = 10;
parameter memory_size = 256;
parameter address_size = 8;
wire [word_size-1:0] data_out;
reg [word_size-1:0] data_in;
reg [address_size-1:0] address;
reg clk, write;
Memory_Unit mem1 (
data_out,
data_in,
address,
clk,
wr... | 7.376101 |
module test_mesh_to_ring_stitch #(
parameter cycle_time_p = 20,
localparam num_tiles_x_p = 8,
localparam num_tiles_y_p = 8,
parameter reset_cycles_lo_p = 1,
parameter reset_cycles_hi_p = 5
);
import bsg_noc_pkg::*; // {P=0, W, E, N, S}
// clock and reset generation
wire clk;
wire reset;
... | 7.186067 |
module Test_MES_AMP_SIN (
output wire S, //S=1, sin(x)>0
input clk,
output wire ce_tact, //ce_tact
input ce,
output wire [`m:0] SIN, //SIN
input [`m-1:0] NT,
output wire ce_S1, //ce_SAMPL1
input [`m:0] NS,
output wire ce_S2, //ce_SAMPL2
input we,
output wire [`m:0] S1, ... | 6.76262 |
module test_microstore_rom;
reg [ 6:0] index; //Las entradas deben ser tipo reg
reg [ 6:0] counter;
wire [44:0] out; // Las salidas deben ser tipo wire
parameter sim_time = 15;
microstore_rom rom (
out,
index
);
initial #sim_time $finish; // Especifica cuando termina simulación
in... | 6.932146 |
module test_mii #(
parameter DATA_WIDTH = 4
) (
input wire clk,
input wire rst,
inout wire [DATA_WIDTH-1:0] mii_d,
inout wire mii_er,
inout wire mii_en,
inout wire mii_clk_en
);
endmodule
| 7.576411 |
module and (a,b,c,d,A_b, Z);
//ports
input [24:0] A_b;
input [-5:5] c;
input [5:-5] d;
input [7:4] a;
input [0:3] b;
output Z;
//wires
wire [24:0] A_b;
wire Z;
endmodule
| 6.739547 |
module test_MMU_XRAM(
input wire clk,
input wire rst_n,
output reg [`VAW-1:0] X_wr,
output reg [`VAW-1:0] X_rd,
output reg [`INTWIDTH*`CORE_N-1:0] X_din,
input wire [`INTWIDTH*`KSIZE-1:0] X_dout,
output reg wr_finish,
output reg X_din_valid,
input wire X_dout_valid,
);
endmodule
| 6.618375 |
module test_moa_8x8p1_tree;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
moa_8x8p1_tree U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.... | 6.902023 |
module test_moa_8x8p2_rt8_fa42;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
moa_8x8p2_rt8_fa42 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),... | 6.902023 |
module test_moa_8x8p2_rt8_mfa42;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
moa_8x8p2_rt8_mfa42 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1... | 6.902023 |
module test_modify_clock_freq ();
reg CLOCK;
reg [15:0] COUNT_LIMIT;
wire PULSE;
modify_clock_freq dut (
CLOCK,
COUNT_LIMIT,
PULSE
);
initial begin
CLOCK = 0;
COUNT_LIMIT = 0;
//COUNT_LIMIT = 16'b0000000000000001; #100;
//COUNT_LIMIT = 16'b0000000000000010; #200;
//C... | 7.508179 |
module: modul01
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_modul01;
// Inputs
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
modul01 uut (
... | 6.931787 |
module: modul03
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_modul03;
// Inputs
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
modul03 uut (
... | 6.813018 |
module: modular_multip
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_modular;
// Inputs
reg clk;
reg reset;
reg [2:0] X;
reg [2:0] Y;
reg [2:0] Z;
// Outputs
wire [4... | 6.974456 |
module test_module03 ();
// Inputs
reg in;
reg [1:0] sel;
// Outputs
/* verilator lint_off UNUSED */
wire [3:0] out;
/* verilator lint_on UNUSED */
// Instantiate the Unit Under Test (UUT)
module03 uut (
.out(out),
.sel(sel),
.in (in)
);
initial begin
$dumpfile("waves03.v... | 7.139646 |
module test_module (
gpio_io,
clk_i,
resetn_i,
apb_penable_i,
apb_psel_i,
apb_pwrite_i,
apb_paddr_i,
apb_pwdata_i,
apb_prdata_o,
apb_pslverr_o,
apb_pready_o,
int_o
);
inout [7:0] gpio_io;
input clk_i;
input resetn_i;
input apb_penable_i;
input apb_psel_i;
inpu... | 6.581827 |
module test_mono_cpu_mips ();
reg clk;
wire [31:0] pc;
mono_cpu cpu (
.clk(clk),
.pc (pc)
);
initial clk = 1'b1;
always begin
#1 clk = ~clk;
if (pc == 32'h98 || pc == 32'h90) $stop;
end
endmodule
| 7.728514 |
module Test_Motherboard;
reg success_flag;
reg rst, clk;
initial begin
success_flag = 1;
rst = 0;
clk = 0;
#5 rst = 1;
#5 rst = 0;
#5
// Print out Success/Failure message
if (success_flag == 0) begin
$display("*FAILED* TEST!");
end else begin
$display("**PASSED** T... | 6.674003 |
module top (
input clk,
input rst,
input [10:0] switch,
output reg [1:0] direction,
output pwm,
output [1:0] led
);
wire [9:0] duty;
assign led[0] = pwm;
assign led[1] = (direction == `MOTOR_FORWARD);
assign duty[9:0] = switch[9:0];
always @(posedge clk) begin
direction <= (swit... | 7.233807 |
module PWM_gen (
input wire clk,
input wire reset,
input [31:0] freq,
input [9:0] duty,
output reg PWM
);
wire [31:0] count_max = 100_000_000 / freq;
wire [31:0] count_duty = count_max * duty / 1024;
reg [31:0] count;
always @(posedge clk, posedge reset) begin
if (reset) begin
co... | 6.517179 |
module test_mul16 (
input [15:0] a,
input [15:0] b,
output [15:0] out
);
assign out = a * b;
endmodule
| 6.773596 |
module test_multiplier;
reg a0, a1, a2, b0, b1, b2;
wire [6:0] led_o, led_t;
multiplier M1 (
a0,
a1,
a2,
b0,
b1,
b2,
led_o,
led_t
);
initial begin
a0 = 1'b0;
a1 = 1'b0;
a2 = 1'b0; //0x4
b0 = 1'b0;
b1 = 1'b0;
b2 = 1'b1;
#10 a0 = 1'b0;... | 6.529891 |
module test_multiplier_6 (
input clk,
input rst,
input start,
output reg [1:0] status
);
reg [4:0] M_test_counter_d, M_test_counter_q = 1'h0;
localparam IDLE_state = 2'd0;
localparam TEST_state = 2'd1;
localparam PASS_state = 2'd2;
localparam FAIL_state = 2'd3;
reg [1:0] M_state_d, M_st... | 6.529891 |
module test_multi_cycle_cpu ();
reg clk;
reg resetn;
wire [31:0] IF_pc;
wire [31:0] IF_inst;
wire [31:0] ID_pc;
wire [31:0] EXE_pc;
wire [31:0] MEM_pc;
wire [31:0] WB_pc;
wire [2:0] display_state;
wire [31:0] rf_data;
wire [31:0] mem_data;
multi_cycle_cpu multi_cycle_cpu (
.clk(clk),
... | 6.517225 |
module test_multX ();
parameter WIRE = 8;
reg [WIRE-1:0] A, B;
wire [WIRE-1:0] out;
multX #(
.WIRE(WIRE)
) inst_multX (
A,
B,
8'b0,
out
);
initial begin
$dumpfile("signal_multX.vcd");
$dumpvars;
$display("\t\ttime,\tA,\tB, \tout");
$monitor("%d \t%d \t%d \t... | 6.708963 |
module test_mul_add16 (
input [15:0] a,
input [15:0] b,
input [15:0] c,
output [15:0] out
);
assign out = (a * b) + c;
endmodule
| 6.744817 |
module test_mux;
parameter SIZE_CTRL = 2;
parameter WIRE = 1;
wire [WIRE - 1 : 0] out;
reg [2 ** SIZE_CTRL - 1 : 0] in;
reg [1 : 0] ctrl;
mux #(
.SIZE_CTRL(SIZE_CTRL),
.WIRE(WIRE)
) mux0 (
ctrl,
in,
out
);
initial begin
$dumpfile("signal_mux.vcd");
$dumpvars;
... | 7.502555 |
module test_mux16;
reg [0:15] in;
reg [0:3] sel;
wire out;
mux16to1 mux (
out,
in,
sel
);
initial begin
$monitor("in :%b | sel : %b | out: %b", in, sel, out);
end
initial begin
in = 16'b0100000000000000;
sel = 4'b0000;
#3 in = 16'b0100000000000000;
sel = 4'b000... | 7.029338 |
module test_mux8;
parameter SIZE_CTRL = 2;
parameter WIRE = 8;
localparam NB_IN = 2 ** SIZE_CTRL;
localparam SIZE_IN = NB_IN * WIRE;
wire [ WIRE - 1 : 0] out;
reg [SIZE_IN - 1 : 0] in;
reg [SIZE_CTRL-1 : 0] ctrl;
integer cpt1;
integer cpt2;
reg ... | 7.373202 |
module: mux_16to1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_mux_16to1;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
reg [31:0] D;
reg [31:0] E;
reg [31:0] F... | 7.639724 |
module test_mux_16x1;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
reg [31:0] I1; //Las entradas del módulo deben ser tipo reg
reg [31:0] I2; //Las entradas del módulo deben ser tipo reg
reg [31:0] I3; //Las entradas del módulo deben ser tipo reg
reg [31:0] I4; //Las entradas del mód... | 6.773965 |
module mux_16to1_test;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg [15:0] C;
reg [15:0] D;
reg [15:0] E;
reg [15:0] F;
reg [15:0] G;
reg [15:0] H;
reg [15:0] I;
reg [15:0] J;
reg [15:0] K;
reg [15:0] L;
reg [15:0] M;
reg [15:0] O;
reg [15:0] P;
reg [15:0] Q;
reg [ 3:0... | 6.563488 |
module test_mux_1_2 (
data0,
data1,
ctrl,
out
);
input [0:0] data0, data1;
input [1:0] ctrl;
output [0:0] out;
wire [0:0] data0, data1;
wire [1:0] ctrl;
wire [0:0] out;
AO22XL g18 (
.A0(data0),
.A1(ctrl[0]),
.B0(data1),
.B1(ctrl[1]),
.Y (out)
);
endmodule
| 6.593147 |
module test_mux_1_32 (
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
data8,
data9,
data10,
data11,
data12,
data13,
data14,
data15,
data16,
data17,
data18,
data19,
data20,
data21,
data22,
data23,
data24,
dat... | 6.655391 |
module test_mux_1_4 (
data0,
data1,
data2,
data3,
ctrl,
out
);
input [0:0] data0, data1, data2, data3;
input [3:0] ctrl;
output [0:0] out;
wire [0:0] data0, data1, data2, data3;
wire [3:0] ctrl;
wire [0:0] out;
wire n_0, n_1;
NAND2X1 g36 (
.A(n_1),
.B(n_0),
.Y(o... | 6.647864 |
module test_mux_2to1_32bit ();
reg [31:0] inp1, inp2;
reg sel;
wire [31:0] outp;
mux_2to1_32bit mx (
outp,
inp1,
inp2,
sel
);
initial begin
$monitor(" inp1: %b ", inp1, " inp2: %b ", inp2, " sel: ", sel, " outp: %b ", outp);
end
initial begin
inp1 = 32'b00000000000000... | 7.468822 |
module test_mux_2to1_8bit ();
reg [7:0] inp1, inp2;
reg sel;
wire [7:0] outp;
mux_2to1_8bit mx (
outp,
inp1,
inp2,
sel
);
initial begin
inp1 = 8'b10101010;
inp2 = 8'b01010101;
sel = 1'b0;
#100 sel = 1'b1;
#1000 $finish;
end
initial $monitor(" inp1 = %b ", ... | 7.468822 |
module test_mux_2x1;
reg [2:0] I;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
reg [31:0] I1; //Las entradas del módulo deben ser tipo reg
wire [31:0] Y; //Las salidas deben ser tipo wire
reg S;
parameter sim_time = 100;
mux_2x1 mux1 (
Y,
S,
I0,
I1
); // Instan... | 6.929887 |
module test_mux_2x1_4;
reg [2:0] I;
reg [3:0] I0; //Las entradas del módulo deben ser tipo reg
reg [3:0] I1; //Las entradas del módulo deben ser tipo reg
wire [3:0] Y; //Las salidas deben ser tipo wire
reg S;
parameter sim_time = 100;
mux_2x1_4 mux1 (
Y,
S,
I0,
I1
); // Insta... | 6.810985 |
module test_mux_32to1 ();
// Inputs
reg [31:0] X;
reg [4:0] S;
// Outputs
wire Z;
// Instantiate the Unit Under Test (UUT)
mux_32to1 uut (
.X(X),
.S(S),
.Z(Z)
);
initial begin
// Initialize Inputs
X = 32'b11000000000000000000000001010101;
S = 4'b0000;
// Wait 100... | 8.005332 |
module test_mux_3to1_32bit ();
reg [31:0] in1, in2, in3;
reg [ 1:0] sel;
wire [31:0] outp;
mux_3to1_32bit mx (
outp,
in1,
in2,
in3,
sel
);
initial begin
$monitor(" in1: %b", in1, " in2: %b", in2, " in3: %b", in3, " sel: %b", sel, " out: %b", outp);
end
initial begi... | 7.240672 |
module test_mux_4in_1out ();
reg in0, in1, in2, in3;
reg [1:0] select;
wire out;
mux_4in_1out mux4in1out (
{in3, in2, in1, in0},
select,
out
);
always #0.1 in0 = ~in0;
always #0.5 in1 = ~in1;
always #1 in2 = ~in2;
always #5 in3 = ~in3;
initial begin
$dumpfile("out_mux.... | 7.490018 |
module test_mux_4x1;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
reg [31:0] I1; //Las entradas del módulo deben ser tipo reg
reg [31:0] I2; //Las entradas del módulo deben ser tipo reg
reg [31:0] I3; //Las entradas del módulo deben ser tipo reg
wire [31:0] Y; //Las salidas deben ser t... | 7.00211 |
module test_mux_4x1_4;
reg [3:0] I0; //Las entradas del módulo deben ser tipo reg
reg [3:0] I1; //Las entradas del módulo deben ser tipo reg
reg [3:0] I2; //Las entradas del módulo deben ser tipo reg
reg [3:0] I3; //Las entradas del módulo deben ser tipo reg
wire [3:0] Y; //Las salidas deben ser tipo... | 7.361327 |
module test_mux_4x1_cu;
reg I0; //Las entradas del módulo deben ser tipo reg
reg I1; //Las entradas del módulo deben ser tipo reg
reg I2; //Las entradas del módulo deben ser tipo reg
reg I3; //Las entradas del módulo deben ser tipo reg
wire Y; //Las salidas deben ser tipo wire
reg [1:0] S;
parameter ... | 7.361327 |
module test_mux_4_1 ();
// Inputs.
reg a;
reg b;
reg c;
reg d;
reg [1:0] sel;
reg i;
reg j;
reg k;
reg l;
/* verilator lint_off UNUSED */
reg out;
wire res;
/* verilator lint_on UNUSED */
// Initializing UUT.
mux_4_1 UUT (
.out (res),
.in0 (a),
.in1 (b),
.in2 (c... | 6.882895 |
module test_mux_8_2 (
data0,
data1,
ctrl,
out
);
input [7:0] data0, data1;
input [1:0] ctrl;
output [7:0] out;
wire [7:0] data0, data1;
wire [1:0] ctrl;
wire [7:0] out;
AO22XL g107 (
.A0(data0[1]),
.A1(ctrl[0]),
.B0(data1[1]),
.B1(ctrl[1]),
.Y (out[1])
);
... | 7.324161 |
module TEST_MUX_Four_1 ();
reg [3:0] D;
reg [1:0] S;
wire Out;
initial begin
#100 D = 4'b0001;
S = 2'b00;
#100 D = 4'b0010;
S = 2'b10;
#100 D = 4'b0000;
S = 2'b01;
#100 D = 4'b1000;
S = 2'b11;
#100 $stop;
end
Four_1_Mux Inst0 (
Out,
S,
D
);
end... | 6.609162 |
module test_myDAC ();
reg CLOCK;
reg RESET;
reg btnU;
reg btnD;
wire [3:0] JA;
wire LED;
myDAC dut (
CLOCK,
RESET,
btnU,
btnD,
JA,
LED
);
initial begin
CLOCK = 0;
RESET = 0;
btnU = 0;
btnD = 0;
end
always begin
#5 CLOCK = ~CLOCK;
en... | 6.663396 |
module test_uart;
// Transmitter Ports
reg i_Tx_Dv;
reg [7:0] i_Tx_Byte;
reg i_clk;
// Receiver Ports:
wire [7:0] o_Rx_Byte;
wire o_Rx_Dv;
// Define Parameter : Purpose : To get the clock of 10MHz and the Baud Rate of 115200.
// So the CLK_CY_PER_BIT = 87 (Approx.)
parameter IN_CLK_PER = 100; /... | 7.673351 |
module test_uart_rx;
//Define the variables same as the ports of DUT (UART Receiver)
reg i_clk;
reg i_Rx_Serial;
wire o_Rx_Dv;
wire [7:0] o_Rx_Byte;
// To Cross checke wheather the data is received is correct or not:
reg r_parity_check;
reg [7:0] r_in_Byte;
reg [10:0] r_in_serial;
reg [3:0] r_bit_... | 7.014426 |
module test_uart_tx;
// Definig the variables same as port of DUT(UART TX):
reg i_clk;
reg i_Tx_Dv;
reg [7:0] i_Tx_Byte;
wire o_Tx_Active;
wire o_Tx_Serial;
wire o_Tx_Done;
//Internal variable to save the expected parity output:
reg r_exp_parity;
// Purpose : Define the parameter to get the clk o... | 7.694888 |
module test_my_mux4way16 ();
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
reg [15:0] d;
reg [ 1:0] s;
reg [15:0] expected;
wire [15:0] e;
my_mux4way16 u1 (
e,
a,
b,
c,
d,
s
);
initial begin
a = 16'b0101010101010101;
b = 16'b1010101010101010;
c = ... | 7.012634 |
module test_my_mux8way16 ();
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
reg [15:0] d;
reg [15:0] e;
reg [15:0] f;
reg [15:0] g;
reg [15:0] h;
reg [ 2:0] sel;
reg [15:0] expected;
wire [15:0] j;
my_mux8way16 u1 (
j,
a,
b,
c,
d,
e,
f,
g,
... | 7.517702 |
module test_N16;
parameter period = 5;
reg clk, rstn;
reg [15:0] in1, in2;
wire [16:0] res;
CAP_N16_R4_P2 DUT (
.clk (clk),
.rstn(rstn),
.in1 (in1),
.in2 (in2),
.res (res)
);
always #period clk = ~clk;
//reset
initial begin
clk = 0;
rstn = 0;
in1 = 0;
... | 6.58306 |
module test_nco (
input wire clk,
output wire [23:0] wave
);
wire [11:0] ph;
nco #(
.WIDTH(12),
.PHASE(23)
) nco (
.clk(clk),
.inc(2237),
.out(ph)
);
wire [16:0] sin;
sincos sc (
.clk(clk),
.phase(ph),
.out_sin(sin),
.out_cos()
);
assign w... | 7.397517 |
module test_next_pc;
wire [31:0] cur_pc;
reg [31:0] imm;
reg branch;
reg zero;
wire [31:0] next_pc;
reg ce;
//reg [31:0] addr;
wire [31:0] inst;
reg clk;
reg rst_n;
initial begin
clk = 0;
rst_n = 0;
#100 rst_n = 1'b1;
ce = 1'b... | 6.571956 |
module test_not (
N1,
N2
);
input N1;
output N2;
not INV1_1 (N2, N1);
endmodule
| 6.747666 |
module: ntsc_clean
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ntsc_clean;
// Inputs
reg clock_65mhz;
reg ntsc_flag;
reg [35:0] ntsc_pixels;
// Outputs
wire clean_nt... | 7.704849 |
module test_num ();
reg [7:0] mem[3:0];
wire [7:0] a;
assign a = mem[0];
initial begin
mem[0] = 8'b0000_0000;
#1 $display("a = %b", a);
$finish();
end
endmodule
| 6.630698 |
module
module test_numbers_top(
input Clock,
input reset,
output HS_probe,
output VS_probe,
output hsync,
output vsync,
output [3:0]VGA_R,
output [3:0]VGA_G,
output [3:0]VGA_B
);
wire display_on;
wire [9:0] hpos;
wire [9:0] vpos;
video_sync_generator hvsync_gen(
.clk(Clock),
.re... | 6.755183 |
module test_ofb_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
OFB_dec e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("ofb_enc.txt", msg);
//$... | 6.528458 |
module test_ofb_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
OFB_enc e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("binary.txt", msg);
//$d... | 6.615351 |
module open_drain_pin #(
parameter tick_interval = 32'd27000000
) (
input clk_i,
input rst_ni,
input listen_first_i,
output led_recv_o,
output reg led_done_o = 1'b1,
inout pin_io
);
localparam INIT = 3'd0;
localparam LISTEN = 3'd1;
localparam TALK = 3'd2;
localparam IDLE = 3'd3;
... | 8.290052 |
module test_open_drain #(
parameter tick_interval = 32'd27000000
) (
input clk_i,
input rst_ni,
inout pin1_io,
inout pin2_io,
output led_recv_1_o,
output led_done_1_o,
output led_recv_2_o,
output led_done_2_o
);
open_drain_pin #(
.tick_interval(tick_interval)
) p1 (
... | 7.970321 |
module i2c_tb ();
reg clk_r = 1'b0;
reg rst_nr = 1'b1;
always #1 clk_r = ~clk_r;
wire pin;
pullup (pin);
wire led_recv_1;
wire led_recv_2;
wire led_done_1;
wire led_done_2;
test_open_drain #(
.tick_interval(10)
) odt (
.clk_i (clk_r),
.rst_ni(rst_nr),
.pin1_io(pin),
... | 7.100397 |
module ROM128x32 (
addr,
data
);
input [6:0] addr;
output [31:0] data;
reg [31:0] data;
reg [31:0] mem[0:127];
integer i;
initial begin
// Initialize the instruction memory
$readmemh(`IMEM_INIT, mem);
$display("Reading instruction memory......");
end
always @(addr) data = mem[add... | 7.116055 |
module test;
// Clock period, ns
parameter CLOCK_PERIOD = 500;
// Pulse width, gap and break delay
parameter PWID = 500;
parameter PGAP = 500;
parameter BREAK = 25000; // 25us
// time constants
localparam USEC = 1000;
localparam MSEC = 1000000;
// Output waveform file for this test
initial be... | 7.816888 |
module test_p2s (
pdata24,
pdata16,
sdata24,
sdata16
);
input pdata24, pdata16;
output sdata24, sdata16;
input [23:0] pdata24;
input [15:0] pdata16;
//<statements>
endmodule
| 6.953236 |
module test_padder1;
// Inputs
reg [31:0] in;
reg [ 1:0] byte_num;
// Outputs
wire [31:0] out;
reg [31:0] wish;
// Instantiate the Unit Under Test (UUT)
padder1 uut (
.in(in),
.byte_num(byte_num),
.out(out)
);
initial begin
// Initialize Inputs
in = 0;
byte_num ... | 6.510528 |
module TOP;
//ALU inputs
wire [63:0] out;
reg [63:0] MM_A, MM_B;
reg [31:0] imm;
reg [2:0] op;
wire [63:0] out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
op = 3'b010;
MM_A = 64'h0000_0000_0000_0082;
... | 7.259416 |
module test_panel_adapter (
input clk,
input test_panel_select_n,
input [15:0] led_vals_in,
output [15:0] led_vals_out
);
synchronous_two_input_multiplexer #(
.WIDTH(16)
) mux (
.clk(clk),
.select(test_panel_select_n),
.in0({led_vals_in[7:0], led_vals_in[15:... | 6.999476 |
module f8_test (
in1,
in2,
out1,
out2,
io1,
io2
);
inout [1:0] io1;
inout [0:1] io2;
output [1:0] out1;
output [0:1] out2;
input [1:0] in1;
input [0:1] in2;
endmodule
| 7.583792 |
module f9_test (
q,
d,
clk,
reset
);
output reg q;
input d, clk, reset;
always @(posedge clk, negedge reset)
if (!reset) q <= 0;
else q <= d;
endmodule
| 6.818192 |
module f2_test #(
parameter v2kparam = 5
) (
in,
out,
io,
vin,
vout,
vio
);
input in;
output out;
inout io;
input [3:0] vin;
output [v2kparam:0] vout;
inout [0:3] vio;
parameter myparam = 10;
endmodule
| 6.635754 |
module test ();
import alu_ops::*;
`include "../lib/display_snippet.sv"
logic clk = 0;
cpu CPU (
1'b0,
clk
);
////////////////////////////////////////////////////////////////////////////////////////////////////
// TESTS ======================================================================... | 6.913895 |
module test_patterns (
input reset,
input clk,
input active_pixel,
input hsync_in,
input vsync_in,
output reg [7:0] r_out,
output reg [7:0] g_out,
output reg [7:0] b_out
);
reg [11:0] ramp = 12'd0;
always @(posedge clk) begin
if (reset) ramp <= 8'd0;
else if (hsync_in) ramp... | 7.186961 |
module test_pattern_2 (
/*
just mux output between two values. not sure if this is useful.
versus real az.
*/
input clk, // master clk.
input [`NUM_BITS - 1 : 0] reg_direct, // synchronous on spi_clk.
input [`NUM_BITS - 1 : 0] reg_direct2, // synchronous on spi_clk.
output reg [`NUM_... | 6.982463 |
module test_pattern_previo_640x480 (
CLK100MHZ,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
input CLK100MHZ;
output VGA_HS, VGA_VS;
output [3:0] VGA_R, VGA_G, VGA_B;
wire [9:0] vc_visible, hc_visible;
reg [1:0] counter_clk_vga, counter_clk_vga_next;
wire clk_vga;
always @(*) counter_... | 6.982463 |
module test_pattern_tb #() ();
localparam ADDRESS_WIDTH = 16;
localparam DATA_WIDTH = 8;
localparam DATA_BYTES = 1;
reg rst_i;
reg clk_i;
wire [ADDRESS_WIDTH-1:0] adr_o;
reg [ DATA_WIDTH-1:0] dat_i;
wire [ DATA_WIDTH-1:0] dat_o;
wire ... | 6.982463 |
module test_PC;
reg [7:0] valorEntradaPC;
reg EscrevePC, clock;
wire [7:0] valorPC;
initial begin
clock = 0;
EscrevePC = 1;
valorEntradaPC = 1;
#1 clock = 1;
#1 clock = 0;
valorEntradaPC = 2;
#1 clock = 1;
EscrevePC = 0;
#1 EscrevePC = 1;
#1 clock = 0;
#1 clock = 1;... | 6.560331 |
module test_pcie_us_axi_master_wr_128;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 128;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_... | 7.787107 |
module test_pcie_us_axi_master_wr_256;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 256;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_... | 7.787107 |
module test_pcie_us_axi_master_wr_512;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 512;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI... | 7.787107 |
module test_pcie_us_axi_master_wr_64;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 64;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_DA... | 7.787107 |
module top;
wire clock, reset;
clockgen clkg (
.clk(clock),
.rst(reset)
);
design_wrapper dut (
.clock(clock),
.reset(reset)
);
`ifdef VCD
initial begin
$dumpfile(`VCD_FILE);
$dumpvars;
end
`endif
`include "tracegen.v"
endmodule
| 6.535004 |
module test_pet2001ps2_key;
// Inputs
reg [3:0] keyrow;
reg ps2_clk;
reg ps2_data;
reg clk;
reg reset;
// Outputs
wire [7:0] keyin;
// Instantiate the Unit Under Test (UUT)
pet2001ps2_key
uut (
.keyin(keyin),
.keyrow(ke... | 7.003772 |
module test_pet2001uart_keys;
reg [3:0] keyrow;
wire [7:0] keyin;
reg [7:0] uart_data;
reg uart_strobe;
reg clk;
reg reset;
initial begin
keyrow = 4'hf;
uart_data = 8'd0;
uart_strobe = 1'b0;
clk = 1'b0;
reset = 1'b1;
end
always #10.0 clk = ~clk; // 50Mhz
... | 6.691541 |
module for Pet2001_Arty and Pet2001Real_Arty.
//
module test_Pet2001_Arty;
reg [2:0] SW;
reg BTN;
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire VGA_HSYNC;
wire VGA_VSYNC;
wire AUDIO;
wire CASS_WR;
reg CASS_RD;
reg PS... | 7.92237 |
module test_PE_0 ();
parameter cycle = 10;
reg clk;
reg rst;
wire [31:0] PE_0_dout_N;
wire [31:0] PE_0_dout_S;
wire [31:0] PE_0_dout_W;
wire [31:0] PE_0_dout_E;
reg init, run;
reg [27:0] PE_inst;
reg [31:0] din_N_i;
reg [31:0] din_S_i;
reg [31:0] din_W_i;
reg [31:0] din_E_i;
... | 6.671543 |
module test_pid;
localparam RATE_BIT_WIDTH = 36;
localparam VELOCITY_BIT_WIDTH = 36;
localparam ROTATION_BIT_WIDTH = 36;
// rates represented in 2's complement fixed point
wire [RATE_BIT_WIDTH-1:0] yaw_rate_out;
wire [RATE_BIT_WIDTH-1:0] roll_rate_out;
wire [RATE_BIT_WIDTH-1:0] pitch_rate_out;
// rat... | 8.032064 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.