code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_pipeline_propagation_core;
reg clk;
reg arst;
localparam data_width = 32;
localparam pstage = 3;
initial clk = 1'b0;
always begin
#(`CLOCK_PERIOD / 2) clk = ~clk;
end
initial begin
arst = 1'b1;
#(10.5 * `CLOCK_PERIOD);
arst = 1'b0;
end
reg [data_width-1:0] data_in;
... | 6.631713 |
module test_player2 (
CLOCK_50,
KEY,
LEDR,
LEDG
);
input CLOCK_50;
input [3:0] KEY;
output [17:0] LEDR;
output [7:0] LEDG;
wire [27:0] one_hz = 28'b0010111110101111000010000000;
reg [19:0] p1_value = 6'b101110;
wire clock;
rate_divider rate0 (
.clock_in(CLOCK_50),
.clock_... | 6.642622 |
module test_pmod_top (
//switch
input wire [15:0] switch,
//led
output wire [15:0] led,
//pmod
output wire [7:0] Ja,
output wire [7:0] Jb,
output wire [7:0] Jc,
output wire [7:0] Jd
);
assign led = switch;
assign Ja = 8'h80;
assign Jb = switch[15:8];
assign Jc = 8'b0;
... | 7.543842 |
module mux2_32 (
D_EXT1,
negative,
Z_ena,
D_negative,
carry,
D_carry,
EXT1_n_c
);
output [0:0] D_EXT1;
input negative;
input Z_ena;
input D_negative;
input carry;
input D_carry;
input EXT1_n_c;
wire [0:0] D_EXT1;
wire D_carry;
wire D_negative;
wire EXT1_n_c;
wire Z_e... | 6.85623 |
module test_ppcm_nexys3 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// PPCM interfaces
output wire pcm_ce_n,
output wire pcm_rst_n,
output wire pcm_oe_n,
o... | 8.436736 |
module test_priority_encoder;
// Parameters
localparam WIDTH = 32;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_unencoded = 0;
// Outputs
wire output_valid;
wire [$clog2(WIDTH)-1:0] output_encoded;
wire [WIDTH-1:0] output_unencoded;
initial begin
... | 7.096955 |
module alu (
out,
Data1,
Data2,
Select
);
input [7:0] Data1, Data2;
input [2:0] Select;
output reg [7:0] out;
always @(Data1, Data2, Select) begin
case (Select)
3'b000: out <= Data1;
3'b001: out <= Data1 + Data2;
3'b010: out <= Data1 & Data2;
3'b011: out <= Data1 | D... | 7.812586 |
module CU (
OUT1addr,
OUT2addr,
INaddr,
immediate,
Select,
imm_signal,
comp_signal,
instruction
);
input [31:0] instruction;
output reg [7:0] immediate;
output reg imm_signal;
output reg [2:0] Select;
output reg [2:0] OUT1addr;
output reg [2:0] OUT2addr;
output reg [2:0] I... | 7.902187 |
module mux (
out,
select,
input1,
input2
);
input select;
input [7:0] input1, input2;
output reg [7:0] out;
always @* begin
if (select == 1) out = input1;
else out = input2;
end
endmodule
| 7.812393 |
module compliment (
out,
in
);
input [7:0] in;
output [7:0] out;
reg [7:0] comp = 8'b11111111;
assign out = (comp - in) + 8'b00000001;
endmodule
| 6.612524 |
module regInstructions (
instruction,
clk,
Read_Addr
);
input clk;
input [2:0] Read_Addr;
output reg [31:0] instruction;
reg [31:0] addr1 = 32'b00001000000001000000000011111111; // loadi 4, X, 0xFF
reg [31:0] addr2 = 32'b00001000000001100000000010101010; // loadi 6, X, 0xAA
reg [31:0] addr3 =... | 7.583668 |
module test_Processing_Unit ();
parameter word_size = 10;
parameter data_size = 8;
parameter op_size = 4;
parameter Sel1_size = 3;
parameter Sel2_size = 3;
reg [6:0] address_decoded;
reg [7:0] constant_decoded;
reg [word_size-1:0] mem_word;
reg Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC;
re... | 6.763534 |
module TOP;
//ALU inputs
reg a, b;
wire p;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 0;
b = 0;
#`cycle //1
if(p != (a | b))
begin
error_free = 0;
error... | 7.259416 |
module TOP;
//ALU inputs
reg [31:0] a, b;
wire [31:0] p;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(p != (a | b))
begin
... | 7.259416 |
module Test_Proyect;
// Entradas
reg Clock_Nexys;
reg Reset;
reg reset_Clck;
reg data_ADC;
reg start;
reg [11:0] Entrada_referencia;
// Salidas
wire CS;
wire Clock_Muestreo;
wire [3:0] data_basura;
wire pwm_out;
wire [17:0] IPD;
// Unit Under Test (UUT)
Servo_Top uut (
.Clock_Nexy... | 7.763372 |
module test_ps2 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] cmd,
output wire [31:0] data,
output wire [7:0] state,
// PS2 interfaces
inout wire ps2_clk,
inout wire ps2_dat
);
parameter CLK_FREQ = 100;
wire [ 7:0] ... | 7.837163 |
module test_ps2_keyboard (
/* PS/2 inputs */
PS2_CLK,
PS2_DAT,
HEX0,
HEX1
);
input PS2_CLK;
input PS2_DAT;
output [6:0] HEX0, HEX1;
wire [7:0] data_out;
wire data_complete;
reg [3:0] hex0_val, hex1_val;
ps2_keyboard keyboard_input (
.ps2_clock(PS2_CLK),
.ps2_data(PS2_D... | 7.581791 |
module test_psram_nexys3 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// PSRAM interfaces
output wire ram_ce_n,
output wire ram_clk,
output wire ram_oe_n,
o... | 8.926065 |
module test_ptp_clock (
input wire clk,
input wire rst,
inout wire [95:0] ts_96,
inout wire [63:0] ts_64,
inout wire ts_step,
inout wire pps
);
endmodule
| 7.202445 |
module test_ptp_clock_cdc_64;
// Parameters
parameter TS_WIDTH = 64;
parameter NS_WIDTH = 4;
parameter FNS_WIDTH = 16;
parameter INPUT_PERIOD_NS = 4'h6;
parameter INPUT_PERIOD_FNS = 16'h6666;
parameter OUTPUT_PERIOD_NS = 4'h6;
parameter OUTPUT_PERIOD_FNS = 16'h6666;
parameter USE_SAMPLE_CLOCK = 1;
... | 7.202445 |
module test_ptp_clock_cdc_96;
// Parameters
parameter TS_WIDTH = 96;
parameter NS_WIDTH = 4;
parameter FNS_WIDTH = 16;
parameter INPUT_PERIOD_NS = 4'h6;
parameter INPUT_PERIOD_FNS = 16'h6666;
parameter OUTPUT_PERIOD_NS = 4'h6;
parameter OUTPUT_PERIOD_FNS = 16'h6666;
parameter USE_SAMPLE_CLOCK = 1;
... | 7.202445 |
module test_ptp_clock_sim_time (
input wire clk,
inout wire [95:0] ts_96,
inout wire [63:0] ts_64,
inout wire pps
);
endmodule
| 7.202445 |
module test_ptp_perout;
// Parameters
parameter FNS_ENABLE = 1;
parameter OUT_START_S = 48'h0;
parameter OUT_START_NS = 30'h0;
parameter OUT_START_FNS = 16'h0000;
parameter OUT_PERIOD_S = 48'd1;
parameter OUT_PERIOD_NS = 30'd0;
parameter OUT_PERIOD_FNS = 16'h0000;
parameter OUT_WIDTH_S = 48'h0;
par... | 7.793635 |
module pulse_detect_tb ();
reg clk_fast;
reg clk_slow;
reg rst_n;
reg data_in;
wire dataout;
pulse_detect dut (
.clk_fast(clk_fast),
.clk_slow(clk_slow),
.rst_n(rst_n),
.data_in(data_in),
.dataout(dataout)
);
initial begin
clk_fast = 0;
clk_slow = 0;
rst_... | 6.636089 |
module Test_PulseCapture;
reg success_flag;
reg clk, rst;
reg oe, clr;
reg ext_pulse;
reg trigger;
reg int_clr;
wire [31:0] data;
wire int;
integer i;
pulseCapture U0 (
.clk(clk),
.rst(rst),
.oe(oe), // output enable
.clr(clr), // clear
.trigger(trigger), // start a capture
.ext_pulse(... | 7.006226 |
module test_pwm_generator;
// pwm_generator module testbench
`timescale 1ns/1ns
/*
* Tested:
* Basic functionality
*
* To test:
* Mid-period input value change
* 0 input value
* >250 input value
*/
reg [7:0] m_1_rate, m_2_rate, m_3_rate, m_4_rate;
wire m_1_pwm, m_2_pwm, m_3_pwm, m_4_pwm;
reg rst, clk;
// TO... | 6.640256 |
module test_pwm_reader;
localparam SUCCESS = 1'b0;
localparam FAIL = 1'b1;
localparam [10:0] INITIAL_PULSE_HIGH_US = 1500;
wire sys_clk;
wire us_clk;
wire [10:0] pwm_pulse_length_us;
reg pwm = 0;
reg resetn = 1;
reg result = SUCCESS;
defparam OSCH_inst.NOM_FREQ = "38.00";
OSCH OSCH_inst (
... | 7.567604 |
module test_ram32x20(
/* clock input */
CLOCK_50,
/* inputs */
KEY,
SW,
LEDR,
);
input CLOCK_50;
input [17:0] SW;
input [2:0] KEY;
output [17:0] LEDR;
wire [3:0] data_out;
reg [4:0] counter;
ram32x20 ram0(
.data(SW[16:0]),
.address(counter),
... | 6.810588 |
module test_ram_256;
reg [31:0] DataIn; //Las entradas del módulo deben ser tipo reg
reg [7:0] Address;
wire [31:0] DataOut;
wire MFC;
reg RW, Enable;
reg [1:0] DataSize;
reg [2:0] counter;
parameter sim_time = 15;
ram_256 ram_module (
DataOut,
MFC,
Enable,
RW,
Address... | 6.545766 |
module test_RAM_rn (
clk,
rst
);
//------------------------------------------------------------------
// -- Input/Output Declarations --
//------------------------------------------------------------------
input clk, rst;
//----------------------------------------... | 6.740844 |
module test_rconst;
// Inputs
reg [23:0] i;
// Outputs
wire [63:0] rc;
// Instantiate the Unit Under Test (UUT)
rconst uut (
.i (i),
.rc(rc)
);
initial begin
// Initialize Inputs
i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i = 0;... | 6.567675 |
module test_rdyackin_rdyackout ();
//Interfaccia ingresso MMU
reg lineaRdyIn;
reg lineaAckIn;
reg betaRdyIn; //per resettare RdyIn
reg betaAckIn; //per resettare AckIn
reg betaRdyOut; //per settare RdyOut
reg betaAckOut; //per settare AckOut
wire rdyIn;
wire ackIn;
wire rdyOut;
wire a... | 7.613287 |
module test ();
localparam verbose = 0;
// 33 exclamation mark
tri [7:0] BUS;
logic [7:0] Dtx;
logic WR;
logic _RD;
wire _TXE;
wire _RXF;
reg [7:0] RECEIVED;
`include "timings.v"
assign BUS = Dtx;
reg [12*8:0] expected;
integer countTx = 0;
integer countRx = 0;
integer MAX_RX = -1;
... | 7.528945 |
module Test_Read_MUX;
// Inputs
reg CLK;
reg RST;
reg [31:0] HRDATA_1;
reg [31:0] HRDATA_2;
reg [31:0] HRDATA_3;
reg [1:0] SEL;
// Outputs
wire [31:0] HRDATA;
// Instantiate the Unit Under Test (UUT)
Read_MUX uut (
.CLK(CLK),
.RST(RST),
.HRDATA(HRDATA),
.HRDATA_1(HRDATA_... | 7.370382 |
module test_receiver;
localparam SUCCESS = 1'b1;
localparam FAIL = 1'b0;
reg result = SUCCESS;
// scaled output values corresponding to their pwm input counterpart
wire [`PWM_VALUE_BIT_WIDTH - 1:0] throttle_val;
wire [`PWM_VALUE_BIT_WIDTH - 1:0] yaw_val;
wire [`PWM_VALUE_BIT_WIDTH - 1:0] roll_val;
wir... | 8.90121 |
module regf_test ();
parameter AWIDTH = 4;
parameter DSIZE = 32;
reg clk;
reg reset_b;
reg halt;
reg [AWIDTH-1:0] addra;
reg a_en;
reg [AWIDTH-1:0] addrb;
reg b_en;
reg [AWIDTH-1:0] addrc;
reg [DSIZE-1:0] dc;
reg wec;
wire [DSIZE-1:0] qra;
wire a_en_out;
wire [DSIZE-1:0] qrb;
wire b_e... | 6.799711 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
... | 7.978522 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
... | 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign core... | 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
common... | 8.559964 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:... | 7.958996 |
module test_regfile_basic_magma_False_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.r... | 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
... | 7.978522 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign core... | 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
common... | 8.559964 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] const_0_4_out;
wire [3:0] reg_P4_inst0_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(I),
.I1(const_0_4_out),
.S (RESET),
.O (Mux2xBits4_inst0_O)
);
coreir_con... | 7.117303 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:0] Mu... | 7.958996 |
module test_regfile_basic_magma_False_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_addr... | 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
... | 7.978522 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
... | 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign core... | 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
common... | 8.559964 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:... | 7.958996 |
module test_regfile_basic_magma_True_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.re... | 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
... | 7.978522 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign core... | 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
common... | 8.559964 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] const_0_4_out;
wire [3:0] reg_P4_inst0_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(I),
.I1(const_0_4_out),
.S (RESET),
.O (Mux2xBits4_inst0_O)
);
coreir_con... | 7.117303 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:0] Mu... | 7.958996 |
module test_regfile_basic_magma_True_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_addr)... | 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = data[read_0_addr];
... | 7.958996 |
module test_regfile_basic_verilog_False_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
... | 6.909877 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = data[read_0_addr];
end... | 7.958996 |
module test_regfile_basic_verilog_False_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_ad... | 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = write_0_addr == rea... | 7.958996 |
module test_regfile_basic_verilog_True_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.... | 6.909877 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = write_0_addr == read_0_a... | 7.958996 |
module test_regfile_basic_verilog_True_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_add... | 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
... | 7.978522 |
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