code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
... | 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign core... | 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
common... | 8.559964 |
module test_regfile_enable_magma (
input [1:0] write_addr,
input [3:0] write_data,
input write_enable,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
... | 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data,
input write_0_en
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
if (write_0_en) begin
data[write_0_addr] <= write_0_data... | 7.958996 |
module test_regfile_enable_verilog (
input [1:0] write_addr,
input [3:0] write_data,
input write_enable,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK)... | 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
... | 7.978522 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
... | 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign core... | 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
common... | 8.559964 |
module test_regfile_two_ports_magma (
input [1:0] write_addr0,
input [3:0] write_data0,
input [1:0] write_addr1,
input [3:0] write_data1,
input [1:0] read_addr0,
output [3:0] read_data0,
input [1:0] read_addr1,
output [3:0] read_data1,
input CLK,
input ASYNCRESET
);
wire [3:0] ... | 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] read_1_addr,
output [3:0] read_1_data,
input [1:0] write_0_addr,
input [3:0] write_0_data,
input [1:0] write_1_addr,
input [3:0] write_1_data
);
reg [3:0] data[3:0];... | 7.958996 |
module test_regfile_two_ports_verilog (
input [1:0] write_addr0,
input [3:0] write_data0,
input [1:0] write_addr1,
input [3:0] write_data1,
input [1:0] read_addr0,
output [3:0] read_data0,
input [1:0] read_addr1,
output [3:0] read_data1,
input CLK,
input ASYNCRESET
);
wire [3:0... | 6.909877 |
module test_registers;
// Inputs
reg clk;
reg RegWrite;
reg [4:0] ReadReg1;
reg [4:0] ReadReg2;
reg [4:0] WriteReg;
reg [31:0] WriteRegData;
// Outputs
wire [31:0] ReadData1;
wire [31:0] ReadData2;
// Instantiate the Unit Under Test (UUT)
Registers_32 uut (
.clk(clk),
.RegWrite(Re... | 7.267008 |
module test_register_32 ();
//由于待测模块中有一个inout类型的端口, 测试比较复杂:
//用wire型的data_bus连接待测模块的这个端口
//用io的值选择data_bus在待测模块外面如何连接:
//io=1, 此时应该向寄存器写入数据, 将data_bus_in连接到data_bus, 并在always中不断改变data_bus_in的值(所以data_bus_in是reg类型)
//io=0, 此时应该从寄存器内读取数据, 则将data_bus连接到data_bus_out, 用以在波形中更好的展示输入输出结果
wire [31:0] data_bus_out;
... | 7.267008 |
module test_register_32_bits;
wire [31:0] Out;
reg [31:0] In;
reg EN, CLR, CLK; //Las entradas del módulo deben ser tipo reg
register_32_bits testReg (
Out,
In,
EN,
CLR,
CLK
);
initial begin
#1 In = 32'heeeeffff;
EN <= 0;
CLR <= 1;
end
initial begin
$mo... | 7.267008 |
module test_register_mips32 ();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
reg [(ADDR_WIDTH -1):0] Rs_addr, Rt_addr, Rd_addr;
reg [(DATA_WIDTH -1):0] Rd_in;
reg [3:0] Rd_Byte_w_en;
reg clk;
wire [(DATA_WIDTH -1):0] Rs_out, Rt_out;
register_mips32 t1 (
.Rs_addr(Rs_addr),
.Rt_addr(Rt... | 7.267008 |
module prova_registro ();
parameter N = 3;
reg [N-1:0] ingresso;
reg clk;
reg beta;
wire [N-1:0] uscita;
registro #(N) R (
uscita,
clk,
beta,
ingresso
);
initial begin
clk = 0;
end
always begin
if (clk == 0) #5 clk = 1;
else #1 clk = 0;
end
initial begin
... | 6.76205 |
module test_registru_multifunctional;
reg [3:0] intrare;
reg clk, rst;
reg [4:0] intrarile_pe_1_bite;
wire [3:0] out;
registru_multifunctional reg1 (
intrare,
clk,
rst,
intrarile_pe_1_bite[4],
intrarile_pe_1_bite[3],
intrarile_pe_1_bite[2],
intrarile_pe_1_bite[1]... | 6.964609 |
module test_replicator;
parameter WAY = 2;
parameter WIRE = 8;
reg [ WIRE-1:0] in;
wire [WAY*WIRE-1:0] out;
replicator #(
.WAY (WAY),
.WIRE(WIRE)
) replicator (
out,
in
);
initial begin
$dumpfile("signal_replicator.vcd");
$dumpvars;
$display("\t\ttime\tin,\tout... | 6.585774 |
module Test_Resp_MUX;
// Inputs
reg CLK;
reg RST;
reg [1:0] HRESP_1;
reg [1:0] HRESP_2;
reg [1:0] HRESP_3;
reg [1:0] SEL;
// Outputs
wire [1:0] HRESP;
// Instantiate the Unit Under Test (UUT)
Resp_MUX uut (
.CLK(CLK),
.RST(RST),
.HRESP(HRESP),
.HRESP_1(HRESP_1),
.H... | 7.497159 |
module test_ripple_counter ();
parameter N = 4;
//inputs for DUT
reg clk, rst;
//outputs for DUt
wire [N-1:0] up;
wire [N-1:0] down;
ripple_counter DUT (
.clk(clk),
.rst(rst),
.upcount(up),
.downcount(down)
);
initial begin
$display($time, " << Simulation Results >>");
... | 7.028022 |
module tb_ripple;
// reg clk;
// reg rst;
// wire [3:0] out;
// ripple_counter r0 ( .clk (clk),
// .rst (rst),
// .out (out));
// always #5 clk = ~clk;
// initial begin
// rst <= 0;
// clk <= 0;
// repeat (4) @ (posedge clk);
// rst <= 1;
// ... | 7.091181 |
module: road
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_road;
// Inputs
reg sensor;
reg clk;
// Outputs
wire [7:0] timer;
wire en;
wire green_main;
wire yellow_ma... | 7.046116 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module test_romb_coreir (
output [15:0] RDATAOUT,
input CLK
);
wire [15:0] SB_RAM40_4K_inst0_RDATA;
wire bit_const_0_None_out;
wire bit_const_1_None_out;
wire [10:0] const_0_11_out;
wire [15:0] const_0_16_out;
wire [10:0] const_1_11_out;
SB_RAM40_4K #(
.INIT_0(256'h00000000000000000000000000... | 7.158187 |
module test_RSA;
reg clk;
reg reset_n;
reg [63:0] Message;
wire [63:0] decrypted_message;
wire [63:0] encrypted_message;
wire [63:0] n;
wire [63:0] encrypt_key;
initial begin
clk = 1'b0;
reset_n = 1'b0;
#40;
reset_n = 1'b1;
Message = 'd2321;
#4000000;
Message = 'd8;
#... | 6.648616 |
module: RX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_rx;
// Inputs
reg clock;
reg RX_en;
reg RX;
reg reset;
// Outputs
wire data_ready;
wire [7:0] data;
wire Pb... | 7.774549 |
module Test_RX_ATRP_AR_TXA (
input clk,
output wire [11:0] TXA,
input [5:0] M,
output wire [11:0] D_RXA,
output wire [11:0] Xns,
output wire RXP,
output wire RXN,
output wire [10:0] AMP,
output wire res,
output wire [7:0] N_RXPN,
output wire en_TX,
output wire err
);
wi... | 6.861472 |
module test_rx_checksum_256;
// Parameters
parameter DATA_WIDTH = 256;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast =... | 7.463546 |
module test_rx_checksum_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0... | 7.463546 |
module test_rx_hash_256;
// Parameters
parameter DATA_WIDTH = 256;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
... | 7.574975 |
module test_rx_hash_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
... | 7.574975 |
module Test_RX_MTRP (
input clk,
output wire [11:0] MTRP,
input st,
output wire [11:0] MEM_dat,
input [5:0] M,
output wire [11:0] Xmax,
input S,
output wire [11:0] Xns,
input res,
output wire [11:0] Xmin,
output wire [11:0] REF_P,
output wire [11:0] REF_N,
output wire... | 7.315729 |
module test_tx_rx(output reg finished, output reg [15:0] errors);
/*
* primary goals:
* test transmit and receive of extended-id CAN frames on a bus.
* secondary goals:
* test basic data bus connectivity for 8051 and wishbone bus.
*/
`include "testbench/fixture.inc"
localparam baudrate_prescaler = 6'h0;
... | 7.629638 |
module test_scan_controller_tb (
input wire clk,
input wire reset,
input wire [1:0] driver_sel,
input wire [8:0] active_select,
input wire [7:0] inputs,
input wire set_clk_div,
output wire [7:0] outputs,
output wire ready,
output wire slow_clk
);
// signals for user_project_wrapp... | 7.530278 |
module: scan_new
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_scan_new;
// Inputs
reg start;
reg clk;
reg rst;
// Outputs
wire [13:0] read_select;
wire scan_start;
... | 6.832349 |
module test_sdram_read (
input iCLK,
input iRST,
input iTEST_WRITE_DONE,
input iWAIT_REQUEST,
output oRD_EN,
output [24:0] oRD_ADDR,
input [15:0] iRD_DATA,
input iRD_DATAVALID,
output [ 7:0] oDATA,
input [9:0] iSW,
input iUPDATE_FRAME,
inp... | 8.6682 |
module fake_SD_card_FAT32_reader (
input iCLK,
input iRST,
input iTRIGGER,
output [15:0] oDATA,
output oDATA_READY,
output oLAST_DATA
);
// Simulate a slow SD card module by slowing the clock
reg [2:0] clock_counter;
wire CLOCK;
always @(posedge iCLK) begin
clock_cou... | 6.824462 |
module test_sequential_regdec_left;
reg [2:0] sequenceur;
reg [7:0] bus_in;
reg clk, reset;
wire [7:0] bus_out;
supply0 masse;
sequential_regdec_left tester (
sequenceur,
bus_in,
masse,
clk,
reset,
bus_out
);
initial begin
$dumpfile("build/memory/signal/signal_te... | 7.101484 |
module test_sequential_regdec_right;
reg [2:0] sequenceur;
reg [7:0] bus_in;
reg clk, reset;
wire [7:0] bus_out;
supply0 masse;
sequential_regdec_right tester (
sequenceur,
bus_in,
masse,
clk,
reset,
bus_out
);
initial begin
$dumpfile("build/memory/signal/signal_... | 7.101484 |
module test_serializer;
reg reset = 0;
reg enable = 1;
reg [47:0] in = 48'b101011010111101011101011101010101010101001110101; // test input data
wire out; //serialized output
wire complete;
initial begin
$display("\n----------------------- Serializer test -------------------------\n");
$display("... | 6.696129 |
module _test_serial_JKlatchUP_rst;
reg [7:0] j, k;
reg clk, reset;
wire [7:0] s1, s2;
supply1 power;
integer i;
serial_JKlatchUP_rst #(
.SIZE(8)
) test_serial_JKlatchUP_rst (
j,
k,
clk,
reset,
s1,
s2
);
initial begin
reset = 1;
j = 0;
k = 0;
... | 6.521444 |
module Test_ServoController;
parameter SIGNAL_BIT_WIDTH = 15;
parameter ADDRESS_BIT_WIDTH = 2;
parameter PWM_SIGNAL_COUNT = 4;
parameter FULL_CYCLE = 32'd20_000;
reg success_flag;
reg clk, rst, cs;
reg [31:0] data_reg;
wire [31:0] data;
reg test_write_enable;
reg [ADDRESS_BIT_WIDTH-1:0] addr;
... | 7.208023 |
module test_setup ();
// clock_generator_0_wb_system_to_wb_example_0_wb_system wires:
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
// Ad-hoc wires:
wire wb_example_0_start_to_wb_example_bench_0_start;
wire wb_example_0_done_t... | 6.59498 |
module test_shifter_5 (
input clk,
input rst,
input start,
output reg [1:0] status
);
reg [3:0] M_test_counter_d, M_test_counter_q = 1'h0;
localparam IDLE_state = 2'd0;
localparam TEST_state = 2'd1;
localparam PASS_state = 2'd2;
localparam FAIL_state = 2'd3;
reg [1:0] M_state_d, M_state... | 7.186684 |
module Test_ShiftLoadRegister ();
reg i_rst, sck, load, i_we, miso;
reg [7:0] tx_packet;
wire [7:0] rx_packet;
SHIFTLOADREG #(8) buff (
.rst(i_rst),
.clk(sck),
.load(load),
.en(i_we),
.in(miso),
.D(tx_packet),
.Q(rx_packet)
);
initial begin
i_rst = 1;
sc... | 7.129724 |
module shift_register_BCD_6;
wire [3:0] BCD_5;
wire [3:0] BCD_4;
wire [3:0] BCD_3;
wire [3:0] BCD_2;
wire [3:0] BCD_1;
wire [3:0] BCD_0;
reg [3:0] d_5;
reg [3:0] d_4;
reg [3:0] d_3;
reg [3:0] d_2;
reg [3:0] d_1;
reg [3:0] d_0;
reg clk;
reg rst_n;
shift_register_BCD_6 U0 (
BCD_5,
... | 6.854847 |
module test_shuffle;
parameter WAY = 3;
parameter WIRE = 5;
reg [WIRE-1:0] e1, e2, e3;
wire [WAY*WIRE-1:0] out;
shuffle #(
.WAY (WIRE),
.WIRE(WAY)
) inst_shuffle (
out,
{e3, e2, e1}
);
initial begin
$dumpfile("signal_test_shuffle.vcd");
$dumpvars;
$display("\t\tti... | 7.116976 |
module test_signal (
input clk,
input [15:0] in,
output reg [15:0] out
);
//assign out = {{B{in[W-1]}},in[W-1-:O_W-B]};
always @(posedge clk) begin
out <= in;
end
endmodule
| 7.333985 |
module test_signal_sync;
localparam RST_DURATION = 50; //ns
localparam CLK_PERIOD = 10; //ns
localparam SIGNAL_PERIOD = 100; //ns
// Inputs
reg clk_i;
reg rst_i;
reg signal_i;
// Outputs
wire signal_o;
wire valid_o;
wire edge_o;
wire posedge_o;
wire negedge_o;
// Instantiate the Un... | 7.59309 |
module: signExt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_signExt;
// Inputs
reg [15:0] immed;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)... | 6.532526 |
module f2_test (
a,
b,
c,
d,
z
);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d) begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule
| 6.539927 |
module f9_MyCounter (
clock,
preset,
updown,
presetdata,
counter
);
input clock, preset, updown;
input [1:0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if (preset) counter <= presetdata;
else if (updown) counter <= counter + 1;
else counter <= counter - 1;
end... | 7.280849 |
module f2_test (
input [1:0] in,
output out
);
assign out = in[0] && in[1];
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
output [1:0] out
);
assign out[0] = in[0];
assign out[1] = in[1];
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
input enable,
output reg [2:0] out
);
always @(in or enable)
if (!enable) out = 3'b000;
else begin
case (in)
2'b00: out = 3'b001;
2'b01: out = 3'b010;
2'b10: out = 3'b010;
2'b11: out = 3'b100;
endcase
end
endmodule
| 6.539927 |
module f2_test (
input in,
output out
);
assign out = -in;
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
input select,
output reg out
);
always @(in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
| 6.539927 |
module f2_test (
input [2:0] in,
output out
);
assign out = !(in[0] & in[1] & in[2]);
endmodule
| 6.539927 |
module f2_test (
input [2:0] in,
output out
);
assign out = ~(in[0] | in[1] | in[2]);
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
output out
);
assign out = in[0] || in[1];
endmodule
| 6.539927 |
module f2_test (
input in,
input clk,
output reg out
);
always @(negedge clk) out <= in;
endmodule
| 6.539927 |
module f2_test (
input [31:0] IN,
input [ 5:0] SHIFT,
output [31:0] OUT
);
assign OUT = IN << SHIFT;
endmodule
| 6.539927 |
module f8_test (
input [3:0] IN,
input [2:0] SHIFT,
output [3:0] OUT
);
assign OUT = IN >> SHIFT;
endmodule
| 7.583792 |
module f9_test (
input [63:0] IN,
input [ 6:0] SHIFT,
output [63:0] OUT
);
assign OUT = IN >> SHIFT;
endmodule
| 6.818192 |
module f10_test (
input [7:0] IN,
input [3:0] SHIFT,
output [7:0] OUT
);
assign OUT = IN >> SHIFT;
endmodule
| 7.142357 |
module f2_test (
input [3:0] in,
input [1:0] select,
output reg out
);
always @(in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
| 6.539927 |
module f8_test (
input in,
output out
);
assign out = ~in;
endmodule
| 7.583792 |
module f2_test (
input in,
output out
);
assign out = ~in;
endmodule
| 6.539927 |
module f2_TECH_AND5 (
input [4:0] in,
output out
);
assign out = ∈
endmodule
| 6.9174 |
module f3_TECH_NAND2 (
input [1:0] in,
output out
);
assign out = ~(&in);
endmodule
| 6.838201 |
module f4_TECH_NAND2 (
input [1:0] in,
output out
);
assign out = ~(&in);
endmodule
| 6.824305 |
module f5_TECH_NAND2 (
input [1:0] in,
output out
);
assign out = ~(&in);
endmodule
| 7.219721 |
module f6_TECH_NOR18 (
input [17:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.590859 |
module f6_TECH_NOR2 (
input [1:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.893604 |
module f7_TECH_NOR18 (
input [17:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.779355 |
module f7_TECH_NOR4 (
input [3:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.646228 |
module f7_TECH_NOR2 (
input [1:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.872539 |
module f8_TECH_NOR18 (
input [17:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.986617 |
module f8_TECH_NOR4 (
input [3:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.631019 |
module f8_TECH_NOR2 (
input [1:0] in,
output out
);
assign out = ~(|in);
endmodule
| 7.149186 |
module f10_TECH_OR5 (
input [4:0] in,
output out
);
assign out = |in;
endmodule
| 6.634688 |
module f11_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 6.783093 |
module f12_TECH_XOR5 (
input [4:0] in,
output out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
| 6.535766 |
module f12_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.227307 |
module f13_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.239592 |
module f14_TECH_XOR5 (
input [4:0] in,
output out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
| 6.778662 |
module f14_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.179551 |
module f15_TECH_XOR5 (
input [4:0] in,
output out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
| 6.596125 |
module f15_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.163836 |
module f2_test (
clk,
cond,
data
);
input cond;
input clk;
output data;
wire synth_net;
wire synth_net_0;
wire synth_net_1;
wire synth_net_2;
wire synth_net_3;
wire synth_net_4;
wire synth_net_5;
wire synth_net_6;
wire synth_net_7;
wire synth_net_8;
wire synth_net_9;
wire sy... | 6.539927 |
module f2_test (
input [2:0] in,
output out
);
assign out = ~(in[0] ^ in[1] ^ in[2]);
endmodule
| 6.539927 |
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