code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module f2_test (
input [2:0] in,
output out
);
assign out = (in[0] ^ in[1] ^ in[2]);
endmodule
| 6.539927 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Register (
input CLK,
input I_0_X,
input [4:0] I_0_Y,
input I_1_X,
input [4:0] I_1_Y,
output O_0_X,
output [4:0] O_0_Y,
output O_1_X,
output [4:0] O_1_Y
);
wire [11:0] reg_P12_inst0_out;
wire [11:0] reg_P12_inst0_in;
assign reg_P12_inst0_in = {I_1_Y, I_1_X, I_0_Y, I_0_X}... | 7.117303 |
module SIPO5 (
input CLK,
input I_0_X,
input [4:0] I_0_Y,
input I_1_X,
input [4:0] I_1_Y,
output O_0_0_X,
output [4:0] O_0_0_Y,
output O_0_1_X,
output [4:0] O_0_1_Y,
output O_1_0_X,
output [4:0] O_1_0_Y,
output O_1_1_X,
output [4:0] O_1_1_Y,
output O_2_0_X,
ou... | 7.167706 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Register (
input I,
output O,
input CLK
);
wire [0:0] reg_P1_inst0_out;
coreir_reg #(
.clk_posedge(1'b1),
.init(1'h0),
.width(1)
) reg_P1_inst0 (
.clk(CLK),
.in (I),
.out(reg_P1_inst0_out)
);
assign O = reg_P1_inst0_out[0];
endmodule
| 7.117303 |
module SIPO5 (
input I,
output [4:0] O,
input CLK
);
wire Register_inst0_O;
wire Register_inst1_O;
wire Register_inst2_O;
wire Register_inst3_O;
wire Register_inst4_O;
Register Register_inst0 (
.I (I),
.O (Register_inst0_O),
.CLK(CLK)
);
Register Register_inst1 (
.I... | 7.167706 |
module test_sipo_basic (
input I,
output [4:0] O,
input CLK
);
wire [4:0] SIPO5_inst0_O;
SIPO5 SIPO5_inst0 (
.I (I),
.O (SIPO5_inst0_O),
.CLK(CLK)
);
assign O = SIPO5_inst0_O;
endmodule
| 7.550389 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Register (
input CLK,
input I_X,
input [4:0] I_Y,
output O_X,
output [4:0] O_Y
);
wire [5:0] reg_P6_inst0_out;
wire [5:0] reg_P6_inst0_in;
assign reg_P6_inst0_in = {I_Y, I_X};
coreir_reg #(
.clk_posedge(1'b1),
.init(6'h00),
.width(6)
) reg_P6_inst0 (
.clk(CLK... | 7.117303 |
module SIPO5 (
input CLK,
input I_X,
input [4:0] I_Y,
output O_0_X,
output [4:0] O_0_Y,
output O_1_X,
output [4:0] O_1_Y,
output O_2_X,
output [4:0] O_2_Y,
output O_3_X,
output [4:0] O_3_Y,
output O_4_X,
output [4:0] O_4_Y
);
wire Register_inst0_O_X;
wire [4:0] Re... | 7.167706 |
module: slt_operator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_slt;
// Inputs
reg signed [31:0] X;
reg signed [31:0] Y;
// Outputs
wire signed [31:0] Z;
// Instan... | 7.050528 |
module datamemory (
write,
addr,
datain,
dataout,
clk,
reset
);
input [31:0] datain;
input [15:0] addr;
input write, clk, reset;
output [31:0] dataout;
reg [31:0] mem[63:0];
assign dataout = mem[addr];
always @(posedge clk) begin
if (reset) begin
mem[0] <= 32'b0000000... | 7.533611 |
module test_spaced_2lvl_penc #(
parameter INPUT_WIDTH = 8192,
parameter PENC1_SIZE = 32,
parameter PENC2_SIZE = 32,
parameter BIN_COUNT = 8,
parameter LARGE_BLOCK = BIN_COUNT*PENC1_SIZE*PENC2_SIZE,
parameter OUTPUT_WIDTH = $clog2(LARGE_BLOCK)
) (
input wire clk,
input wire rst,
... | 7.880448 |
module test_spcm_nexys3 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// SPCM interfaces
output wire spcm_cs_n,
output wire spcm_sck,
output wire spcm_mosi,
... | 8.44029 |
module test_jbimu;
// Inputs
reg clks;
85
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire... | 6.632599 |
module test_spils;
// Inputs
reg iocs;
reg [2:0] ioaddr;
reg [15:0] din;
reg iowr;
reg sdi;
reg clk;
reg rst;
// Outputs
wire [15:0] dout;
wire sdo;
wire sck;
wire ss0n, ss1n;
// Instantiate the Unit Under Test (UUT)
spils uut (
.iocs(iocs),
.ioaddr(ioaddr),
.din(din),... | 6.866726 |
module test_spi_master (
input nrst, //Асинхронный сброс
input clk, //Тактовый генератор
//input start, //Старт цикла передачи
//output [(1<<3)-1:0]data_out,
//output cyc_num,
//output data_rdy,
//output busy,
output spi_cs, // выбор кристалла
output ... | 7.286245 |
module: spi_sniffer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_spi_sniffer2;
// Inputs
reg spi_cs;
reg spi_clk;
reg spi_si;
reg spi_so;
reg clk;
reg reset;
reg ena... | 6.527639 |
module test_float_sqrt;
reg l_r_clk;
reg l_r_rst;
wire [15:0] result;
reg [15:0] l_r_radicand;
// sqrt #(.WIDTH(11)) l_m_sqrt(
// .o_w_root(l_w_root),
// .o_w_rdy(l_w_rdy),
// .i_w_clk(l_r_clk),
// .i_w_rst(l_r_rst),
// .i_w_radicand(l_r_rad)
// );
... | 6.602395 |
module test_SRAM;
parameter CYCLE = 10; // use "CYCLE" to represent the period
parameter END_CYCLE = 20000;
parameter DRAM_DATA_WIDTH = 32;
parameter DRAM_ADDR_WIDTH = 13;
parameter SRAM_DATA_WIDTH = 4;
parameter SRAM_ADDR_WIDTH = 7;
parameter DATA_WIDTH = 8;
///// declare input(reg) and output(wire... | 7.71558 |
module test_sram_if (
input clk,
input rst,
input [`WIDTH-1:0] RAM_D_pi,
output [`WIDTH-1:0] RAM_D_po,
output RAM_D_poe,
output [`DEPTH-1:0] RAM_A,
output RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
output RAM_CE1n,
output reg correct
);
reg [`DEPTH-1:0]... | 7.093279 |
module test_sram_sword (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// SRAM interfaces
output wire sram_ce_n,
output wire sram_oe_n,
output wire sram_we_n,
... | 7.142417 |
module test_sreg8;
wire [7:0] q;
reg si, en, ck, nr;
// Instancia el shift register de 8 bits
sreg8 dut (
.Q(q),
.ShiftIn(si),
.Enable(en),
.Clock(ck),
.nReset(nr)
);
// Reset del shift register
initial begin
#10 nr = 0;
#10 nr = 1;
end
initial begin
wait ... | 7.060803 |
module test_srff ();
reg S, R, clk;
wire Q, QPrima;
srff_clk srff_1 (
S,
R,
clk,
Q,
QPrima
);
initial begin
$dumpfile("out.vcd");
$dumpvars(1, test_srff);
clk = 1;
S = 0;
R = 0;
#20 S = 1;
R = 0;
#20 S = 0;
R = 0;
#20 S = 0;
R = 1;... | 6.569613 |
module test_srff ();
reg S, R;
wire Q, QPrima;
srff srff_1 (
S,
R,
Q,
QPrima
);
initial begin
$dumpfile("out.vcd");
$dumpvars(1, test_srff);
S = 0;
R = 0;
#20 S = 1;
R = 0;
#20 S = 0;
R = 0;
#20 S = 0;
R = 1;
#20 S = 0;
R = 0;
#20 S ... | 6.569613 |
module top (
input clk,
input rst,
input [15:0] switch,
output reg [ 3:0] in, // IN4, IN3, IN2, IN1
output [ 1:0] pwm, // {left, right}
output [ 3:0] led,
output led15
);
assign led15 = switch[15];
assign led = in;
assign SPIN_... | 7.233807 |
module: step_gen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_step_gen;
// Inputs
reg clk;
reg reset;
reg signed [31:0] velocity;
wire step;
wire dir;
wire signed [31... | 7.24573 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction ha... | 6.890266 |
module test_stream_buf;
reg clk = 0;
reg rst = 0;
reg en = 0;
wire [7:0] data_in;
wire [7:0] data_out;
wire valid_in;
wire valid_out;
reg ready_in = 0;
wire ready_out;
always #5 clk = ~clk;
always @(posedge clk) begin
if (ready_in && valid_out) begin
$display("slave received %d", data... | 6.592789 |
module test_stub_scan ( /*AUTOARG*/
// Outputs
mux_drive_disable,
mem_write_disable,
sehold,
se,
testmode_l,
mem_bypass,
so_0,
so_1,
so_2,
// Inputs
ctu_tst_pre_grst_l,
arst_l,
global_shift_enable,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_macro... | 7.575823 |
module test_sub16 (
input [15:0] a,
input [15:0] b,
output [15:0] out
);
assign out = a - b;
endmodule
| 6.564557 |
module test_subtracter;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg c_in;
// Outputs
wire [31:0] sum;
wire c_out;
// Instantiate the Unit Under Test (UUT)
Sub_32 uut (
.sum(sum),
.c_out(c_out),
.a(a),
.b(b),
.c_in(c_in)
);
initial begin
// Initialize Inputs
... | 6.55589 |
module TOP;
//ALU inputs
reg a, b, c;
wire sum1;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 0;
b = 0;
c = 0;
#`cycle //1
if(sum1 != a^b^c)
begin
error_free... | 7.259416 |
module: super
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_super;
// Inputs
reg clk;
reg btnd;
reg [1:0] sw;
// Outputs
wire hsync;
wire vsync;
wire [7:0]rgb;
... | 7.281223 |
module test_syncfifo;
localparam ADDR_WIDTH = 3;
localparam DATA_WIDTH = 8;
syncfifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) dut (
.i_clk(clk),
.i_rst(rst),
.i_data(wr_data),
.o_data(rd_data),
.i_wr(wr),
.i_rd(rd),
.o_count(count),
.o_e... | 7.212939 |
module test_SyncGen;
reg clk, rst;
wire [9:0] hcount, vcount;
wire hsync, vsync, hblank, vblank;
SyncGen sync (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
rst = 1;
#33_444_000 $stop;
end
always begin
#20 clk = ~clk;
end
endmodule
| 6.770419 |
module test_synchronous_fifo ();
reg i_clk;
reg i_rst_n;
reg i_wr_en;
reg i_rd_en;
reg [47:0] i_data;
wire o_fifo_empty;
wire o_fifo_full;
wire o_fifo_almst_full;
wire [47:0] o_fifo_data;
//instantiate the design module
Synchronous_FIFO DUT (
i_clk, // single clock domain
i_rst_n, ... | 6.562984 |
module test_syndet;
// Inputs
reg [5:0] din;
reg iv;
reg [5:0] length;
reg clk;
reg rst;
// Outputs
wire [13:0] dout;
wire ov;
// Instantiate the Unit Under Test (UUT)
syndet uut (
.din(din),
.iv(iv),
.dout(dout),
.ov(ov),
.length(length),
.clk(clk),
.r... | 6.719478 |
module: systol_new1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_systol_new;
// Inputs
reg start;
reg [7:0] read_data;
reg clk;
reg rst;
// Outputs
wire [13:0] read_... | 6.510316 |
module test_s_core;
reg clk;
reg rst_n;
//reg[31:0] i_pc_instr_start_addr;
//reg[31:0] inst_mem_addr;
//reg[31:0] inst_mem_data;
//reg[4:0] load_reg_addr;
//reg[31:0] load_reg_data;
//reg setup;
wire [31:0] o_pc;
wire [31:0] o_inst_data;
wire [31:0] o_rs1_data;
wire [31:0] o_rs2_data;
wire [3... | 6.729422 |
module test_table_lookup;
// Inputs
reg clk;
reg [31:0] state;
// Outputs
wire [31:0] p0;
wire [31:0] p1;
wire [31:0] p2;
wire [31:0] p3;
// Instantiate the Unit Under Test (UUT)
table_lookup uut (
.clk(clk),
.state(state),
.p0(p0),
.p1(p1),
.p2(p2),
.p3(p3)
... | 6.599303 |
module test_target ();
reg [35:0] keys_code = 0;
wire [35:0] target_key;
target TGT (
keys_code,
target_key
);
initial begin
#5 keys_code = 36'b000000000000000000000000000000000001;
#5 keys_code = 36'b000000000000000000000000000000000000;
#5 keys_code = 36'b1000000000000000000000000... | 6.755529 |
module test_tb ();
initial begin
$dumpfile("test_tb.vcd");
$dumpvars(0, my_cpu, d_ram_and_io_inst);
#1000 $finish;
end
reg clk = 0;
always begin
#1 clk <= ~clk;
end
//***************************************************************
// Instantiate CPU
//*******************************... | 7.972333 |
module test_tdma_scheduler;
// Parameters
parameter INDEX_WIDTH = 8;
parameter SCHEDULE_START_S = 48'h0;
parameter SCHEDULE_START_NS = 30'h0;
parameter SCHEDULE_PERIOD_S = 48'd0;
parameter SCHEDULE_PERIOD_NS = 30'd1000000;
parameter TIMESLOT_PERIOD_S = 48'd0;
parameter TIMESLOT_PERIOD_NS = 30'd100000;
... | 6.556205 |
module: tft_address_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_tft_addr_gen;
// Inputs
reg [8:0] x;
reg [8:0] y;
wire [17:0] addr;
// Instantiate the Uni... | 6.954032 |
module test_tiledBcdCounter ();
reg clock, up, down, set9, set0;
wire [3:0] ups, down;
wire [15:0] num;
assign ups = {0, 0, 0, up};
assign downs = {0, 0, 0, down};
tiledBcdCounter #(
.DIGITS(4)
) counter (
num,
cout,
bout,
up,
down,
set9,
set0,
clo... | 6.833341 |
module: token_production
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_token_production;
// Inputs
reg [2:0] park_number;
reg [2:0] pattern;
// Outputs
wire [2:0] token... | 6.63451 |
module: TOP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module text_TOP_bh;
// Inputs
reg clk;
reg reset;
// Instantiate the Unit Under Test (UUT)
TOP uut (
.clk(clk),.reset(re... | 7.274763 |
module: top_level
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_top_koli_jani;
// Inputs
reg clk;
reg rst;
// Outputs
wire [15:0] mixed_signal;
wire [15:0] sampled_s... | 7.56918 |
module test_touch;
// Inputs
reg cclk;
reg rstb;
wire touch_busy;
wire data_in;
// Outputs
wire touch_clk;
wire touch_csb;
wire data_out;
wire [11:0] x, y, z;
// Instantiate the Unit Under Test (UUT)
touchpad_controller uut (
.cclk(cclk),
.rstb(rstb),
.touch_busy(touch_bus... | 6.645161 |
module: transmitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_transmiiterandreceiver;
// Inputs
reg [7:0] data;
reg start;
reg clk;
// Outputs
wire Tx;
wire Rx;
... | 6.812619 |
module test_transrf_b4r5g3;
parameter period = 5;
reg clk_w, clk_r, rst_n, w_en, r_en;
reg [ 3:0] w_data;
wire [19:0] r_data;
wire rf_full, rf_empty;
transrf_b4r5g3 DUT (
.clk_w(clk_w),
.clk_r(clk_r),
.rst_n(rst_n),
.w_en(w_en),
.w_data(w_data),
.r_en(r_en),
.r_... | 6.710434 |
module test_trig_gen (
input gclk_40m,
input trigger_select,
input htrig,
input strig_cmd,
input [3:0] strig_config,
input sptrig_en,
input [15:0] sptrig_period,
input [15:0] test_l0_latency,
input [15:0] test_l1_latency,
input [15:0] test_l2a_latency,
output reg test_l0 = ... | 7.485104 |
module test_tristate_buffer;
reg in;
reg en;
wire out_h;
wire out_l;
tsb_h #(1) ts_h(in, out_h, en);
tsb_l #(1) ts_l(in, out_l, en);
localparam N = 4;
reg [1:N] test_in = 8'b0011;
reg [1:N] test_en = 8'b0101;
reg [1:N] exp_out_h = 8'bz0z1;
reg [1:N] exp_out_l = 8'b0z1z;
... | 6.877788 |
module: TX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_tx;
// Inputs
reg clock;
reg tx_en;
reg [7:0] data_in;
reg reset;
// Outputs
wire tx;
// Instantiate the Un... | 8.797909 |
module test_tx_checksum_256;
// Parameters
parameter DATA_WIDTH = 256;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 0;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 0;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USE_INIT_VALUE = 1;
... | 8.158623 |
module test_tx_checksum_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 0;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 0;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USE_INIT_VALUE = 1;
pa... | 8.158623 |
module test_tx_mac #(
parameter mac_aw = 10, // 16-bit words
parameter big_endian = 0
) (
input clk,
// There is an implied DPRAM _not_ included in this module.
// These ports access its read port, with assumed 1-cycle latency
// The packet length is stored as the first word of a buffer.
//... | 8.703978 |
module test_tx_tb;
parameter mac_aw = 8;
reg clk;
integer cc;
reg [15:0] host_mem[0:(1<<mac_aw)-1];
integer out_file;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("test_tx.vcd");
$dumpvars(5, test_tx_tb);
end
$readmemh("host_mem", host_mem);
out_file = $fopen("test_t... | 7.634402 |
module test_uart;
// Testbench uses a 48 MHz clock
// Want to interface to 115200 baud UART
// 10000000 / 115200 = 87 Clocks Per Bit.
parameter c_CLOCK_MHZ = 48;
parameter c_UART_SPEED = 115200;
parameter c_CLOCK_PERIOD_NS = 1000 / c_CLOCK_MHZ;
parameter c_CLKS_PER_BIT = c_CLOCK_MHZ * 1000000 / c_UART_S... | 7.673351 |
module test_uart_rx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg m_axis_tready = 0;
reg rxd = 1;
reg [15:0] prescale = 0;
// Outputs
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire busy;
wire overrun_error;
wire frame_error;
initial begin
// myhdl integrati... | 7.014426 |
module test_uart_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 8'd0;
reg s_axis_tvalid = 1'b0;
reg [15:0] prescale = 0;
// Outputs
wire s_axis_tready;
wire txd;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current... | 7.694888 |
module test_uart_tx_buffer ();
reg clk = 0;
always #1 clk = ~clk;
reg ena, sent;
initial begin
ena = 0;
end
always #2 ena = ~ena;
reg [15:0] data_transmit = {8'd10, 8'd97};
parameter LEN = 2;
reg last_ena;
reg last_tx_sent;
reg tx_ena;
reg sending = 0;
reg [7:0] count;
reg [(LEN+1)... | 6.689567 |
module test_ULA;
reg [1:0] Operacao;
reg signed [7:0] in1;
reg signed [7:0] in2;
wire saida_comp;
wire signed [7:0] saida;
initial begin
#1 $display("Soma sem sinal");
in1 = 0;
in2 = 1;
Operacao = 0;
#1 $display("Soma com sinal");
in1 = -1;
Operacao = 1;
#1 $display("Multip... | 6.912582 |
module (TEST)
module Unit_test (clk, updown, reset, teller,
full, empty, alarm, display1, display2, display3, pcount, tcount);
// We have five inputs to get from the user
input wire clk, reset, updown;
input [2:0] teller;
// We give four outputs
// Two for empty or flag
// ,one for showing the number of people in qu... | 7.772727 |
module unit_test_t ();
reg clk, reset, updown;
reg [2:0] teller;
wire full, empty, alarm;
wire [3:0] pcount;
wire [1:0] tcount;
wire [6:0] display1, display2, display3;
initial begin
clk = 0;
reset = 1;
// Up
#100;
reset = 0;
updown = 1;
teller[2] = 0;
teller[1] = 0;
... | 6.897001 |
module contains the following parts:
*
* 1. A routine which provides procedural stimulus to the inputs of the
* controller design.
*
* 2. A routine to generate a test vector file by recording the stimulus.
*
* 3. A routine to generate an expected results file based on the outputs
* of the controller desig... | 7.358377 |
module vga_bounceball_test;
// input
reg clk;
reg nreset;
// output
wire vga_hs;
wire vga_vs;
wire [2:0] red;
wire [2:0] green;
wire [2:0] blue;
reg xpos_ball;
reg ypos_ball;
// Instantiate the Unit Under Test (UUT)
vga_bounceball uut (
.clk(clk),
.nreset(nreset),
.vga_h... | 6.522684 |
module Test_VGA_Keyboard;
reg clk, rst;
reg ps2_clk, ps2_data;
wire ready, hsync, vsync;
wire [3:0] r, g, b;
reg [63:0] counter;
Keyboard_DEMO demo (
.clk(clk),
.rst(rst),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.ready(ready),
.hsync(hsync),
.vsync(vsync),
.... | 6.863595 |
module test_vga_nexys3 (
input wire clk,
input wire clk_base,
input wire clk_bus,
input wire rst,
input wire cs,
input wire [7:0] mode,
output wire [31:0] data,
output wire [7:0] state,
// VGA interfaces
output wire vga_h_sync,
output wire vga_v_sync,
output wire [2:0] vg... | 7.789579 |
module test_vga_sword (
input wire clk,
input wire clk_base,
input wire clk_bus,
input wire rst,
input wire cs,
input wire [7:0] mode,
output wire [31:0] data,
output wire [7:0] state,
// VGA interfaces
output wire vga_h_sync,
output wire vga_v_sync,
output wire [3:0] vga... | 6.918621 |
module test_wave (
input sclk,
output signed [13:0] data_out
);
//--------------------------------------------------------//
parameter Freq_I = 32'd4294967; //frequence_I = 500k
parameter Freq_Q = 32'd12884902; //frequence_Q = 1.5M
parameter cnt_width = 8'd32;
//-------------------------------------... | 6.672295 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [9:0] test_vector_idx = 0;
reg [7:0] test_vector[0:1023];
integer i;
initial begin
i = 0;
// Zero bytes
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_v... | 6.890266 |
module test_wbcon;
localparam WB_ADDR_WIDTH = 8;
localparam COUNT_WIDTH = 8;
wb_mem_dly #(
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.STALL_WS(0),
.ACK_WS(0)
) mem (
.i_clk(clk),
.i_rst(rst),
// wb
.i_wb_cyc(wb_cyc),
.i_wb_stb(wb_stb),
.o_wb_stall(wb_stall),
.o... | 6.98367 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction ha... | 6.890266 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [9:0] test_vector_idx = 0;
reg [7:0] test_vector[0:1023];
integer i;
initial begin
i = 0;
// Zero bytes
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_v... | 6.890266 |
module test_wbcon_tx;
reg clk = 0;
reg rst = 0;
reg mreq_valid = 0;
wire mreq_ready;
wire exec_mreq_valid;
wire exec_mreq_ready;
reg exec_mreq_done = 0;
//
wire [7:0] tx_data;
wire tx_valid;
reg tx_ready = 1;
//
reg [7:0] body_data = 8'hAA;
reg body_valid = 1;
wire body_ready;
wbcon_t... | 6.536109 |
module test_wb_adapter_16_32;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 16;
parameter WBM_SELECT_WIDTH = 2;
parameter WBS_DATA_WIDTH = 32;
parameter WBS_SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0... | 8.256746 |
module test_wb_adapter_32_16;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 32;
parameter WBM_SELECT_WIDTH = 4;
parameter WBS_DATA_WIDTH = 16;
parameter WBS_SELECT_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0... | 8.256746 |
module test_wb_adapter_32_8;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 32;
parameter WBM_SELECT_WIDTH = 4;
parameter WBS_DATA_WIDTH = 8;
parameter WBS_SELECT_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
... | 8.256746 |
module test_wb_adapter_8_32;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 8;
parameter WBM_SELECT_WIDTH = 1;
parameter WBS_DATA_WIDTH = 32;
parameter WBS_SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
... | 8.256746 |
module test_wb_arbiter_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = (DATA_WIDTH / 8);
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] ... | 7.035949 |
module test_wb_async_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg wbm_clk = 0;
reg wbm_rst = 0;
reg wbs_clk = 0;
reg wbs_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_... | 7.700978 |
module test_wb_dp_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg a_clk = 0;
reg a_rst = 0;
reg b_clk = 0;
reg b_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] a_adr_i = 0;
reg [DATA_WIDTH-1:0] a_dat_i = 0;
reg a_... | 7.622853 |
module test_wb_drp;
// Parameters
parameter ADDR_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wb_adr_i = 0;
reg [15:0] wb_dat_i = 0;
reg wb_we_i = 0;
reg wb_stb_i = 0;
reg wb_cyc_i = 0;
reg [15:0] drp_di = 0;
reg drp_rdy = 0;
// Outputs... | 6.871205 |
module test_wb_mux_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0... | 6.699358 |
module test_wb_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
... | 7.612469 |
module test_wb_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] ... | 7.04094 |
module KGP_MiniRISC (
input clk,
rst,
output [3:0] opcode,
output [10:0] funct,
output [4:0] shamt,
output [31:0] pc_in,
output [31:0] reg_show1,
reg_show2,
reg_show3,
reg_show4,
reg_show5,
output [31:0] reg_show6,
reg_show7,
reg_show8,
reg_show9,
reg_show... | 6.590719 |
module used in used in GZIP.
*/
`timescale 1 ns / 10 ps
module test_word_merge;
integer i;
// Declare input/output variables
reg clk;
reg rst_n;
reg in_valid =0;
reg in_last =0;
reg [5:0] in_size=0;
reg [31:0] in_data=0;
reg [31:0] total_value = 0;
wire out_valid;
... | 7.760949 |
module used in used in GZIP.
*/
`timescale 1 ns / 10 ps
module test_word_merge64();
integer i;
// Declare input/output variables
reg clk;
reg rst_n;
reg in_valid =0;
reg in_last =0;
reg [6:0] in_size=0;
reg [63:0] in_data=0;
reg [63:0] total_value = 0;
wire out_valid;
... | 7.760949 |
module : i_memory_interface
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Soft... | 8.392825 |
module Write_MUX (
CLK,
RST,
HWDATA,
HWDATA_1,
HWDATA_2,
SEL
);
input [1:0] SEL;
input RST, CLK;
input [31:0] HWDATA_1, HWDATA_2;
output reg [31:0] HWDATA;
always @(posedge CLK or posedge RST) begin
if(SEL == 2'b01 && RST != 1) // Master 1 selected
begin
HWDATA = HWDATA_... | 7.749282 |
module: test_with_alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module KGP_MiniRISC_tb;
// Inputs
reg clk;
reg rst;
integer i;
// Outputs
wire [3:0] opcode;
wire [10:0] funct... | 6.769852 |
module test_xfcp_mod_axil_32;
// Parameters
parameter XFCP_ID_TYPE = 16'h0001;
parameter XFCP_ID_STR = "AXIL Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter COUNT_SIZE = 16;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter STRB_WIDTH = (DATA_WIDTH / 8);
... | 6.880446 |
module test_xfcp_mod_i2c_master;
// Parameters
parameter XFCP_ID_TYPE = 16'h2C00;
parameter XFCP_ID_STR = "I2C Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter DEFAULT_PRESCALE = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in... | 6.880446 |
module test_xfcp_mod_wb_32;
// Parameters
parameter XFCP_ID_TYPE = 16'h0001;
parameter XFCP_ID_STR = "WB Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter COUNT_SIZE = 16;
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 32;
parameter WB_SELECT_WIDTH = (WB_DATA_WIDT... | 6.880446 |
module test_xfcp_switch_4;
// Parameters
parameter PORTS = 4;
parameter XFCP_ID_TYPE = 16'h0100;
parameter XFCP_ID_STR = "XFCP Switch";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
re... | 6.623789 |
module test_xgmii #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8)
) (
input wire clk,
input wire rst,
inout wire [DATA_WIDTH-1:0] xgmii_d,
inout wire [CTRL_WIDTH-1:0] xgmii_c,
inout wire xgmii_clk_en
);
endmodule
| 6.504648 |
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