code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_xgmii_baser_dec_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] encoded_rx_data = 0;
reg [HDR_WIDTH-1:0] encoded_rx_hdr = 0;
// Output... | 7.176683 |
module test_xgmii_baser_enc_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] xgmii_txd = 0;
reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
// Outputs
wire [... | 7.176683 |
module test_xor ();
reg a, b;
wire out;
xor_gate dut (
out,
a,
b
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test_xor);
a = 0;
b = 0;
#10;
a = 1;
b = 0;
#10;
a = 0;
b = 1;
#10;
a = 1;
b = 1;
#10;
end
endmodule
| 6.507287 |
module test_yxt_2497_7 ();
reg clk_in;
reg rst;
reg auto;
reg [13:0] Key;
wire clk_out;
wire beep;
wire [ 7:0] codeout;
wire [ 6:0] low;
wire [ 6:0] middle;
yxt_2497_3 play (
.clk_in(clk_in),
.rst(rst),
.auto(auto),
.Key(Key),
.... | 7.188798 |
module LFSR (
out,
clk,
rst
);
output reg [4:0] out;
input clk, rst;
wire feedback;
assign feedback = ~(out[2] ^ out[4]);
always @(posedge clk, posedge rst) begin
if (rst) out = 5'b0;
else out = {out[3:0], feedback};
end
endmodule
| 7.001839 |
module test_zet;
// Net declarations
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
wire inta;
wire [19:0] pc;
reg clk;
reg rst... | 7.145266 |
module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Tes_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT... | 7.550078 |
module divfreq (
input CLK,
output reg CLK_div,
output reg CLK_Hz10
); //時脈
reg [30:0] Hz10_Count;
reg [19:0] CLK_Count;
always @(posedge CLK) begin
if (CLK_Count > 10000) begin
CLK_Count <= 0;
CLK_div <= ~CLK_div;
end else CLK_Count <= CLK_Count + 1'b1;
if (Hz10_Count > 24... | 6.846501 |
module JIZLOTS_sel(input[2:0] type, input[1:0] rot, output reg[0:15] block);
wire[0:15] block_t, block_z, block_s, block_j, block_l, block_o, block_i;
T_sel t(rot, block_t);
Z_sel z(rot, block_z);
S_sel s(rot, block_s);
J_sel j(rot, block_j);
L_sel l(rot, block_l);
O_sel o(rot, block_o);
I_sel i(rot, block_i);
alway... | 6.673376 |
module T_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] t0 = 16'b1110010000000000;
wire [0:15] t1 = 16'b0010011000100000;
wire [0:15] t2 = 16'b0000010011100000;
wire [0:15] t3 = 16'b1000110010000000;
always @* begin
case (rot)
0: block = t0;
1: block = t1;
2: blo... | 7.316494 |
module Z_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] z0 = 16'b1100011000000000;
wire [0:15] z1 = 16'b0010011001000000;
wire [0:15] z2 = 16'b0000110001100000;
wire [0:15] z3 = 16'b0100110010000000;
always @* begin
case (rot)
0: block = z0;
1: block = z1;
2: blo... | 7.190765 |
module S_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] s0 = 16'b0110110000000000;
wire [0:15] s1 = 16'b0100011000100000;
wire [0:15] s2 = 16'b0000011011000000;
wire [0:15] s3 = 16'b1000110001000000;
always @* begin
case (rot)
0: block = s0;
1: block = s1;
2: blo... | 6.90364 |
module J_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] j0 = 16'b0100010011000000;
wire [0:15] j1 = 16'b1000111000000000;
wire [0:15] j2 = 16'b0110010001000000;
wire [0:15] j3 = 16'b0000111000100000;
always @* begin
case (rot)
0: block = j0;
1: block = j1;
2: blo... | 7.501091 |
module L_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] l0 = 16'b0100010011000000;
wire [0:15] l1 = 16'b0000111010000000;
wire [0:15] l2 = 16'b1100010001000000;
wire [0:15] l3 = 16'b0010111000000000;
always @* begin
case (rot)
0: block = l0;
1: block = l1;
2: blo... | 7.330394 |
module O_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] o0 = 16'b1100110000000000;
always @* begin
case (rot)
default: block = o0;
endcase
end
endmodule
| 7.929439 |
module I_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] i0 = 16'b1000100010001000;
wire [0:15] i1 = 16'b0000000011110000;
always @* begin
case (rot)
0: block = i0;
1: block = i1;
2: block = i0;
3: block = i1;
default: block = i0;
endcase
end
endmod... | 6.906223 |
module Tetris_tb ();
reg clk, rstn, ps2clk, ps2data;
wire pwm;
Tetris Tetris (
.clk(clk),
.rstn(rstn),
.pwm(pwm),
.PS2_CLK(ps2clk),
.PS2_DATA(ps2data)
);
initial begin
clk = 0;
rstn = 1;
ps2clk <= 1;
ps2data <= 1;
#0.1 rstn = 0;
#0.1 rstn = 1;
#1 #0.... | 7.263495 |
module tetris_tester (
input CLK,
input [4:0] BTN, // CENTER, DOWN, RIGHT, LEFT, UP
input [15:0] SW, // LEFT : RIGHT
input UART_RX, // See Ref. Page 7
output UART_TX, // See Ref. Page 7
output [7:0] SSEG_CA, // See Ref. Page 15
output [3:0] SSEG_AN, // See Ref. Page 15
output [15:0... | 8.213129 |
module sync_gen (
input clk,
output h_sync,
output v_sync,
output blank,
input gfx_clk,
output [9:0] x,
output [9:0] y,
input rst
);
reg [9:0] hcount, vcount;
assign h_sync = hcount < 96 ? 1'b0 : 1'b1;
assign v_sync = vcount < 2 ? 1'b0 : 1'b1;
assign blank = h_sync & v_sync;
... | 7.042061 |
module textbox (
input wire pclk,
input wire rst,
input wire hblnk_in,
input wire [10:0] hcount_in,
input wire hsync_in,
input wire [3:0] level,
input wire [10:0] vcount_in,
input wire vsync_in,
input wire vblnk_in,
input wire [3:0] dead_count_1,
input wire [3:0] dead_cou... | 8.168478 |
module textdrv (
input clk_i,
input rst_i,
input vga_clock,
input [31:0] cursorpos,
input [3:0] cursormode,
input [15:0] x,
input [15:0] y,
output [7:0] r,
output [7:0] g,
output [7:0] b,
output cyc_o,
output [31:0] adr_o,
input [31:0] dat_i,
input ack_i
);
wir... | 8.098516 |
module: SingleCycleCPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TextFile;
// Instantiate the Unit Under Test (UUT)
SingleCycleCPU uut (clk, Extsel, PCWre, InsMemRW, RegOut... | 6.674631 |
module textgen_8x8 (
input clk_i,
input [7:0] chr_ord_i, // character number (8bit, 0~256)
input [2:0] cell_col_i, // cell column (0~7)
input [2:0] cell_lin_i, // cell line (0~7)
output px_o // pixel is on or off
);
wire vcc = 1'b1;
wire gnd = 1'b0;
reg [7:0] chrl... | 7.49105 |
module textlcd_tb;
//input
reg RESETN, CLK;
//output
wire LCD_RW, LCD_RS, LCD_E;
wire [7:0] LCD_DATA;
textlcdforSLOT U1 (
RESETN,
CLK,
LCD_E,
LCD_RS,
LCD_RW,
LCD_DATA
);
initial begin
RESETN = 1;
CLK = 0;
#5 RESETN = 0;
end
endmodule
| 6.589122 |
module textlinebuf (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`i... | 6.573833 |
module TextMemory #( //width of data bus
parameter TEXT_ADDR_WIDTH = 'h800,
parameter ADDR_WIDTH = 12 //width of addresses buses
) (
//input CLK,
input [(ADDR_WIDTH-1):0] R_ADDR, //address for write/read operation
output reg [ (32-1):0] DOUT //read data
);
//! Inter... | 8.477673 |
module textmode(clk, ce, vsync, hsync, pixel, background, address, data, wren, q,
// debug stuff
linebegin, textaddr, loadchar, tileaddr, tile_y, tileline, pixelreg);
input clk;
input ce;
input vsync;
input hsync;
output pixel = background & pixxel;
output background;
input [`LOG2TXT-... | 6.532894 |
module texto (
index,
ascii_code
);
input [3:0] index;
output reg [7:0] ascii_code;
always @(*) begin
ascii_code = 8'h00;
case (index)
4'h0: ascii_code = 8'h41; // A
4'h1: ascii_code = 8'h6c; // l
4'h2: ascii_code = 8'h65; // e
4'h3: ascii_code = 8'h78; // x
4'h4... | 7.107614 |
module Texto_tb(
);
<<<<<<< HEAD
reg [9:0] Qh_tb;
reg [9:0] Qv_tb;
wire BIT_FUENTEtb;
=======
reg [9:0] Qh_tb;// = 10'b0000000000;
reg [9:0] Qv_tb;// = 9'b000000000;
wire BIT_FUENTEtb,ANDD1,ANDD2,ORD,ANDJ,ANDV;
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
reg reloj_tb;
reg ... | 7.302459 |
module TextPC4 (
clk,
clrn,
wpcir,
pc,
pc4
);
input clk, clrn, wpcir;
output [31:0] pc;
output [31:0] pc4;
//reg [31:0] pc4;
pipepc pcreg (
pc4,
wpcir,
clk,
clrn,
pc
);
cla32 pc_plus4 (
pc,
32'h4,
1'b0,
pc4
);
endmodule
| 7.117047 |
module TextRam (
aclr_a,
aclr_b,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input aclr_a;
input aclr_b;
input [5:0] address_a;
input [5:0] address_b;
input clock_a;
input clock_b;
input [2559:0] data_a;
input [2559:0] data_b;
input wren_a;
inp... | 6.749353 |
module textRenderer (
output [11:0] rgb,
input [31:0] x,
input [31:0] y,
input clk
);
wire member1, member2, member3, member4, member5, anykey;
Pixel_On_Text2 #(
.displayText("6031033521 Nisaruj Rattanaaram")
) t1 (
clk,
200,
100,
x,
y,
member1
);
Pix... | 6.732481 |
module texture_memory (
input clk,
wen,
ren,
input [11:0] waddr,
raddr,
input [2:0] wdata,
output reg [2:0] rdata
);
reg [2:0] mem [0:4095]; // enough memory for 64 8x8 texture tiles @ 3bpp // uses 4/32 BRAMS of Ice40
always @(posedge clk) begin
if (ren) rdata <= mem[raddr];
if... | 6.850403 |
module texture_rom (
input clk,
input [5:0] texture_idx,
input [2:0] y_idx,
input [2:0] x_idx,
output reg [2:0] val
);
reg [2:0] TEXTURE_ROM[0:4095]; /* 16 x (32 x 32 x 4bpp) textures */
initial $readmemh("textures.mem", TEXTURE_ROM);
// the indexing below is a little bit complicated, but i... | 8.165941 |
module text_display
#(parameter COLOR=24'hFF_FF_FF, WIDTH=31, HEIGHT=31, READ_WIDTH=31)
(input wire [10:0] x, hcount,input wire [9:0] y, vcount,
input wire [5:0] alphabet_num,input wire clk, output reg [23:0] pixel);
// alphabet_num is a number in [1,26] representing A-Z, [27,52] a-z,... | 6.604801 |
module text_editor_keyboard_controller (
input sys_Clk,
input PS2_Clk,
input Reset,
inout PS2KeyboardData,
inout PS2KeyboardClk,
output reg [7:0] KeyData,
output reg KeyReleased
);
/************************************************************************
* LO... | 8.826465 |
module text_editor_RAM (
input clk,
input Reset,
input write,
input [ADDR_WIDTH-1:0] write_address,
input [DATA_WIDTH-1:0] write_data,
input [ADDR_WIDTH-1:0] read_address,
output [DATA_WIDTH-1:0] read_data
);
parameter DATA_WIDTH = 8;
... | 6.821493 |
module text_font (
input wire clk,
input wire [2:0] sw,
input wire [9:0] pix_x,
pix_y,
output wire text_on,
output reg [7:0] text_rgb
);
// declaracion de seales
reg [ 7:0] color_word;
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_l;
reg [3:0] row_addr;
wire [3:0] row_addr_l... | 8.957293 |
module text_graph (
input wire clk,
input wire [3:0] left_high,
left_low,
input wire [3:0] right_high,
right_low,
input wire [9:0] pix_x,
pix_y,
output wire text_on,
output reg [2:0] text_rgb
);
wire [10:0] rom_add;
wire [3:0] row_add;
wire [2:0] bit_add;
wire [7:0] temp_data... | 7.513612 |
module text_manager (
input CLK,
input advanced_sw,
input [3:0] MENU_R,
input [3:0] MENU_G,
input [3:0] MENU_B,
input [11:0] VGA_HORZ_COORD,
input [11:0] VGA_VERT_COORD,
input [3:0] MENU_OPTIONS,
output reg [3:0] TEXTR,
output reg [3:0] TEXTG,
output reg [3:0] TEXTB
);
wir... | 6.762367 |
module text_screen_top (
input wire clk,
rst,
input wire [7:0] vga_cmd_word,
input wire [6:0] vga_char_code,
input wire [6:0] vga_cursor_x_pos,
input wire [4:0] vga_cursor_y_pos,
output wire vga_ctrl_idle,
output wire hsync,
vsync,
output wire [11:0] rgb
);
endmodule
| 6.793237 |
module: text
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module text_tb;
// Inputs
// Outputs
wire [3:0] c;
// Instantiate the Unit Under Test (UUT)
text uut (
.c(c)
);
... | 6.951458 |
module ata (
input CLK,
input AS,
input RW,
input [23:0] A,
input WAIT,
output [1:0] IDECS,
output IOR,
output IOW,
output DTACK,
output ACCESS
);
assign ACCESS = 1'b1;
assign DTACK = 1'b1;
assign IOR = 1'b1;
assign I... | 6.974379 |
module tf530_ram (
input CLKCPU,
input RESET,
input A0,
input A1,
input [8:2] AB,
input [23:12] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
input IDEWAIT,
output INT2,
input AS20,
input RW20,
input DS20,
// cache and burst control
input CBREQ,... | 6.876238 |
module tflip (
input t,
qp,
clk,
reset,
output reg qn
);
always @(posedge clk) begin
if (reset == 1'b1) qn = 1'b0;
else qn = t ^ qp;
end
endmodule
| 6.815993 |
module TFF_AsyncClear (
output reg Q,
input T,
input clr,
input clk
);
initial begin
Q = 0;
end
always @(posedge clk, posedge clr) begin
if (clr) Q <= 0;
else Q <= Q ^ T;
end
endmodule
| 6.931557 |
module tff_async_reset (
data, // Data Input
clk, // Clock Input
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code... | 6.8872 |
module tff_async_rst_tb ();
// Signal Decleration
reg clk_i;
reg rst_i;
reg t_i;
wire q_o;
wire q_n_o;
// Instantiation
tff_async_rst dut (
.clk_i(clk_i),
.rst_i(rst_i),
.t_i (t_i),
.q_o (q_o),
.q_n_o(q_n_o)
);
// Clock generation
initial begin
clk_i = 1'b... | 7.313492 |
module to connect to the FPGA
module tff_final(SW, KEY, HEX0, HEX1);
input [1:0] SW;
input [0:0] KEY;
output [6:0] HEX0;
output [6:0] HEX1;
wire clk = ~KEY[0];
wire enable = SW[1];
wire clear_b = SW[0];
wire [7:0] Q;
t_flipflop t0(.clk(clk), .enable(enable), .clear_b(clear_b), .Q(Q));
seven_seg h0(.in(Q[3:... | 6.782222 |
module flipflop (
clk,
enable,
clear_b,
Q
);
input clk;
input enable;
input clear_b;
output reg Q;
always @(posedge clk, negedge clear_b) begin
if (clear_b == 1'b0) Q <= 1'b0;
else Q <= Q ^ enable;
end
endmodule
| 6.626138 |
module tff_p (
output reg q,
qbar,
input clk,
rst_n,
t
);
always @(posedge clk) begin
if (~rst_n) {q, qbar} <= 2'b01;
else if (t) {q, qbar} <= {qbar, q};
end
endmodule
| 8.046041 |
module TFF_SyncClear (
output reg Q,
input T,
input clr,
input clk
);
initial begin
Q = 0;
end
always @(posedge clk) begin
if (clr) Q <= 0;
else Q <= Q ^ T;
end
endmodule
| 6.528098 |
module t_ff_tb ();
// Step 1. Define a parameter with name "cycle" which is equal to 10
parameter cycle = 10;
reg clk, reset, t;
wire q, qb;
// Step 2. Instantiate the dff design
t_ff DUT (
.clk(clk),
.reset(reset),
.t(t),
.q(q),
.qb(qb)
);
// Step 3. Underst... | 6.501445 |
module tflipflop (
q,
qbar,
clk,
rst,
t
);
output reg q;
output qbar;
input clk, rst;
input t;
assign qbar = ~q;
always @(posedge clk) begin
if (rst) q <= 0;
else
case (t)
1'b0: q <= q;
1'b1: q <= ~q;
endcase
end
endmodule
| 6.576555 |
module Tflip_flop (
T,
clk,
reset,
Q
);
input T, clk, reset;
output Q;
reg Q;
wire D;
xor XOR (D, T, Q);
always @(negedge reset or posedge clk) begin
if (~reset) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.927708 |
module tfp401a (
input wire rst,
input wire odck_in,
input wire vsync_in,
input wire hsync_in,
input wire de_in,
input wire [7:0] pixel_r_in,
input wire [7:0] pixel_g_in,
input wire [7:0] pixel_b_in,
output reg scdt_o,
output wire odck_o,
output wire vsync_o,
output wir... | 6.562374 |
module tfp410 (
input wire rst,
input wire odck_in,
input wire vsync_in,
input wire hsync_in,
input wire de_in,
input wire [7:0] pixel_r_in,
input wire [7:0] pixel_g_in,
input wire [7:0] pixel_b_in,
output wire pixel_clk_o,
output wire vsync_o,
output wire hsync_o,
outp... | 7.272075 |
module tfpam ();
reg clk, rst;
reg pushin;
reg [63:0] ab, bb, cb, db, eb, fb;
wire pushout;
wire [63:0] z;
real a, b, c, d, e, f, res, rz;
reg [63:0] rfifo[0:128];
reg [6:0] rpt, wpt;
real r0 = 0.0;
real r1 = 1.0;
real mr1 = -1.0;
real r2 = 2.0;
real r2_5 = 2.5;
reg [63:0] mask = 64'hffff... | 6.621664 |
module TftDriver (
input clk,
output reg tft_h,
output reg tft_v,
output reg [ 3:0] tft_r,
output reg [ 3:0] tft_g,
output reg [ 3:0] tft_b,
input [14:0] pixel, // Pixel for current cycle.
input de,
input border,
output ... | 7.589874 |
module TFTLCDCtrl (
input clk,
input rst_n,
input [ 2:0] convert_type,
output [15:0] RGB, // TFT-LCD Red signal
output write_en,
output stop,
input [15:0] BRAMDATA, // BRAM Data 16bits
output reg [15:0] BRAMADDR // BRAM Address
);
alwa... | 7.256011 |
module tftlcd_pong_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S01_AXI
parameter integer C_S01_AXI_DATA_WIDTH = 32,
parameter integer C_S01_AXI_ADDR_WIDTH = 4
) (
// Users to add p... | 7.266773 |
module tfto_decade_counter (
input clk,
reset,
output wire [3:0] q
);
wire [3:0] tmpq;
wire check;
wire tmpwire;
reg [3:0] B;
four_bit_decade_counter fourbit (
clk,
reset,
tmpq
);
assign check = (tmpq[3] & ~tmpq[2]) | (tmpq[2] & tmpq[0]) | (tmpq[2] & tmpq[1] & ~tmpq[0]);
al... | 7.236144 |
module four_bit_decade_counter (
input clk,
reset,
output wire [3:0] q
);
wire [3:0] qc;
wire [3:0] tmpq;
wire [6:0] tmpwire;
jk_ff b1 (
1'b1,
1'b1,
clk,
tmpq[0],
qc[0]
);
and (tmpwire[0], tmpq[0], qc[3]);
jk_ff b2 (
tmpwire[0],
tmpwire[0],
clk,... | 7.235784 |
module adder4bit (
A,
B,
Ci,
S,
Co
);
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] A, B, S;
wire Ci, Co;
wire [2:0] C;
adder1bit add1 (
A[0],
B[0],
Ci,
S[0],
C[0]
);
adder1bit add2 (
A[1],
B[1],
C[0],
S[... | 6.983906 |
module tft_char (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output wire [15:0] rgb_tft, //输出像素信息
output wire hsync, //输出行同步信号
output wire vsync, //输出场同步信号
output wire tft_clk, //输出TFT时钟信号
output wire tft_de, //输出TFT使能信号... | 9.158181 |
module tft_color (
sclk,
srst,
hsync,
vsync,
rgb,
tft_bl,
tft_clk,
tft_de
);
input sclk;
input srst; // effective on Low Level
output hsync;
output vsync;
output [15:0] rgb;
output tft_bl;
output tft_clk;
output tft_de;
wire tft_sclk_33m;
wire tft_clk_50m;
wi... | 7.634653 |
module tft_colorbar (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output wire [15:0] rgb_tft, //输出像素信息
output wire hsync, //输出行同步信号
output wire vsync, //输出场同步信号
output wire tft_clk, //输出TFT时钟信号
output wire tft_de, //输出TFT... | 9.255621 |
module tft_pclk_gen (
clk,
rst,
pclk,
clock_divide,
lock
);
input clk;
input rst;
input [15:0] clock_divide;
//I need this statement because of simulation only in the real design, the pclk will transition when rst is low
output lock;
`ifdef VENDOR_XILINX
output pclk;
wire clk_fb... | 7.75834 |
module tft_pix (
tft_sclk_33m,
srst,
pix_x,
pix_y,
decode_finished,
etc_rgb,
//output
//rd_en,
image_start,
address,
pix_data
);
parameter H_VALID = 10'd800, V_VALID = 10'd480;
parameter RED = 16'hF800,
ORANGE = 16'hFC00,
YELLOW = ... | 7.014257 |
module: ACCM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_ACCM;
// Inputs
reg [6:0] X;
reg clk;
// Outputs
wire [15:0] ACC;
wire CO;
wire Mx;
// Instantiate the Unit... | 6.816828 |
module: AFE_ADS_TOP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_AFE_ADS;
// Inputs
reg sys_rst_n;
reg sys_clk;
reg AFE_STO;
reg AFE_EOC;
reg ADS_BUSY;
reg ADS_SDOA;
r... | 6.87026 |
module tf_AR_TXD;
// Inputs
reg clk;
reg [1:0] Nvel;
reg [7:0] ADR;
reg [22:0] DAT;
reg st;
// Outputs
wire ce_tact;
wire TXD1;
wire TXD0;
wire SLP;
wire en_tx;
wire T_cp;
wire FT_cp;
wire SDAT;
wire QM;
wire [5:0] cb_bit;
wire en_tx_word;
// Instantiate the Unit Under Test (UUT... | 6.525415 |
module tf_DISPL;
// Inputs
reg clk;
reg [7:0] HB;
reg [7:0] LB;
// Outputs
wire [3:0] AN;
wire [6:0] seg;
wire seg_P;
wire ce1ms;
// Instantiate the Unit Under Test (UUT)
DISPL uut (
.clk(clk),
.AN(AN),
.HB(HB),
.seg(seg),
.LB(LB),
.seg_P(seg_P),
.ce1ms... | 7.223089 |
module tf_FB16_to_FD27;
// Inputs
reg [15:0] FBI;
reg clk;
reg st;
// Outputs
wire [26:0] FDO;
wire [4:0] cb_tact;
wire EN_conv;
wire ok_conv;
// Instantiate the Unit Under Test (UUT)
FB16_to_FD27 uut (
.FDO(FDO),
.FBI(FBI),
.cb_tact(cb_tact),
.clk(clk),
.EN_conv(E... | 7.610092 |
module: Gen_M
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_M;
// Inputs
reg clk;
reg ce5ms;
reg [10:0] x;
// Outputs
wire s;
// Instantiate the Unit Under Test (U... | 6.786262 |
module: Gen_SIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_SIN;
// Inputs
reg clk;
reg ce;
// Outputs
wire S;
wire [3:0] X;
wire [7:0] Y;
wire [8:0] SIN;
// I... | 7.383916 |
module tf_Gen_st;
// Inputs
reg clk;
// Outputs
wire st;
// Instantiate the Unit Under Test (UUT)
Gen_st uut (
.clk(clk),
.st (st)
);
parameter Tclk = 20;
always begin
clk = 0;
#(Tclk / 2) clk = 1;
#(Tclk / 2);
end
initial begin
// Initialize Inputs
clk = 0;
... | 7.0985 |
module: Gen_TM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_TM;
// Inputs
reg clk;
reg st;
reg ce;
// Outputs
wire Tm;
// Instantiate the Unit Under Test (UUT)
... | 7.068677 |
module: Gen_Ux
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_Ux;
// Inputs
reg clk;
reg up;
reg BTN;
// Outputs
wire ceo;
wire ce1ms;
wire Ux;
wire [15:0] Xf;
/... | 7.421621 |
module tf_Gen_XY;
// Inputs
reg st;
reg clk;
reg [7:0] SW;
// Outputs
wire [11:0] Q;
wire UP;
wire [11:0] X;
wire [11:0] Y;
// Instantiate the Unit Under Test (UUT)
Gen_XY uut (
.Q (Q),
.st (st),
.UP (UP),
.clk(clk),
.X (X),
.SW (SW),
.Y (Y)
);
... | 6.815201 |
module tf_Hex;
// Inputs
reg [7:0] bin;
// Outputs
wire [9:0] bcd;
// Instantiate the Unit Under Test (UUT)
Hex2Dec uut (
.bin(bin),
.bcd(bcd)
);
initial begin
// Initialize Inputs
bin = 8'hA;
end
endmodule
| 6.944989 |
module tf_HEX27_to_DEC8;
// Inputs
reg [26:0] Dbin;
reg clk;
reg st;
// Outputs
wire [31:0] Ddec;
wire [3:0] ptr_dig;
// Instantiate the Unit Under Test (UUT)
HEX27_to_DEC8 uut (
.Dbin(Dbin),
.Ddec(Ddec),
.clk(clk),
.ptr_dig(ptr_dig),
.st(st)
);
parameter Tclk = 2... | 7.190962 |
module tf_quantization (
clk,
layer_reset,
stage_finish_i,
quan_weight_zero_i,
tf_quantization_en_i,
neuron_activation_i,
quan_scale_o
);
parameter NEURON_ACTIV_BIT_WIDTH = 8;
parameter SUM_QUAN_OFFSET_BIT_WIDTH = 16;
parameter INIT_SUM_QUAN_OFFSET = 16'd0;
parameter QUAN_SCALE_BIT... | 6.947266 |
module tf_Sch_test_SLAVE;
// Inputs
reg st;
reg clk;
reg [14:0] MTX_DAT;
reg RESET;
reg [14:0] STX_DAT;
// Outputs
wire LOAD;
wire SCLK;
wire MOSI;
wire [14:0] MRX_DAT;
wire [14:0] sr_MTX;
wire [14:0] sr_MRX;
wire [7:0] cb_bit;
wire ce_tact;
wire MISO;
wire [14:0] sr_STX;
wire [14:... | 6.58972 |
module tf_Sch_test_URXD1B;
// Inputs
reg tx_clk;
reg st;
reg [7:0] tx_dat;
reg rx_clk;
// Outputs
wire TXD;
wire [3:0] cb_bit_tx;
wire en_rx_byte;
wire [7:0] sr_dat;
wire [3:0] cb_bit_rx;
wire ok_rx_byte;
wire start_rx;
wire T_start;
wire T_dat;
wire T_stop;
wire ce_tact;
wire ce_b... | 6.708776 |
module tf_SOURCES_DAT;
// Outputs
wire [14:0] MASTER_dat;
wire [15:0] MASTER_dat_disp;
wire [15:0] SLAVE_dat_disp;
wire [14:0] SLAVE_dat;
// Instantiate the Unit Under Test (UUT)
SOURCES_DAT uut (
.MASTER_dat(MASTER_dat),
.MASTER_dat_disp(MASTER_dat_disp),
.SLAVE_dat_disp(SLAVE_dat_dis... | 6.848456 |
module tf_SPI_DAC8043;
// Inputs
reg st;
reg clk;
reg [11:0] DI;
// Outputs
wire SDAT;
wire SCLK;
wire NLD;
wire ce;
wire [3:0] cb_bit;
// Instantiate the Unit Under Test (UUT)
SPI_DAC8043 uut (
.SDAT(SDAT),
.st(st),
.SCLK(SCLK),
.clk(clk),
.DI(DI),
.NLD(NL... | 6.506143 |
module tf_SPI_MASTER;
// Inputs
reg st;
reg clk;
reg MISO;
reg clr;
reg [14:0] DI;
// Outputs
wire LOAD;
wire SCLK;
wire MOSI;
wire ce;
wire ce_tact;
wire [7:0] cb_bit;
wire [14:0] sr_MTX;
wire [14:0] sr_MRX;
wire [14:0] DO;
// Instantiate the Unit Under Test (UUT)
SPI_MASTER uut ... | 6.99594 |
module testbench;
parameter cyc = 10; //use "cyc" to represent the period
///// declare input(reg) and output(wire) /////
reg clk;
reg rst_n;
reg enable;
wire [1:0] out_state;
///// declare module /////
trafficlight #(
.RED_TIME(3),
.GREEN_TIME(2),
.YELLOW_TIME(1)
) u1 (
... | 7.015571 |
module: transform
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_test;
// Inputs
reg clk;
reg [10:0] t_height;
reg [10:0] t_width;
reg [10:0] x;
reg [9:0] y;
// Outputs
... | 6.675281 |
module: transform
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_testb;
// Inputs
reg clk;
reg [10:0] t_height;
reg [10:0] t_width;
reg [10:0] x;
reg [9:0] y;
// Outputs... | 6.675281 |
module tf_Test_DET_FSK;
// Inputs
reg clk;
reg st;
reg [7:0] dat;
reg [7:0] Mamp;
// Outputs
wire [11:0] FSK_SH;
wire S;
wire ce_SIN;
wire en_tx;
wire TX_bit;
wire ce_tx_bit;
wire [11:0] DFSK_SH;
wire OCD;
wire [11:0] AMP;
wire [12:0] bf_SH;
wire FSK_tact;
wire [6:0] cb_tact;
wir... | 6.757608 |
module: Test_MES_AMP_SIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "CONST.v"
module tf_Test_MES_AMP_SIN;
// Inputs
reg clk;
reg ce;
reg [7:0] NT;
reg [8:0] NS;
reg we;
... | 7.572703 |
module tf_Test_RX_ATRP_AR_TXA;
// Inputs
reg clk;
reg [5:0] M;
// Outputs
wire [11:0] TXA;
wire [11:0] D_RXA;
wire [11:0] Xns;
wire RXP;
wire RXN;
wire [10:0] AMP;
wire res;
wire [7:0] N_RXPN;
wire en_TX;
wire err;
// Instantiate the Unit Under Test (UUT)
Test_RX_ATRP_AR_TXA uut (
... | 6.638156 |
module tf_Test_RX_MTR;
// Inputs
reg clk;
reg st;
reg [5:0] M;
reg S;
reg res;
// Outputs
wire [11:0] MTRP;
wire [11:0] MEM_dat;
wire [11:0] Xmax;
wire [11:0] Xns;
wire [11:0] Xmin;
wire [11:0] REF_P;
wire [11:0] REF_N;
wire RXP;
wire RXN;
wire [10:0] AMP;
// Instantiate the Unit ... | 7.203734 |
module tf_Test_Sch;
// Inputs
reg clk;
reg [1:0] Nvel;
reg [7:0] ADR;
reg [22:0] DAT;
reg st;
// Outputs
wire ce_tx;
wire TXD1;
wire TXD0;
wire SLP;
wire en_tx_dat;
wire T_cp_tx;
wire FT_tx;
wire SDAT;
wire QM;
wire [5:0] cb_bit;
wire en_tx_word;
wire [22:0] sr_dat_rx;
wire [7:... | 6.555105 |
module tf_UTXD1B;
// Inputs
reg clk;
reg [7:0] dat;
reg st;
// Outputs
wire TXD;
wire ce_tact;
wire [3:0] cb_bit;
wire T_start;
wire T_dat;
wire T_stop;
wire ce_stop;
wire en_tx_byte;
wire [7:0] sr_dat;
// Instantiate the Unit Under Test (UUT)
UTXD1B uut (
.clk(clk),
.TXD(... | 7.159277 |
module: VCB4SED
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_VCB4SED;
// Inputs
reg ce;
reg clk;
reg s;
// Outputs
wire [3:0] Q;
wire TC;
wire CEO;
// Instantiate t... | 6.971183 |
module.
// The dual-port ram holding the program is part of the local bus
// address space, defined by an external address decoder that supplies
// the dests_write port signal. The size of that memory is defined
// by the pcw parameter.
// After filling the table, toggle bank_next to make it take effect.
// In theor... | 8.331668 |
module tgen_tb;
reg clk;
integer cc, errors;
`ifdef SIMULATE
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("tgen.vcd");
$dumpvars(5, tgen_tb);
end
errors = 0;
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 240; cc = cc + 1) begin
clk = 0;... | 6.817933 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.