code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tg_prbs_gen #(
parameter PRBS_WIDTH = 64, // // "SEQUENTIAL_BURST"
parameter START_ADDR = 32'h00000000,
parameter DMODE = "READ",
parameter PRBS_OFFSET = 0,
parameter [PRBS_WIDTH-1:0] TAPS= 32'h80200003 //32'b10000000_00... | 7.599107 |
module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module tg_status ... | 7.544807 |
module thcomp ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Parameters------------------------------
parameter IDLE = 1'b0, CMP = 1'b1;
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input thcomptop_thcomp_start;
input [MSB:0] thcompregs_thcomp_reg_data_out0;
... | 6.861777 |
module thcompregs ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input cfg_we;
input [MSB_REGS_ADDRESS:0] cfg_addr;
input [MSB:0] cfg_data_in;
input thcomptop_thcompregs_we0;
input [MSB:0] thcomptop_thcompregs_reg_data_in0;
/... | 6.626007 |
module thcomptop ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Parameters------------------------------
parameter IDLE = 2'b00, START = 2'b01, CMP = 2'b10;
parameter MSB_STATE = 1;
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input ematop_thcomptop_start;
... | 6.892987 |
module regFile (
rs_address,
rt_address,
dest_address,
writeBack_data,
reg_write,
clk,
rs_data,
rt_data,
reg_file_address,
reg_file_data
); // 6 i/p , 2 o/p
input [4:0] rs_address, rt_address, reg_file_address; //address '5 bits
input [4:0] dest_address;
input [31:0] wr... | 7.797802 |
module ForwardUnit (
ID_EX_RS,
ID_EX_RT,
EX_MEM_RD,
MEM_WB_RD,
ForwardA,
ForwardB,
MEM_RegWrite,
WB_RegWrite
);
input wire [4:0] ID_EX_RS, ID_EX_RT, EX_MEM_RD, MEM_WB_RD;
input wire MEM_RegWrite, WB_RegWrite;
output reg [1:0] ForwardA, ForwardB;
always @* begin
if ((MEM_Re... | 6.879476 |
module testbench;
wire [31:0] pc_output, ALU_Result, Mem_out, Instr_32;
wire [31:0] reg_file_data;
reg [ 4:0] reg_file_address;
reg [31:0] read_address, write_address; //address '32 bits
reg [7:0] write_data;
reg We, clk;
wire [31:0] read_data;
reg [7:0] index[0:256];
always #100 clk = ~clk;
... | 7.015571 |
module dataMem (
R1,
D1,
We,
Re,
clk,
O1
); // 5 i/p , 1 o/p
input [31:0] R1; //address '32 bits
input [31:0] D1; // data to be saved '32 bits
input We, Re;
input clk;
output reg [31:0] O1; //output data from R1 '32 bits
reg [7:0] index[0:255]; // first is number of mem size... | 6.754704 |
module InstMem (
read_address,
write_address,
write_data,
We,
clk,
read_data
); // 5 i/p , 1 o/p
input [31:0] read_address, write_address; //address '32 bits
input [7:0] write_data;
input clk, We;
output reg [31:0] read_data; //output data from R1'32 bits
reg [7:0] index[0:255]; ... | 6.646235 |
module signext (
ip,
op
);
input [15:0] ip;
output [31:0] op;
reg [31:0] ext;
always @(*) begin
ext[15:0] = ip;
ext[31:16] = {16{ip[15]}};
end
assign op = ext;
endmodule
| 7.970829 |
module mux_2x1_5 (
ip0,
ip1,
sel,
out
);
input sel;
input [4:0] ip1;
input [4:0] ip0;
output reg [4:0] out;
always @(*) begin
if (sel == 1'b1) begin
out <= ip1;
end else begin
out <= ip0;
end
end
endmodule
| 6.663991 |
module mux_2x1_32 (
ip0,
ip1,
sel,
out
);
input sel;
input [31:0] ip1;
input [31:0] ip0;
output reg [31:0] out;
always @(*) begin
if (sel == 1'b1) begin
out <= ip1;
end else begin
out <= ip0;
end
end
endmodule
| 7.462987 |
module mux_3x1_32 (
ip0,
ip1,
ip2,
sel,
out
);
input [1:0] sel;
input [31:0] ip1;
input [31:0] ip0;
input [31:0] ip2;
output reg [31:0] out;
always @(*) begin
if (sel == 2'b0) out <= ip0;
else if (sel == 2'b1) begin
out <= ip1;
end else if (sel == 2'b10) begin
o... | 6.941975 |
module IF_ID (
clk,
input_pc,
output_pc,
input_Inst,
output_Inst
);
input wire [31:0] input_pc, input_Inst;
input clk;
output reg [31:0] output_pc, output_Inst;
always @(posedge clk) begin
output_pc <= input_pc;
output_Inst <= input_Inst;
end
endmodule
| 7.397718 |
module andg (
out,
a,
b
);
input a, b;
output reg out;
always @(*) begin
out <= a & b;
end
endmodule
| 6.551197 |
module pro_counter (
in,
clk,
reset,
out
);
input [7:0] in;
input clk;
input reset;
output reg [7:0] out;
always @(posedge clk) begin
if (reset) out <= 8'b00000000;
else out <= in;
end
endmodule
| 6.693721 |
module CONTROL_UNIT (
input [3:0] opcode,
output reg reg_sel,
output reg alu_src,
output reg reg_w_enbl,
output reg br,
output reg jump,
output reg m_r_enbl,
output reg m_w_enbl,
output reg mem_mux,
output reg [3:0] to_alu_ctrl
);
always @(opcode) begin
to_alu_ctrl <=... | 6.766875 |
module dmem (
input [7:0] addr,
input [7:0] in,
input read,
input write,
input clk,
output [7:0] out
);
reg [7:0] out;
reg [7:0] DATA[255:0];
always @(posedge clk) begin
#1;
if (read == 1) begin
out <= DATA[addr];
end else if (write == 1) DATA[addr] <= in;
end
e... | 7.276583 |
module imem (
input [ 7:0] Addr,
output [15:0] rd
);
reg [15:0] RAM[256:0];
initial begin
RAM[8'b00000000] = 16'b0100110000000101;
RAM[8'b00000001] = 16'b0100111000001010;
RAM[8'b00000010] = 16'b1111110000000000;
RAM[8'b00000011] = 16'b1111111000000001;
RAM[8'b00000100] = 16'b101100100... | 6.860817 |
module reg_file (
input clk,
input rst,
// write port
input reg_write_en,
input [2:0] reg_write_dest,
input [7:0] reg_write_data,
//read port 1
input [2:0] reg_read_addr_1,
output [7:0] reg_read_data_1,
//read port 2
input [2:0] reg_read_addr_2,... | 7.294051 |
module cpu ();
reg clk = 1'b0;
reg pc_rst, reg_rst;
wire [7:0] pc_in, pc_out, inc_pc;
wire reg_sel, alu_src, reg_w_enbl, br, jump, m_r_enbl, m_w_enbl, mem_mux_sel;
wire [ 3:0] to_alu_ctrl;
wire [15:0] inst;
wire [2:0] mx_t_reg, alu_ctrl_t_alu;
wire [7:0] reg_w_data, reg_a_data, reg_b_data, alu_out, m... | 6.915037 |
module thedesign (
input wire i_clk,
input wire i_reset,
input wire i_btn,
`ifdef VERILATOR
output wire [31:0] o_setup,
`endif
`ifdef USB_UART
input wire i_clk48,
inout wire usb_p,
inout wire usb_n,
`endif
output wire o_uart_tx,
output wire [7:0] o_debug
);
wire tx_stb, tx_busy, ... | 7.893862 |
module theFFT (
clk,
reset_n,
inverse,
sink_valid,
sink_sop,
sink_eop,
sink_real,
sink_imag,
sink_error,
source_ready,
sink_ready,
source_error,
source_sop,
source_eop,
source_valid,
source_exp,
source_real,
source_imag
);
input clk;
input res... | 7.019736 |
module thermometer_to_bcd (
bcd,
thermometer
);
output [7:0] bcd;
input [15:0] thermometer;
assign bcd = (thermometer == 16'b0) ? 0 :
(thermometer == 16'b1) ? 1 :
(thermometer == 16'b11) ? 2 :
(thermometer == 16'b111) ? 3 :
(thermometer == 16'b1111) ? ... | 7.27633 |
module thermometer_to_bcd_tb;
wire [ 7:0] bcd;
reg [15:0] thermometer = 0;
thermometer_to_bcd translator (
bcd,
thermometer
);
initial begin
$monitor("thermometer: %b, bcd: %b, dec: %d%d", thermometer, bcd, bcd[7:4], bcd[3:0]);
repeat (16) #5 thermometer = {thermometer[14:0], 1'b1};
... | 7.27633 |
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = ~mode & too_hot;
assign fan = (mode & too_cold) | (~mode & too_hot) | fan_on;
endmodule
| 7.203305 |
module thermo_maj (
in1,
in2,
in3,
in4,
out
);
input [14:0] in1, in2, in3, in4;
output [3:0] out;
wire [14:0] thermo_out;
majority maj0 (
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.out(thermo_out)
);
thermo_to_bin encoder0 (
.thermo(thermo_out),
... | 6.811401 |
module thermo_to_onehot (
thermo,
onehot
);
input [14:0] thermo;
output reg [15:0] onehot;
integer i;
always @(thermo) begin
if (thermo[0] == 0) onehot[0] = 1;
else onehot[0] = 0;
onehot[15] = thermo[14];
for (i = 14; i > 0; i = i - 1) begin
onehot[i] = thermo[i] ^ thermo[i-1];
... | 6.77721 |
module therm_out (
input wire clk,
input wire rst,
input wire [31:0] therm_in,
output wire therm_do,
output wire therm_fs
);
reg [5:0] therm_in_buf;
wire [4:0] therm_z;
count_lead_zero #(
.W_IN (32),
.W_OUT(5)
) clz (
.in (therm_in_buf),
.out(therm_z)
);
reg [... | 6.82457 |
module count_lead_zero #(
parameter W_IN = 64, // Must be power of 2, >=2
parameter W_OUT = 6
) (
input wire [ W_IN-1:0] in,
output wire [W_OUT-1:0] out
);
generate
if (W_IN == 2) begin : base
assign out = !in[1];
end else begin : recurse
wire [ W_OUT-2:0] half_count;
w... | 7.246378 |
module.
module BCD_TO_7SEG(
bcd,
leds
);
// Declare inputs, outputs and internal variables.
input [3:0] bcd;
output reg [6:0] leds;
// always block for converting bcd digit into 7 segment format
always @ (*) begin
case (bcd)
4'b0000 : leds = 7'b1111110; // O ... | 8.215158 |
module the_test (
input tb_clk,
input tb_rst
);
reg [31:0] d_out;
task run_the_test;
begin
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
repeat (6) @(posedge... | 7.031746 |
module The_Top (
input clk_in,
input reset,
input key_clk,
input key_data,
output [7:0] o_seg,
output [7:0] o_sel
);
wire clk;
wire key_state;
wire [7:0] key_ascii;
wire [31:0] final_num;
Divider #(800) divider (
clk_in,
reset,
clk
);
Keyboard_PS2 keyboard (
... | 7.977606 |
modules in order to be authentic to the SM83 topology. We will leave the architectural solution as an appendix to the developers of the SM83.
module Thingy ( w8, w31, w35, ALU_to_Thingy, WR, Temp_Z, TTB1, TTB2, TTB3, Thingy_to_bot, bot_to_Thingy );
input w8;
input w31;
input w35;
input ALU_to_Thingy;
input WR;
... | 7.347743 |
module add (
out,
A,
B
);
output [63:0] out;
input [63:0] A;
input [63:0] B;
assign out = A + B;
endmodule
| 6.843391 |
module And (
out,
A,
B
);
output [63:0] out;
input [63:0] A;
input [63:0] B;
assign out = A & B;
endmodule
| 6.789627 |
module Xor (
out,
A,
B
);
output [63:0] out;
input [63:0] A;
input [63:0] B;
assign out = A ^ B;
endmodule
| 7.144897 |
module ThirdTap (
rst,
clk,
Xin,
Yout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟，频率为2kHz
input signed [8:0] Xin; //数据输入频率为2kHZ
output signed [10:0] Yout; //滤波后的输出数据
//零点系数的实现代码/////////////////////////
//将输入数据存入移位寄存器中
reg signed [8:0] Xin1, Xin2;
always @(posedge clk or posed... | 7.175866 |
module third_assign_osc (
CLOCK_50,
SWTCH,
VGA_CLK,
VGA_VS,
VGA_HS,
VGA_BLANK_n,
VGA_B,
VGA_G,
VGA_R
);
input CLOCK_50;
input SWTCH;
output VGA_CLK;
output VGA_VS;
output VGA_HS;
output VGA_BLANK_n;
output wire [7:0] VGA_B;
output wire [7:0] VGA_G;
output wire [7:0]... | 7.499189 |
module: thirteen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module thirteen_test;
// Inputs
reg MR;
reg LOAD;
reg EN;
reg UpDown;
reg CLK;
reg [3:0] D;
// Outputs
wire [3:0]... | 6.71885 |
module ThirtyTwoBitAdderTB ();
reg [31:0] A;
reg [31:0] B;
reg cin;
wire [31:0] sum;
wire cout;
wire overFlow;
ThirtyTwoBitAdder uut (
.A,
.B,
.cin,
.sum,
.cout,
.overFlow
);
initial begin
assign cin = 0;
assign A = 32'b01010100101100111101010011000011;
... | 6.829372 |
module ThirtyTwoBitSub (
input [31:0] B,
input [31:0] A,
input cin,
output [31:0] Diff
);
//cin = 1 to be subtraction
wire [31:0] Ba;
wire [31:0] ecin;
wire cout;
wire overFlow;
//[31:0] array of cins --> bitwise XORed with B --> this bitwise XORed value then will go into B
// if Cin i... | 7.948503 |
module ThirtyTwoBitSubTB ();
reg [31:0] A;
reg [31:0] B;
reg cin;
wire [31:0] Diff;
ThirtyTwoBitSub uut (
.A,
.B,
.cin,
.Diff
);
initial begin
assign A = 32'b01010100101100111101010011000011;
assign B = 32'b00101101011101010000000101110111;
assign cin = 1;
end
endm... | 7.948503 |
module thirty_second_timer (
clk,
rst,
show,
ssd_active
);
input clk, rst;
output [7:0] show;
output [3:0] ssd_active;
reg [4:0] q_temp;
reg [4:0] q;
reg [7:0] a;
reg [7:0] b;
reg [7:0] show;
reg [3:0] ssd_active;
wire clk_1hz;
wire ssd_ctrl;
frequency_divider_about_1hz U0 (
... | 7.43344 |
module thirty_two_bit_alu (
a,
b,
inp,
out
);
input [31:0] a, b;
input [2:0] inp;
output reg [31:0] out;
always @(inp) begin
case (inp)
3'b000: out = 0; //clear
3'b001: out = a + b; //addition
3'b010: out = a - b; //subtraction
3'b011: out = a << 1; //left shift
... | 6.672265 |
module thirty_two_bit_cla (
a,
b,
c0,
s,
cout
);
input [31:0] a, b; //32 bit input
input c0;
output [31:0] s;
output cout;
//32 bit CLA made from 8 4-bit CLA
wire c1, c2, c3, c4, c5, c6, c7;
carry_look CA1 (
a[3:0],
b[3:0],
c0,
s[3:0],
c1
);
carry_loo... | 6.672265 |
module thirty_two_bit_cselect (
a,
b,
c0,
s,
cout
);
input [31:0] a, b;
input c0;
output [31:0] s;
output cout;
//32 bit carry select adder with 8 4-bit carry select adder
wire [3:0] x, y, c1, c2, c3, c4, c5, c6, c7, c8;
carry_select CSL1 (
a[3:0],
b[3:0],
c0,
... | 6.672265 |
module thirty_two_bit_cskip (
a,
b,
c0,
s,
cout
);
input [31:0] a, b;
input c0;
output [31:0] s;
output cout;
//32 bit carry skip adder with 8 4-bit Carry Skip Adder
wire c1, c2, c3, c4, c5, c6, c7;
carry_skip CS1 (
a[3:0],
b[3:0],
c0,
s[3:0],
c1
);
c... | 6.672265 |
module thread_number #(
parameter N_CORES = -1,
parameter N_THREADS = 2 * N_CORES,
parameter N_THREADS_MSB = `MSB(N_THREADS - 1)
) (
input CLK,
input entry_pt_switch,
output [N_THREADS_MSB : 0] ts_rd_num,
input [`THREAD_STATE_MSB : 0] ts_rd,
input NEXT_THREAD,
output RELOAD,
... | 6.849515 |
module three (
G1,
G2,
G3,
A,
Y
);
input G1, G2, G3;
input [2:0] A;
output [7:0] Y;
wire G1, G2, G3;
wire [2:0] A;
reg [7:0] Y;
always @(A, G1, G2, G3) begin
if (~G1 | G2 | G3) Y = 8'b1111_1111;
else
case (A)
3'b000: Y = 8'b1111_1110;
3'b001: Y = 8'b1111_... | 6.570476 |
module tb_comparator3 ();
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
comparator3 test_comparator3 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
A = 3'b001;
B = 3'b001;
... | 6.843472 |
module threeBitDFFupCounterWasynClock (
count,
Clk,
ClrN
);
output [2:0] count;
input Clk, ClrN;
wire w2, w1, w0;
wire [2:0] dummy;
dFlipFlopNegClkNegRst
c0 (
w0,
dummy[0],
~w0,
Clk,
ClrN
),
c1 (
w1,
dummy[1],... | 7.228737 |
module threeBitDFFupCounterWasynClock_tb;
input [2:0] count;
output reg Clk, ClrN;
threeBitDFFupCounterWasynClock dffAsynClock (
count,
Clk,
ClrN
);
initial /*stimulus*/
begin
$dumpfile("Simulation/threeBitDFFupCounterWasynClock_tb.vcd");
$dumpvars;
$monitor($time, " Clk=%b,... | 7.228737 |
module threebit_adder (
input carry_in,
input [2:0] a,
input [2:0] b,
output [2:0] sum,
output carry_out
);
// internal signals
wire stage1_carry;
wire stage2_carry;
full_adder stage1 (
.carry_in(carry_in),
.a(a[0]),
.b(b[0]),
.sum(sum[0]),
.carry_out(stage1_... | 8.166291 |
module threebit_adder_tb;
// Inputs
reg [2:0] t_a;
reg [2:0] t_b;
reg t_carry_in;
// Outputs
wire [2:0] t_sum;
wire t_carry_out;
// Instantiate the Unit Under Test (UUT)
threebit_adder UUT (
.carry_in(t_carry_in),
.a(t_a),
.b(t_b),
.sum(t_sum),
.carry_out(t_carry_out)
... | 8.166291 |
module represents a three by one mux.
**********************************************************************/
`timescale 1ns / 1ps
module threebyone_MUX(input [31:0] A, [31:0] B, [31:0] C,input [1:0]S, output reg[31:0] r );
always @(*) begin
case(S)
2'b00: r=A;
2'b01: r=B;
2'b10: r=C;
default: r=A;
endcase
end
e... | 7.311982 |
module ThreeInOneSelector5Bit (
input [1:0] Control,
input [4:0] OneInput,
input [4:0] TwoInput,
output reg [4:0] DataOutput
);
always @(Control or TwoInput or OneInput) begin
if (Control == 2'b00) DataOutput = 5'b11111;
else if (Control == 2'b01) DataOutput = OneInput;
else if (Control =... | 6.944395 |
module ThreeInputOrGate (
input i1,
input i2,
input i3,
output gateOutput
);
or (gateOutput, i1, i2, i3);
endmodule
| 7.420145 |
module ThreeMusicNotes (
keyC,
keyD,
keyE,
Speaker,
Reset,
Clock
);
parameter NumberOfBits = 20;
input keyC, keyD, keyE, Reset, Clock;
output Speaker;
wire [NumberOfBits-1:0] NoteC, NoteD, NoteE;
wire NoteCoutput, NoteDoutput, NoteEoutput;
assign Speaker = NoteCoutput || NoteDoutpu... | 8.544833 |
module THREEtoEIGHT_decoder (
DA,
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7
);
input [2:0] DA; //address to which data will be written
output wire R0, R1, R2, R3, R4, R5, R6, R7; //wire corresponding to one of 8 registers
//combinational logic
assign R0 = ~DA[2] & ~DA[1] & ~DA[0];
a... | 6.895561 |
module ThreeToOneMux #(
parameter integer RV_BIT_NUM_THREE = `RV_BIT_NUM_THREE)
(
input [`MUX_WIDTH_THREE-1:0] sel,
input [(RV_BIT_NUM_THREE*`MUX_OPTION_THREE)-1 : 0] d,
output reg [RV_BIT_NUM_THREE-1:0]q);
always@(*) begin
case( sel )
`muxcasethree(`MUX_WI... | 8.292129 |
module three_1_mux (
data1,
data2,
data3,
sel,
outputdata
);
input [15:0] data1;
input [15:0] data2;
input [15:0] data3;
input [1:0] sel;
output [15:0] outputdata;
reg [15:0] outputdata;
parameter first = 2'b00;
parameter second = 2'b01;
parameter third = 2'b10;
always @(sel o... | 8.449086 |
module tri_3_input_and_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
a2,
b2,
c2,
a3,
b3,
c3,
output wire y1,
y2,
y3
);
and #DELAY (y1, a1, b1, c1);
and #DELAY (y2, a2, b2, c2);
and #DELAY (y3, a3, b3, c3);
endmodule
| 8.188634 |
module tri_3_input_nand_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
a2,
b2,
c2,
a3,
b3,
c3,
output wire y1,
y2,
y3
);
nand #DELAY (y1, a1, b1, c1);
nand #DELAY (y2, a2, b2, c2);
nand #DELAY (y3, a3, b3, c3);
endmodule
| 8.082136 |
module tri_3_input_nor_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
a2,
b2,
c2,
a3,
b3,
c3,
output wire y1,
y2,
y3
);
nor #DELAY (y1, a1, b1, c1);
nor #DELAY (y2, a2, b2, c2);
nor #DELAY (y3, a3, b3, c3);
endmodule
| 8.082136 |
module three_bits_decoder_enable (
output reg [7:0] Y,
input [2:0] I,
input En
);
always @(I or En) begin
if (En == 1'b1)
case (I)
3'b000: Y = 8'b00000001;
3'b001: Y = 8'b00000010;
3'b010: Y = 8'b00000100;
3'b011: Y = 8'b00001000;
3'b100: Y = 8'b00010000;... | 8.452091 |
module Three_Bit_Comparator (
A,
B,
Greater,
Less,
Equal
);
input [2:0] A, B;
output Greater, Less, Equal;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13;
not n1 (w1, A[0]);
not n2 (w2, A[1]);
not n3 (w3, A[2]);
not n4 (w4, B[0]);
not n5 (w5, B[1]);
not n6 (w6, B[2]);
... | 6.599156 |
module Three_Bit_Comparator_TB;
reg [2:0] A;
reg [2:0] B;
wire Greater;
wire Less;
wire Equal;
Three_Bit_Comparator uut (
.A(A),
.B(B),
.Greater(Greater),
.Less(Less),
.Equal(Equal)
);
initial
$monitor("A = %d | B = %d | Greater = %b | Equal = %b | Less = %b", A, B, Gre... | 6.599156 |
module three_bit_comparator_test;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
wire GT;
wire LT;
wire EQ;
// Instantiate two counter variables for both loop
integer count;
// Instantiate the Unit Under Test (UUT)
three_bit_comparator uut (
.A (A),
.B (B),
.GT(GT),
.LT... | 8.281171 |
module: three_bit_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module three_bit_test;
// Inputs
reg enable;
reg mode;
reg clk;
reg clear;
reg preset;
reg [2:0] load;
//... | 7.884088 |
module up_down_synchronous_counter (
Q,
M,
CLR,
CLK
);
input M, CLR, CLK;
output [2:0] Q;
wire [2:0] J, K, Qbar;
// Dataflow Modeling
assign J[0] = (~M & ~Q[1] & ~Q[2]) | (M & Q[1] & Q[2]),
K[0] = J[0],
J[1] = ~(M ^ Q[2]),
K[1] = J[1],
J[2] = 1,
K[2] = 1;
//... | 7.759982 |
module Level1 (
input [15:0] addr,
output [15:0] data
);
wire [15:0] level2_addr;
wire [15:0] level2_data;
Level2 level2 (
.addr(level2_addr),
.data(level2_data)
);
assign data = level2_data;
assign level2_addr = addr;
endmodule
| 7.460002 |
module Level2 (
input [15:0] addr,
output [15:0] data
);
wire [15:0] memory_addr;
wire [15:0] memory_data;
Level3 memory (
.addr(memory_addr),
.data(memory_data)
);
assign data = memory_data;
assign memory_addr = addr;
endmodule
| 7.782242 |
module Level3 (
input [15:0] addr,
output [15:0] data
);
assign data = addr;
endmodule
| 6.678458 |
module Top (
input clk,
input reset,
input [15:0] addr,
output [15:0] data
);
wire [15:0] level1_addr;
wire [15:0] level1_data;
Level1 level1 (
.addr(level1_addr),
.data(level1_data)
);
assign data = level1_data;
assign level1_addr = addr;
endmodule
| 6.64497 |
module with_SSI (
input a,
b,
c,
d,
output f3,
f2,
f1,
f0
);
// GATE LEVEL DESIGN
wire temp1, temp2, temp3, temp4, temp5, temp6;
and (temp1, a, d);
and (temp2, b, c);
and (f3, temp1, temp2);
and (temp3, a, c);
NAND nand0 (
temp4,
b,
d
);
and (f2, t... | 6.893239 |
module with_MUX (
input a,
b,
c,
d,
output f3,
f2,
f1,
f0
);
// With MUX
wire temp12, temp13, temp14, temp15, temp16, temp17, temp18;
and (temp12, b, d);
MUX mux0 (
f0,
{temp12, temp12, temp12, temp12},
{a, c}
);
NOT not0 (
temp13,
d
);
NO... | 6.760408 |
module three_eight (
m,
y
);
input wire [2:0] m;
output reg [7:0] y;
reg move;
always @(*) begin
move = 1;
y = ~(move << m);
end
endmodule
| 7.168577 |
module Three_EightMux (
out1,
mov_out,
Not_out,
add_out,
sub_out,
or_out,
and_out,
select
);
input mov_out, Not_out, add_out, sub_out, or_out, and_out;
input [2:0] select;
output reg out1;
always @(*) begin
case (select)
3'b000: out1 = mov_out;
3'b001: out1... | 7.141743 |
module three_eight_decoder (
d,
a
);
output [7:0] d;
input [2:0] a;
wire [2:0] nota;
not not_gates[2:0] (nota, a);
and (d[0], nota[2], nota[1], nota[0]);
and (d[1], nota[2], nota[1], a[0]);
and (d[2], nota[2], a[1], nota[0]);
and (d[3], nota[2], a[1], a[0]);
and (d[4], a[2], nota[1], nota[0... | 6.538449 |
module three_eight_decoder_tb;
reg [2:0] a;
wire [7:0] d;
three_eight_decoder decoder (
d,
a
);
initial begin
$monitor($time, " d: %b, a: %b", d, a);
a = 0;
repeat (7) #5 a = a + 1;
end
endmodule
| 6.538449 |
module three_fsm_tb;
reg clk;
reg [3:0] choose;
reg [15:0] hs_3fsm = 16'b1111_1111_1010_1010;
reg [15:0] vs_3fsm = 16'b1111_1111_0001_0001;
reg [15:0] pic_ena = 16'b1111_1111_1111_1111;
wire [11:0] VGA_data;
wire final_pic_ena;
wire HSYNC, VSYNC;
three_fsm U_3fsm (
.clk(clk),
.rst(1'b0),
... | 8.211055 |
module three_inputs_gate (
a,
b,
c,
out
);
input wire a;
input wire b;
input wire c;
output wire out;
assign out = a | b | c;
endmodule
| 8.156517 |
module three_inputs_gate_tb;
`define THREE_INPUTS_TEST(ID, A, B, C, OUT) \
a = A; \
b = B; \
c=C;\
#5; \
if(out == OUT) \
$display("Case %d passed!", ID); \
else begin \
$display("Case %d failed!", ID); \
$finish; \
end \
#5;
reg a;
reg b;
reg c;
wi... | 8.156517 |
module three_input_and_gate (
input a,
b,
c,
output x,
y
);
assign x = a & b;
assign y = x & c;
endmodule
| 7.125004 |
module three_input_and_gate_a (
input a,
input b,
input c,
output d
);
assign d = a & b & c;
endmodule
| 7.125004 |
module three_input_and_gate_a_tb;
reg aa, bb, cc;
wire y;
three_input_and_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(y)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#100... | 7.125004 |
module three_input_AND_gate_b (
input A,
input B,
output D,
input C,
output E
);
assign D = A & B;
assign E = D & C;
endmodule
| 7.245442 |
module three_input_AND_gate_b_tb;
reg aa, bb, cc;
wire dd, ee;
three_input_AND_gate_b u_inv (
.A(aa),
.B(bb),
.D(dd),
.C(cc),
.E(ee)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initi... | 7.245442 |
module three_input_and_gate_tb;
reg aa, bb, cc;
wire x, y;
three_input_and_gate u_three_input_and_gate (
.a(aa),
.b(bb),
.c(cc),
.x(x),
.y(y)
);
initial aa = 0'b0;
initial bb = 0'b0;
initial cc = 0'b0;
always aa = #50 ~aa;
always bb = #100 ~bb;
always cc = #200 ~cc;... | 7.125004 |
module three_input_nand_gate_a (
input a,
input b,
input c,
output d
);
assign d = ~(a & b & c);
endmodule
| 6.503775 |
module three_input_nand_gate_a_tb;
reg aa, bb, cc;
wire y;
three_input_nand_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(y)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1... | 6.503775 |
module three_input_nand_gate_b (
input a,
input b,
input c,
output d,
output e
);
assign d = ~(a & b);
assign e = ~(d & c);
endmodule
| 6.503775 |
module three_input_nand_gate_b_tb;
reg aa, bb, cc;
wire d, e;
three_input_nand_gate_b u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d),
.e(e)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
ini... | 6.503775 |
module three_input_nor_gate_a (
input a,
input b,
input c,
output d
);
assign d = ~(a | b | c);
endmodule
| 6.503775 |
module three_input_nor_gate_a_tb;
reg aa, bb, cc;
wire d;
three_input_nor_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#100... | 6.503775 |
module three_input_nor_gate_b (
input a,
input b,
input c,
output d,
output e
);
assign d = ~(a | b);
assign e = ~(d | c);
endmodule
| 6.503775 |
module three_input_nor_gate_b_tb;
reg aa, bb, cc;
wire d, e;
three_input_nor_gate_b u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d),
.e(e)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initi... | 6.503775 |
module three_input_or_gate (
input a,
b,
c,
output x,
y
);
assign x = a | b;
assign y = x | c;
endmodule
| 6.687992 |
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