code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Queue_3 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [1:0] io_enq_bits_resp,
input [4:0] io_enq_bits_id,
input io_enq_bits_user,
input io_deq_ready,
output io_deq_valid,
output [1:0] io_deq_bits_resp,
output [4:0] io_deq_bits_id,
output ... | 6.517764 |
module FlowThroughSerializer_1 (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [1:0] io_in_bits_client_xact_id,
input [2:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input [127:0] io_in_bits_data,
inp... | 6.711201 |
module FlowThroughSerializer_0 (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [1:0] io_in_bits_client_xact_id,
input [2:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input [127:0] io_in_bits_data,
inp... | 6.711201 |
module RecFNToRecFN (
input [32:0] io_in,
input [ 1:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire [4:0] T0;
wire invalidExc;
wire T1;
wire T2;
wire [55:0] outRawFloat_sig;
wire [55:0] T3;
wire [26:0] T4;
wire [26:0] T5;
wire [24:0] T6;
wire [22:... | 6.761906 |
module DivSqrtRecF64 (
input clk,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [1:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
o... | 6.793472 |
module DataArray_T9 (
input CLK,
input RST,
input init,
input [7:0] W0A,
input W0E,
input [127:0] W0I,
input [127:0] W0M,
input [7:0] R1A,
input R1E,
output [127:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 2; i = i + 64... | 6.622475 |
module MetadataArray_T6 (
input CLK,
input RST,
input init,
input [5:0] W0A,
input W0E,
input [87:0] W0I,
input [87:0] W0M,
input [5:0] R1A,
input R1E,
output [87:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 4; i = i + 2... | 6.901681 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] D_o;
reg A_sign;
reg B_sign;
reg add_sign;
localparam a_width = MAN+1+2; // width of sum after rounding (_su... | 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [EXP+MAN:0] D_o;
reg A_sign;
reg B_sign;
reg C_sign;
localparam a_width = MAN+1+2; // width of su... | 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [MAN+2:0] A_o;
reg [MAN+2:0] B_o;
reg [MAN+2:0] C_o;
reg [MAN+2:0] D_o;
reg A_sign;
reg B_sign;
reg ... | 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [EXP+MAN:0] D_o;
reg A_sign;
reg B_sign;
reg C_sign;
initial begin
clk = 1'b1;
A_i = 32'h0;
... | 6.608387 |
module
`timescale 1ns/1ps
module top;
reg clk;
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
localparam EXP = 8;
localparam MAN = 23;
initial begin
clk = 1'b1;
A = 32'h00000000;
B = 32'hbd7b54be;
#100
$display("[%t] : larger one of %h and %h is %h\n", $realtime, A, B, C);
$finis... | 7.853048 |
module
`timescale 1ns/1ps
module top;
reg clk;
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
localparam EXP = 8;
localparam MAN = 23;
initial begin
clk = 1'b1;
A = 32'h430260bb;
B = 32'hbd7b54be;
#100
$display("[%t] : %h mul %h is %h\n", $realtime, A, B, C);
$finish;
end
fp... | 7.853048 |
module
`timescale 1ns/1ps
module top;
reg clk;
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
localparam EXP = 8;
localparam MAN = 23;
reg [MAN:0] exp_sum; //[(MAN+3)*2-1:0]
initial begin
clk = 1'b1;
//A = 32'h3e6c074f;
//B = 32'h3f437ebe;
A = 32'h430260bb;
B = 32'hbd7b54be;
... | 7.853048 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 12;
reg clk;
reg sum_sign;
reg [MAN+4:0] sum_unsigned;
reg [EXP-1:0] sum_exp;
reg [EXP+MAN:0] sum_o;
localparam a_width = MAN+1+2; // width of sum after rounding (_sum)
// addr_width should be less than ... | 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [MAN+2:0] A_o;
reg [MAN+2:0] B_o;
reg [MAN+2:0] C_o;
reg [MAN+2:0] D_o;
reg A_sign;
reg B_sign;
reg ... | 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg A_sign;
reg B_sign;
reg C_sign;
reg [MAN+4:0] D_o;
reg D_sign;
initial begin
clk =... | 6.608387 |
module Queue_3 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [127:0] io_enq_bits_data,
input io_enq_bits_last,
input [15:0] io_enq_bits_strb,
input io_enq_bits_user,
input io_deq_ready,
output io_deq_valid,
output [127:0] io_deq_bits_data,
outpu... | 6.517764 |
module RRArbiter_0 (
input clk,
input reset,
output io_in_1_ready,
input io_in_1_valid,
input io_in_1_bits_rw,
input [11:0] io_in_1_bits_addr,
input [63:0] io_in_1_bits_data,
output io_in_0_ready,
input io_in_0_valid,
input io_in_0_bits_rw,
input [11:0] io_in_0_bits_addr,
... | 6.876771 |
module FlowThroughSerializer (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [1:0] io_in_bits_client_xact_id,
input [3:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input [127:0] io_in_bits_data,
input... | 6.711201 |
module RecFNToRecFN (
input [32:0] io_in,
input [ 1:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire [4:0] T0;
wire invalidExc;
wire T1;
wire T2;
wire [55:0] outRawFloat_sig;
wire [55:0] T3;
wire [26:0] T4;
wire [26:0] T5;
wire [24:0] T6;
wire [22:... | 6.761906 |
module DivSqrtRecF64 (
input clk,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [1:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
o... | 6.793472 |
module DataArray_T9 (
input CLK,
input RST,
input init,
input [7:0] W0A,
input W0E,
input [127:0] W0I,
input [127:0] W0M,
input [7:0] R1A,
input R1E,
output [127:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 2; i = i + 64... | 6.622475 |
module MetadataArray_tag_arr (
input CLK,
input RST,
input init,
input [5:0] W0A,
input W0E,
input [87:0] W0I,
input [87:0] W0M,
input [5:0] R1A,
input R1E,
output [87:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 4; i = ... | 6.901681 |
module HellaQueue_0 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [127:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [127:0] io_deq_bits_data
//output[4:0] io_count
);
wire fq_io_enq_ready;
wire fq_io_deq_valid;
wire [127:0] fq... | 6.761208 |
module FlowThroughSerializer (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [127:0] io_in_bits_data,
input [6:0] io_in_bits_client_xact_id,
input [2:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input... | 6.711201 |
module LockingArbiter_0 (
input clk,
input reset,
output io_in_1_ready,
input io_in_1_valid,
input [25:0] io_in_1_bits_addr_block,
input [6:0] io_in_1_bits_client_xact_id,
input [1:0] io_in_1_bits_addr_beat,
input [127:0] io_in_1_bits_data,
input [2:0] io_in_1_bits_r_type,
input ... | 8.44302 |
module divSqrtRecodedFloat64 (
input clk,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [1:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_ou... | 6.548765 |
module MetadataArray_T1 (
input CLK,
input RST,
input init,
input [5:0] W0A,
input W0E,
input [87:0] W0I,
input [87:0] W0M,
input [5:0] R1A,
input R1E,
output [87:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 4; i = i + 2... | 6.901681 |
module HackBox (
input [63:0] io_in_0,
input [63:0] io_in_1,
input [63:0] io_in_2,
output [63:0] io_out
);
assign out = in_0 + (in_1 * in_2);
endmodule
| 6.993909 |
module proc_control (
input wire clk,
input wire rst_n,
output reg on_3mul,
output reg on_align3,
output reg on_sum3,
output reg on_bias
);
localparam ON_MUL = 3'h1;
localparam ON_ALIGN = 3'h2;
localparam ON_SUM = 3'h3;
localparam ON_BIAS = 3'h4;
reg [2:0] _state;
reg [2:0] _... | 8.057958 |
module
`timescale 1ns/1ps
`define NULL 0
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] ker1;
reg [EXP+MAN:0] ker2;
reg [EXP+MAN:0] ker3;
reg [EXP+MAN:0] data1;
reg [EXP+MAN:0] data2;
reg [EXP+MAN:0] data3;
reg [EXP+MAN:0] bias;
reg [EXP+MAN:0] result;
reg ... | 6.608387 |
module proc_control (
input wire clk,
input wire rst_n,
output reg on_3mul,
output reg on_align3,
output reg on_sum3,
output reg on_bias
);
localparam ON_MUL = 3'h1;
localparam ON_ALIGN = 3'h2;
localparam ON_SUM = 3'h3;
localparam ON_BIAS = 3'h4;
reg [2:0] _state;
reg [2:0] _... | 8.057958 |
module prga_simple_buf (
input wire [0:0] C,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
Q <= D;
end
endmodule
| 7.13912 |
module prga_simple_bufr (
input wire [0:0] C,
input wire [0:0] R,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
if (R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.13912 |
module iob (
input wire [0:0] outpad
, output wire [0:0] inpad
, input wire [0:0] ipin
, output wire [0:0] opin
, output wire [0:0] oe
, input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [0:0] prog_... | 6.616918 |
module scanchain_delim (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [0:0] prog_we_o
, output reg [1 - 1:0] prog_dout
);
always @(posedge prog_clk) begin
if (prog_rst) be... | 7.198827 |
module scanchain_data_d2 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [2 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 2;
localparam C... | 7.770095 |
module scanchain_data_d1 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [1 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 1;
localparam C... | 7.770095 |
module sw4 (
input wire [3:0] i
, output reg [0:0] o
, input wire [0:0] prog_done
, input wire [2:0] prog_data
);
always @* begin
if (~prog_done) begin
o = 1'b0;
end else begin
o = 1'b0; // if ``prog_data == 0`` or ``prog_data`` out of bound, output 0
case (prog_data)
... | 6.587067 |
module scanchain_data_d3 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [3 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 3;
localparam C... | 7.770095 |
module iopad (
input wire [0:0] outpad
, output reg [0:0] inpad
, input wire [0:0] ipin
, output reg [0:0] opin
, output reg [0:0] oe
, input wire [0:0] prog_done // programming
, input wire [1:0] prog_data // mode:
// - 00: disabled
... | 7.272753 |
module scanchain_data_d4 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [4 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 4;
localparam C... | 7.770095 |
modules/top.v"
`timescale 1us/1ns
module top_tb ();
// 10 MHz clock
reg clk = 1;
always #0.05 clk = ~clk;
reg rst;
wire [1:0] r,g,b;
top_m top (
.clk(clk),
.rst(rst),
.r(r), .g(g), .b(b)
);
initial begin
$dumpfile( "dump.vcd" );
$dumpvars( 0, top );
//\\ =========================== \\//
rst = 1;
#1
... | 7.284158 |
module Top #(
parameter INSTRUCTION_FILE_NAME = "default_instr_file"
) (
clk,
rst
);
`include "Parameters.vh"
input clk;
input rst;
/* Signal wires between different modules */
// Between datapath and instruction memory
wire [XLEN - 1 : 0] PC;
wire [XLEN - 1 : 0] instruction;
// Between i... | 8.750164 |
module top0 (
input i_clk_sys50m,
input i_red,
output [6:0] o_num,
output [7:0] o_sel,
output o_sdram_clk,
inout [15:0] io_sdram_data,
output [1:0] o_sdram_ba,
output [12:0] o_sdram_addr,
output o_sdram_ras,
output o_sdram_cas,
output o_sdram_we,
output o_sdram_cke,
... | 6.685 |
module top (
input d,
clk,
output reg q
);
wire u;
wire s;
assign u = s;
assign u = d;
assign u = clk;
always @(posedge clk) q <= u;
endmodule
| 7.233807 |
module top10 #(
parameter DATA_WIDTH = 16,
NUM_WORDS = 16
) (
input clk,
input rst,
input enable,
input [DATA_WIDTH*NUM_WORDS-1:0] array_in,
output [DATA_WIDTH*10-1:0] array_out,
output [6*10-1:0] id_out,
output reg sorted
);
integer j, k, l, m;
// integer x;
// always @(*)b... | 6.604105 |
module Top2 (
Clk,
Reset,
v0_OUT,
v1_OUT,
PC_OUT,
MIN_OUT,
test1,
test2,
test3
);
input Clk, Reset;
wire [31:0] v0_A, v1_A, PCValue_A, MIN_A,
v0_B, v1_B, PCValue_B, MIN_B,
v0_C, v1_C, PCValue_C, MIN_C,
v0_D, v1_D, PCValue_D, MIN_D,
... | 6.629108 |
module Top3 (
Clk,
Reset,
out7,
en_out
);
input Clk, Reset;
wire Clk_f;
output [6:0] out7;
output [7:0] en_out;
wire [31:0] v1_final, v0_final;
ClkDiv clkdiv (
Clk,
Reset,
Clk_f
);
Top2 FourCoreSystem (
Clk_f,
Reset,
v0_final,
v1_final
);
... | 7.702056 |
module top4digit7seg (
input clk,
rst,
input [3:0] dig0,
dig1,
dig2,
dig3,
output [6:0] abcdefg,
output en0,
en1,
en2,
en3 //reg???
);
wire [1:0] sel;
wire nclk;
wire [3:0] ssmout;
//BE FAMILIAR WITH THE DATASHEET OF A 4 DIGIT 7-SEG LED BEFORE PROCEEDING//
SevenSe... | 7.057612 |
module topaudio (
input clock,
input miso,
output adconv,
output ready,
output sck,
output mosi,
output daccs,
output dacclr,
output spissb,
output sf_ce0,
output fpgainitb,
output ampcs,
output ampshdn
);
wire clockslow; //fredivider1
wire enablegain, enablead... | 7.355552 |
module topaudiotest;
// Inputs
reg clock;
reg miso;
// Outputs
wire adconv;
wire ready;
wire sck;
wire mosi;
wire daccs;
wire dacclr;
wire spissb;
wire sf_ce0;
wire fpgainitb;
wire ampcs;
wire ampshdn;
// Instantiate the Unit Under Test (UUT)
topaudio uut (
.clock(clock),
... | 7.695563 |
module TopAvoidObstacle (
input clk,
input nCR_Avoid,
input left, //
input right, //Ҽ
input Echo_Signal,
output Trig_Signal,
output [1:0] AvoidSignal
);
wire clk_1m;
wire clk_seg;
wire [19:0] dis; // زߵƽʱus
wire CLK_1s;
Divider50MHzAvoid A0 (
.CLK_50M(clk),
.nCLR(... | 6.678003 |
module TopBottom (
x1,
x2,
z1,
z2p,
aL,
zL,
b
);
input [1:0] x1, x2; //Pin
input [1:0] b; //1 digit of y
input [1:0] aL; //input of LSD
output [1:0] z1;
output z2p;
output [1:0] zL; //output of LSD
//---- MSD Slice -----------------------------------------------------... | 7.068883 |
module topControl (
input [6:0] opcode,
input [3:0] func,
output branch,
memRead,
memToReg,
memWrite,
ALUSrc,
regWrite,
output [3:0] operation
);
wire [1:0] ALUOp;
controlUnit cu (
opcode,
branch,
memRead,
memToReg,
memWrite,
ALUSrc,
re... | 8.29194 |
module topCost (
input clk,
input rst,
input set, //预置信号
input [2:0] initcost, //起步价
input [2:0] percost, //单价
input [2:0] addmail, //加费里程
input [15:0] distence,
output [6:0] seg0,
output [6:0] seg1,
output [6:0] seg2,
output [6:0] seg3
);
wire [15:0] fare;
//计费模块
... | 6.829222 |
module topcount (
input clk,
reset,
direction,
output reg seg_1,
seg_2,
seg_3,
seg_4,
seg_5,
seg_6,
seg_7,
seg_8,
seg_9,
seg_10,
seg_11,
seg_12,
seg_13,
seg_14,
seg_15,
seg_16,
output LOCK,
output [7:0] count3t,
output [3:0] count2t... | 6.583833 |
module TopCountWorkpieces (
input clk,
nCR,
detector,
output [3:0] Light,
output [6:0] seg
);
wire CLK_Light;
wire fall;
wire [15:0] det_counter;
Divider50MHz U0 (
.CLK_50M(clk),
.nCLR(nCR),
.CLK_1HzOut(CLK_Light)
);
defparam U0.N = 26, U0.CLK_Freq = 50000000, U0.OUT_F... | 7.506983 |
module topcpu (
input clk_in,
input reset,
output [7:0] o_seg,
output [7:0] o_sel,
input miso,
output cs,
output mosi,
output spiclk,
output initfinish,
output writefinish,
output readfinish,
/************************/
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,... | 7.267667 |
module mb8_top (
mx1,
my1,
CLK,
RST,
sum1,
carry1,
mx2,
my2
);
parameter WIDTH = 8;
input wire [WIDTH-1:0] mx1;
input wire [WIDTH-1:0] my1;
input wire CLK;
input wire RST;
output wire [(2*WIDTH)-1:0] sum1;
output wire [(2*WIDTH)-1:0] carry1;
output reg [WIDTH-1:0] mx2;
... | 6.835868 |
module TopDesign (
input clk,
input [2:0] PathDectSignal,
input En_Tracing,
input SpeedControl,
input nCR,
input detector,
input another,
input nCR_Avoid,
input Echo_Signal,
output [3:0] Led_Direction,
output Speed_Wheel_1,
Speed_Wheel_2,
output [1:0] Control_Wheel_1,... | 7.796766 |
module topedoMux (
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
sel,
result
);
input data0;
input data1;
input data2;
input data3;
input data4;
input data5;
input data6;
input data7;
input [2:0] sel;
output result;
wire [0:0] sub_wire0;
wire s... | 6.532598 |
module TopLayer (
rst,
CLK,
mem_addr,
dis_mode,
swi_halt,
swi_freq,
seg,
an
);
input rst;
input CLK;
input [3:0] mem_addr;
input [2:0] dis_mode;
input swi_halt;
input swi_freq;
output [7:0] seg; //߶ʾ
output [7:0] an; //Ƭѡź
wire clk, clk_dis;
wire [31:0] mem_dis;
/... | 6.720977 |
module toplayici_33 (
input [32:0] islec0_i,
input [32:0] islec1_i,
output [32:0] toplam_o
);
toplayici utt (
.islec0_i(islec0_i[32:1]),
.islec1_i(islec1_i[32:1]),
.carry_i (islec0_i[0] && islec1_i[0]),
.toplam_o({toplam_o[32:1]})
);
assign toplam_o[0] = islec0_i[0] ^ isle... | 6.893337 |
module TopLevelDec (
input start,
read,
clk,
rst,
output ready,
done,
output [6:0] out0,
out1,
out2,
out3
);
reg [17:0] q;
reg [ 2:0] usedw;
ExpAcc acc (
.done(done),
.start(start),
.clk(clk),
.rst(rst),
.read(read),
.ready(ready),
... | 7.118355 |
module TopLevelDesign (
input CLK,
input RST,
input [7:0] SWITCHES,
output IR_LED
);
//////////////////////////////////////////////////////////////////////////////////
//Interconnecting wires
//Processor Buses
wire [7:0] data_bus;
wire [7:0] addr_bus;
wire bus_we;
//ROM Buses
wire [7:... | 7.384458 |
module toplevelfinal (
input clk,
reset,
output [9:0] sprite_x,
output [8:0] sprite_y,
output [4:0] sprite_sel,
output sprite_attr,
sprite_pos,
sprite_vis,
bck_ch_active,
output font_ch_active,
font_clr,
font_en,
output [10:0] font_addr,
output [3:0] font_data,
... | 7.749115 |
module TopLevelHex (
input start,
read,
clk,
rst,
output ready,
done,
output [6:0] out0,
out1,
out2,
out3
);
reg [17:0] q;
ExpAcc acc (
.done(done),
.start(start),
.clk(clk),
.rst(rst),
.read(read),
.ready(ready),
.q(q)
);
HexDi... | 7.156546 |
module topLevelPiston (
CLOCK_50, // On Board 50 MHz
SW,
KEY, // On Board Keys
// The ports below are for the VGA output.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, ... | 8.743876 |
module TopLevelModule (
clk,
reset,
reset_check,
h_sync,
v_sync,
red,
blue,
green,
PS2_CLK,
PS2_DATA,
state,
crash_en,
car_on,
road_on
);
input clk;
input reset;
output reset_check;
output h_sync;
output v_sync;
output [3:0] red;
output [3:0] blue;
... | 7.42032 |
module game_state (
state_OBUF,
\FSM_sequential_state_reg[0]_0 ,
CLK
);
output [0:0] state_OBUF;
input \FSM_sequential_state_reg[0]_0 ;
input CLK;
wire CLK;
wire \FSM_sequential_state_reg[0]_0 ;
wire [0:0] state_OBUF;
(* FSM_ENCODED_STATES = "iSTATE:10,iSTATE0:01,iSTATE1:00,iSTATE2:11" *)
... | 7.12042 |
module: QuickSilverNEO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TopLevelTest;
// Inputs
reg clk;
// Outputs
wire [2:0] vgaRed;
wire [2:0] vgaGreen;
wire [1:0] vgaBlue;... | 7.435384 |
module topLevelVendingMachine (
input c,
u, // Botao 1, 2,
input cima,
baixo,
enter, // Botao 3,4,5
input clock,
reset, // 50 MHz Clock
output [9:0] led, // Led
output sucesso, // Parametro para afirmar se funcionou ou nao
output pizza,
burguer,
torta,
soda ... | 6.833642 |
module toplevel_apo_5_nodes (
clk,
out_data,
sw_on,
sw_sel_data,
sw_sel_router,
key_inc,
key_dec,
hex_data,
hex_router
);
input clk;
input sw_on;
input sw_sel_data;
input sw_sel_router;
input key_inc;
input key_dec;
output wire [127:0] out_data;
output wire [6:0] h... | 7.129722 |
module toplevel_apo_9_nodes (
clk,
out_data,
sw_on,
sw_sel_data,
sw_sel_router,
key_inc,
key_dec,
hex_data,
hex_router
);
input clk;
input sw_on;
input sw_sel_data;
input sw_sel_router;
input key_inc;
input key_dec;
output wire [127:0] out_data;
output wire [6:0] h... | 7.129722 |
module integrate_system (
input clk,
rst,
adjust,
end_cal,
start,
input [3:0] n,
input [15:0] InFreq,
input [15:0] frac,
input [1:0] ui,
output valid,
done
);
fer_mul_toplevel fre (
clk,
rst,
adjust,
end_cal,
n,
InFreq,
valid,
... | 6.973707 |
module integrateTB ();
reg clk, rst, adjust, end_cal, start;
reg [ 3:0] n;
reg [15:0] InFreq;
reg [15:0] frac;
reg [ 1:0] ui;
wire valid, done;
integrate_system cpu (
clk,
rst,
adjust,
end_cal,
start,
n,
InFreq,
frac,
ui,
valid,
done
);... | 7.443204 |
module TopLevel_evt_sync #(
parameter SIZE = 65,
parameter DATA_WIDTH = 65,
parameter FIFO_DEPTH = 6,
parameter TOTAL_CLUSTERS = 17,
parameter TOTAL_OUTPUT_BOARDS = 4,
parameter BOARD_ID = 0
) (
input wire clock,
input wire reset_n,
input wire [SIZE-1:0] input_data[TOTAL_CLUSTERS],
... | 6.652922 |
module cpu_test ();
reg clk;
reg reset;
// Clock generation
initial clk = 0;
always #10 clk = !clk;
// Instantiate CPU
dsp dsp (.clk(clk));
initial begin
$readmemb("./assemble/machine_code_short.dat", dsp.InstrMem.mem, 0);
$readmemb("./assemble/data_mem.dat", dsp.DataMem.mem, 0);
$disp... | 7.39269 |
module toplevel_pl (
output reg [7:0] JA,
output reg [7:0] JB,
inout [7:0] JC,
inout [7:0] JD,
output reg [7:0] led,
input [7:0] sw,
input BTNL,
input BTNR,
input BTNU,
input BTND,
input BTNC,
input GCLK
);
wire clk;
clk_div cdiv (
.clk_in(GCLK),
.clk_out... | 8.02994 |
module toplevel_primerLoopback #(
parameter LEN_DATA_BLOCK = 64,
parameter LEN_CTRL_BLOCK = 8,
parameter LEN_CODED_BLOCK = 66,
parameter TX_NMODULES = 2,
parameter RX_NMODULES = 2
) (
input i_clock,
input i_reset,
input i_enable_frameGenerator,
input i_enable_frameC... | 7.781586 |
module cpu_test ();
reg clk;
reg reset;
// Clock generation
initial clk = 0;
always #10 clk = !clk;
// Instantiate CPU
dsp dsp (.clk(clk));
initial begin
$readmemb("./assemble/machine_code_full.dat", dsp.InstrMem.mem, 0);
$readmemb("./assemble/data_mem.dat", dsp.DataMem.mem, 0);
$displ... | 7.39269 |
module TopLevel_sim ();
reg clkin, btnU, btnD, btnL, btnR;
reg [15:0] sw;
wire Hsync, Vsync;
wire [3:0] vgaRed, vgaBlue, vgaGreen;
TopLevel UUT (
.clkin(clkin),
.btnU(btnU),
.btnD(btnD),
.btnL(btnL),
.btnR(btnR),
.sw(sw),
.Hsync(Hsync),
.Vsync(Vsync),
.v... | 6.553764 |
module TopLevel_sw_switcher #(
parameter SIZE = 65,
parameter DATA_WIDTH = 65,
parameter FIFO_DEPTH = 6,
parameter TOTAL_INPUTS = 2,
parameter TOTAL_OUTPUTS = 2
) (
input wire clock,
input wire reset_n,
input wire [SIZE-1:0] input_data[TOTAL_INPUTS],
output wire [SIZE-1:0] output_dat... | 9.244739 |
module TopLevel_tb ();
reg clk;
reg rst;
TopLevel #(
.ROM_ADDR (10),
.DATA_BITS(32),
.MEM_ADDR (10),
.PC_ADDR (10)
) //Rom的地?线长、PC的数据位?
toplevel (
.clk(clk),
.btnL(rst),
.seg(), // segment driver signals, ordered { a, b, ..., g, dp }
.dp(),
.an() /... | 6.705295 |
module toplevel_test;
// Inputs
// UART
reg RST = 1;
reg CLK = 0;
reg RXD = 1;
//CAMERA
reg PIXCLK = 1;
reg FRAME_VALID = 0;
reg LINE_VALID = 0;
reg [9:0] DATA_IN = 0;
// Outputs
wire TXD;
wire CAM_SYSCLK = CLK;
// Instantiate the Unit Under Test (UUT)
topmodule #(2, 3) uut (
.RST... | 7.105914 |
module TopLevel_tb ();
parameter ADDRESS_SIZE = 32;
parameter TRAINING_DATA_SIZE = 4100000;
parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
parameter GHL = 22;
parameter WS = 5;
parameter LS = 128;
parameter LS_INDEX_SIZE = $clog2(LS);
reg Clk, Rst;
wire BranchPrediction;
wire Predict... | 6.705295 |
module topLevel_wrapper (
CLK100MHZ,
ck_io,
ck_rst,
led,
trigger,
uart_rxd_out,
uart_txd_in
);
input CLK100MHZ;
input [3:0] ck_io;
input ck_rst;
output [3:0] led;
input trigger;
output uart_rxd_out;
input uart_txd_in;
wire CLK100MHZ;
wire [3:0] ck_io;
wire ck_rst;
wire... | 8.516765 |
module Toplv (
input en,
input clk,
input rst,
output [7:0] AN,
output [1:7] seg
);
wire [25:0] dispSel;
wire [ 3:0] wmod6;
wire [ 3:0] wmod10;
wire [ 3:0] wmux;
progcnt #(
.N (26),
.MAX(67108863)
) main (
.clk(clk),
.rst(rst),
.en(1),
.count(dispSel)... | 6.858588 |
module toplevel_STACK (
input clk,
rst
);
wire [2:0] opcode, ALUOP;
wire PCSrc, pc_write, pc_write_con, mem_sel, Mem_read, Mem_write,
IR_write, stack_sel, load_A, A_sel, B_sel, push, pop, tos, ALUZero;
datapath dp (
clk,
rst,
PCSrc,
pc_write,
pc_write_con,
ALUZero,... | 6.893419 |
module AtomALU (
input [63:0] io_src1,
input [63:0] io_src2,
input [ 6:0] io_func,
input io_isWordOp,
output [63:0] io_result
);
wire isAdderSub = ~io_func[6]; // @[LSU.scala 184:20]
wire [63:0] _T_2 = isAdderSub ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
wire [63:0... | 7.306711 |
module MOU (
input io_in_valid,
input [ 6:0] io_in_bits_func,
input [38:0] io_cfIn_pc,
output [38:0] io_redirect_target,
output io_redirect_valid,
output flushICache_0,
output flushTLB_0
);
wire _T_2 = io_in_bits_func == 7'h1; // @[MOU.scala 52:36]
wire fl... | 7.890495 |
module LockingArbiter (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [31:0] io_in_0_bits_addr,
input [ 3:0] io_in_0_bits_cmd,
input [ 7:0] io_in_0_bits_wmask,
input [63:0] io_in_0_bits_wdata,
output io_in_1_ready... | 8.44302 |
module SimpleBusAddressMapper (
output io_in_req_ready,
input io_in_req_valid,
input [31:0] io_in_req_bits_addr,
input [ 3:0] io_in_req_bits_cmd,
input [63:0] io_in_req_bits_wdata,
output io_in_resp_valid,
output [ 3:0] io_in_resp_bits_cmd,
output [63:0] io_in_re... | 6.846243 |
module of the design. It instantiates the
// 'gpif_interface' in it.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Include File
`include "params.v"
module topmod
(
i... | 8.52834 |
module jtrclr (
input clk,
button,
output button_n
);
reg [3:0] cnt;
always @(posedge clk) begin
if (button == 1'b0) cnt <= 4'h0;
else if (cnt < 4'h8) cnt <= cnt + 4'b1;
end
assign button_n = cnt[3];
endmodule
| 6.815102 |
module signal_edge (
input clk,
button,
output button_edge
);
reg button_r1, button_r2;
always @(posedge clk) begin
button_r1 <= button;
end
always @(posedge clk) begin
button_r2 <= button_r1;
end
assign button_edge = button_r1 & (~button_r2);
endmodule
| 6.590149 |
module for VGA and CPU implementation
// Feature CPU, Timer and VGA blocks
// Instruction in CPU modify colour register in VGA_Wrapper module
// once a second via an interrupt from the Timer
//
// Dependencies: input clock CLK of 50MHz
// Modules: RAM, ROM, CPU, Timer and VGA_Wrapp... | 8.679063 |
module: TopModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TopModule1_tb;
// Inputs
reg CLK;
reg RESET;
reg [1:0] IQR_RAISE;
// Outputs
wire [1:0] IRQ_ACK;
// Instanti... | 7.864778 |
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