code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TopmodulePS2 #(
parameter clk_freq = 50000000
) (
input sys_rst,
input sys_clk,
input [7:0] csr_di, //datainput
input csr_we, //control status register write enable
inout ps2_clk,
inout ps2_data,
output irq,
output rx_avail,
output [7:0] kcode,
output tx_busy,
... | 7.401869 |
module TopModuleS (
CLOCK_50,
VGA_VS,
VGA_HS,
VGA_CLK,
COLOR,
led1,
swa,
swb,
swc,
swd,
swe,
swf,
swg
);
input CLOCK_50;
output reg [7:0] led1;
output VGA_HS, VGA_VS;
output reg VGA_CLK = 0;
output wire [7:0] COLOR;
input swa, swb, swc, swd, swe, swf, swg... | 6.690679 |
module ModWithNestedClk (
input reset,
input io_inClk,
output io_bbOutClk_0,
output io_bbOutClk_1,
output io_bbOutClk_2,
output io_clkDivOut_0,
output io_clkDivOut_1,
output io_clkDivOut_2
);
wire bb_outClk_0; // @[ClkGenSpec.scala 63:18]
wire bb_outClk_1; // @[ClkGenSpec.scala 6... | 6.895733 |
module ModWithNestedClk_1 (
input reset,
input io_inClk,
output io_bbOutClk_0,
output io_bbOutClk_1,
output io_bbOutClk_2,
output io_clkDivOut_0,
output io_clkDivOut_1,
output io_clkDivOut_2
);
wire bb_outClk_0; // @[ClkGenSpec.scala 63:18]
wire bb_outClk_1; // @[ClkGenSpec.scala... | 6.895733 |
module TopModule_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire instruction_bit;
wire alu_result_bit;
wire jump_offset_bit;
wire pc_bit;
// Instantiate the Unit Under Test (UUT)
TopModule uut (
.clk(clk),
.rst(rst),
.instruction_bit(instruction_bit),
.alu_result_bit(alu... | 8.900291 |
module top (
input clk,
reset,
output [31:0] writedata,
adr,
output memwrite
);
wire [31:0] readdata;
// microprocessor (control & datapath)
mips mips (
clk,
reset,
adr,
writedata,
memwrite,
readdata
);
// memory
mem mem (
clk,... | 7.233807 |
module TopMultiplier (
x_in,
y_in,
result_out
);
input [15:0] x_in, y_in;
output [31:0] result_out;
// internal connections
wire [15:0] pp0, pp1, pp2, pp3, pp4, pp5, pp6, pp7, pp8, pp9, pp10, pp11, pp12, pp13, pp14, pp15;
wire [31:0] opa, opb;
wire [15:0] sign;
//wire [15: 0] sign_compensate... | 7.182111 |
module topnbit_verification (
result,
clk,
c_in,
a,
b,
ALOP
);
parameter W = 32;
input [2:0] ALOP;
input clk;
input [W-1:0] a, b;
input c_in;
output [W:0] result;
wire [W-1:0] sum_to_reg;
assign {result} = //verifies each function
(ALOP == 3'b000) ? {a}:
(ALOP == 3'b... | 7.745191 |
module VizModC ( // @[:@3.2]
input [15:0] io_in, // @[:@6.4]
output [15:0] io_out // @[:@6.4]
);
assign io_out = io_in;
endmodule
| 9.030593 |
module VizModA ( // @[:@13.2]
input [31:0] io_in, // @[:@16.4]
output [15:0] io_out // @[:@16.4]
);
wire [15:0] modC_io_in; // @[VisualizerSpec.scala 40:20:@21.4]
wire [15:0] modC_io_out; // @[VisualizerSpec.scala 40:20:@21.4]
VizModC modC ( // @[VisualizerSpec.scala 40:20:@21.4]
.io_in (modC... | 8.095252 |
module VizModC (
input [15:0] io_in,
output [15:0] io_out
);
assign io_out = io_in; // @[VisualizerSpec.scala 25:10]
endmodule
| 8.61491 |
module VizModA (
input [31:0] io_in,
output [15:0] io_out
);
wire [15:0] modC_io_in; // @[VisualizerSpec.scala 40:20]
wire [15:0] modC_io_out; // @[VisualizerSpec.scala 40:20]
VizModC modC ( // @[VisualizerSpec.scala 40:20]
.io_in (modC_io_in),
.io_out(modC_io_out)
);
assign io_out = m... | 8.589487 |
module topology_module #(
parameter PORT_SIZE = 37 + 2,
parameter PORTS_NUM = 4,
parameter NODES_NUM = 2,
`ifdef MESH_2D
parameter H_SIZE = 2
`else
`ifdef CIRCULANT_2
parameter S0 = 1,
parameter S1 = 2
`else
`ifdef TORUS
parameter H_SIZE = 2
`endif // TORUS
`endif // CIRCULANT_2
`endif //... | 7.862427 |
module toppest (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
input wire [ 3:0] sw, // four switches, [0] right [1] left [2] down [3] up
output wire VGA_HS_O, // horizontal sync output
output wire VGA_... | 7.883028 |
module PC_PCArthmetic (
clk,
startingPC,
address,
signExtend,
unconditionalBranchFlag,
branchFlag,
zeroFlag
);
input clk;
input [31:0] signExtend; //sign extended insturction
input unconditionalBranchFlag; //flag from controller
input branchFlag; //flag from controller
input ze... | 7.379809 |
module instructionCache (
output reg [31:0] data,
output reg missFlag,
input [31:0] PC,
input [31:0] inputData,
input writeData
); //inputData and writeData would be used if we had an imperfect cache that would go to a lower level and get more data to load into this iCache. Here we include but ign... | 6.897004 |
module ALU (
input1,
input2,
result,
zero,
ALUControl
);
input [31:0] input1, input2;
input [3:0] ALUControl;
output reg [31:0] result;
output reg zero;
always @(input1, input2) begin
case (ALUControl)
//CBZ
4'b0111: begin
if (input1 == 0) begin
resul... | 7.960621 |
module multiplexer64_32 (
option1,
option2,
out,
select
);
input [31:0] option1, option2;
input select;
output reg [31:0] out;
always @(select, option1, option2) begin
if (select) begin
out = option2;
end else begin
out = option1;
end
end
endmodule
| 7.246896 |
module fetchDecodeReg (
input enable,
input [31:0] thisPCAddressIN,
input [31:0] in,
output reg [31:0] out,
output reg [31:0] thisPCAddressOUT
);
always @(enable) begin
if (enable) begin
out = in;
end
end
endmodule
| 7.450352 |
module DecodeExecuteReg (
input enable,
input [31:0] i1,
input [31:0] i2,
input [31:0] i3,
input i4,
input i5,
input i6,
input i7,
input [4:0] i8,
output reg [31:0] o1,
output reg [31:0] o2,
output reg [31:0] o3,
output reg o4,
output reg o5,
output reg o6,
... | 6.856126 |
module ExecuteMemoryReg (
input enable,
input [31:0] ALUresultIN,
input [31:0] readdata2IN,
output reg [31:0] ALUresultOUT,
output reg [31:0] readdata2OUT,
input memWriteIN,
output reg memWriteOUT,
input memToRegIN,
output reg memToRegOUT,
input [4:0] writeRegIN,
output reg [... | 7.836619 |
module MemoryWriteBackReg (
input enable,
input [31:0] readDataIN,
output reg [31:0] readDataOUT,
input [31:0] aluResultIN,
output reg [31:0] aluResultOUT,
input [4:0] destinationRegIN,
output reg [4:0] destinationRegOUT,
input memToRegIN,
output reg memToRegOUT,
input [4:0] writ... | 7.077478 |
module topPlaca (
input CLK_28,
input [17:0] SW,
input [3:0] KEY,
output [17:0] LEDR,
output [7:0] LEDG,
output [7:0] HEX0_D,
output [7:0] HEX1_D,
output [7:0] HEX2_D,
output [7:0] HEX3_D,
output [7:0] HEX4_D,
output [7:0] HEX5_D,
output [7:0] HEX6_D,
output [7:0] HEX... | 6.873084 |
module top (
input extClk,
rst,
output [7:0] port
);
// Wires and regs
wire invClk;
wire clk;
wire hlt;
wire [9:0] instAddr;
wire [40:0] ctrlUnitInstIn;
wire [2:0] waddr, raddr1, raddr2;
wire [3:0] aluOpSel;
wire sto;
wire [31:0] imm;
wire [31:0] db1, db2;
wire [31:0] aluRes;
reg ... | 7.233807 |
module RAM_IN (
pix_val,
indx,
wren
);
input [9:0] indx;
output [15:0] pix_val;
output reg wren;
reg [15:0] pix_val;
reg [15:0] in_ram [839:0];
always @(indx) begin
pix_val = in_ram[indx];
wren = pix_val[0];
end
initial begin
$readmemb("EvilSnowman.txt", in_ram);
end
endm... | 6.865802 |
module toprobertsons (
input clk,
reset,
input [ 7:0] multiplier, // 8-bit data input to multiplier unit
input [ 7:0] multiplicand, // 8-bit data input to multiplier unit
output [15:0] product, // 16-bit data output of multiplier unit
output done // flag to s... | 6.8185 |
module tops (
input wire clk,
rst,
output wire jump,
branch,
alusrc,
memwrite,
regwrite,
regdst,
memtoreg,
output [2:0] alu_control,
output wire [6:0] seg,
output wire [7:0] ans
);
wire [31:0] pcaddr;
integer cnt; //count
reg clk_1hz;
always @(posedge clk) begi... | 6.611875 |
module TopSchematic2(
input_DECa,
input_DECb,
input_DECc,
input_FAa,
input_FAb,
input_FAc,
input_FSa,
input_FSb,
input_FSc,
input_HAa,
input_HAb,
input_COUNTclk,
input_COUNTrst,
input_PISOclk,
input_SIPO,
input_SIPOclk,
input_clkin,
input_BCD,
input_ENC,
input_PENC,
input_PISO,
output_FAs,
output... | 7.29016 |
module topsd (
input clk,
input reset,
input sd_miso,
output sd_cs,
output sd_mosi,
output sd_clk,
// output led,
// output [7:0]o_seg,
// output [7:0]o_sel,
output init_done,
output write_finish,
output read_finish,
input [8:0] raddr,
output [7:0] r... | 6.726821 |
module TopSDD (
input clk,
input rst
);
reg [ 7:0] oled_x_dc;
reg [ 7:0] oled_y_data;
reg [15:0] oled_rgb;
reg oled_strobe;
reg oled_setpixel_raw8tx;
wire oled_cs;
wire oled_mosi;
wire oled_sck;
wire oled_dc;
wire oled_rst;
wire ... | 7.135786 |
module topServo (
input clk_i,
output reg srv_o
);
reg reset;
rst_gen rst_inst (
.clk_i(clk_i),
.rst_i(1'b0),
.rst_o(reset)
);
SimpleServo sso (
.clk_i(clk_i),
.rst_i(reset),
.en_i(1'b1),
.position_i(8'hFF),
.srv_o(srv_o)
);
endmodule
| 6.837843 |
module topset (
clk,
rst,
start,
Done,
SEG,
AN
);
input clk, rst, start;
output Done;
output [7:0] SEG;
output [7:0] AN;
wire clk_N1, clk_N2;
wire [31:0] sum_out;
wire ld_sum, ld_next;
wire sum_sel, next_sel;
wire a_sel;
wire next_zero;
divider Divider1 (
.clk(clk),... | 7.127837 |
module TopStateMachine (
input clk,
input btnUDLR,
input btnC,
input WinDetect,
input LossDetect,
output reset,
output btnCenable,
output btnUDLRenable,
output TimerEnable,
output flashSlug,
output flashBorder,
output [3:0] state
);
wire [3:0] Q;
wire [3:0] D;
Top... | 6.500673 |
module TopStateMachineLogic (
input clk,
input btnUDLR,
input btnC,
input WinDetect,
input LossDetect,
input [3:0] Q,
output reset,
output btnCenable,
output btnUDLRenable,
output TimerEnable,
output flashSlug,
output flashBorder,
output [3:0] D
);
assign D[0] = (... | 6.500673 |
module TopSystem(
input clk
,input PS2Clk
,input PS2Data
,output Hsync
,output Vsync
,output [3:0] vgaRed
,output [3:0] vgaGreen
,output [3:0] vgaBlue
,output [6:0] seg
,output [3:0] an
,output dp
);
wire [15:0] key;
/*--Keyboard--*/
kb_top keyboard_handl... | 7.655706 |
module toptb ();
reg HCLK;
reg HRESETn = 0;
wire [31:0] pwdata, prdata, paddr;
wire [2:0] psel;
wire pwrite, penable;
wire [31:0] pwdatao, prdatao, paddro;
wire [2:0] pselo;
wire pwriteo, penableo;
wire [1:0] Hresp;
wire hwrite;
parameter cycle = 10;
ahbmaster MASTER (
.HCLK(HCLK),
... | 6.637427 |
module topteset ();
reg clk_p;
reg clk_n;
// reg en;
reg start;
reg stop;
reg enable;
reg reset;
// reg t;
wire [39:0] TDC_out;
wire valid;
wire out;
integer f, j;
real i;
TOP test (
.clk_p(clk_p),
.clk_n(clk_n),
.start(start),
.stop(stop),
.reset_butt... | 6.549927 |
module TopTracing (
input clk,
input SpeedControl,
input En_Tracing,
input [2:0] PathDectSignal,
input nCR_Avoid,
input [1:0] AvoidSignal,
output [3:0] Led_Direction,
output Speed_Wheel_1,
Speed_Wheel_2,
output [1:0] Control_Wheel_1,
output [1:0] Control_Wheel_2
);
PWM Tra... | 6.502608 |
module topUnit (
input clk,
input rst
);
wire [7:0] instrCode, pcIn, pcOut, immOut, pc_EX_WB, immOut_EX_WB;
wire branch, branch_EX_WB, branch_ID_EX;
wire [7:0] pc_ID_EX;
wire [7:0] jmpAddr;
wire flush;
assign flush = branch;
assign pcIn = branch ? (jmpAddr) : (pcOut + 1);
// assign pcIn = ... | 7.501513 |
module PC_PCArthmetic (
clk,
startingPC,
address,
signExtend,
unconditionalBranchFlag,
branchFlag,
zeroFlag
);
input clk;
input [31:0] signExtend; //sign extended insturction
input unconditionalBranchFlag; //flag from controller
input branchFlag; //flag from controller
input ze... | 7.379809 |
module instructionCache (
output reg [31:0] data,
output reg missFlag,
input [31:0] PC,
input [31:0] inputData,
input writeData
); //inputData and writeData would be used if we had an imperfect cache that would go to a lower level and get more data to load into this iCache. Here we include but ign... | 6.897004 |
module ALU (
input1,
input2,
result,
zero,
ALUControl
);
input [31:0] input1, input2;
input [3:0] ALUControl;
output reg [31:0] result;
output reg zero;
always @(input1, input2) begin
case (ALUControl)
//CBZ
4'b0111: begin
if (input1 == 0) begin
resul... | 7.960621 |
module multiplexer64_32 (
option1,
option2,
out,
select
);
input [31:0] option1, option2;
input select;
output reg [31:0] out;
always @(select, option1, option2) begin
if (select) begin
out = option2;
end else begin
out = option1;
end
end
endmodule
| 7.246896 |
module TopWrapper (
// inputs
input CLK,
input RESET,
input [7:0] SWITCHES,
//inouts
inout CLK_MOUSE,
inout DATA_MOUSE,
//outputs
output [7:0] StatusLED,
output [3:0] SEG_SELECT,
output [7:0] DEC_OUT,
output [7:0] COLOUR_OUT,
output HS_OUT,
output VS_OUT,
... | 6.717782 |
module mux (
sel,
res
);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res) begin
case (sel)
3'b000: res = 8'b00000001;
3'b001: res = 8'b00000010;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00010000;
3'b101: r... | 7.856429 |
module top_1000 (
input clk,
input rst_n,
input [7:0] data_in,
output [3:0] decision,
output finish
);
wire signed [11:0] conv_out_1, conv_out_2, conv_out_3;
wire signed [11:0] conv2_out_1, conv2_out_2, conv2_out_3;
wire signed [11:0] max_value_1, max_value_2, max_value_3;
wire signed [11:... | 6.737425 |
module top8_1step_CLA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
process... | 8.479229 |
module top8_1step_RCA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
process... | 8.090952 |
module top8_1step_CSelA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
proce... | 7.915499 |
module top8_1step_CSkipA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
proc... | 7.915499 |
module top8_1step_KSA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
process... | 7.797858 |
module top8_1step_CLA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P... | 8.479229 |
module top8_1step_RCA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P... | 8.090952 |
module top8_1step_CSelA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
... | 7.915499 |
module top8_1step_CSkipA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
... | 7.915499 |
module top8_1step_KSA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P... | 7.797858 |
module top16_1step_CLA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 6.897723 |
module top16_1step_RCA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 7.289314 |
module top16_1step_CSelA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
... | 6.897723 |
module top16_1step_CSkipA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
... | 6.897723 |
module top16_1step_KSA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 6.855856 |
module top16_1step_CLA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 6.897723 |
module top16_1step_RCA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.289314 |
module top16_1step_CSelA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 6.897723 |
module top16_1step_CSkipA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 6.897723 |
module top16_1step_KSA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 6.855856 |
module top (
input [7:0] i,
output o
);
always @*
case (i[6:3])
4: o <= i[0];
3: o <= i[2];
7: o <= i[3];
default: o <= 1'b0;
endcase
endmodule
| 7.233807 |
module Top_2048 (
input wire clk,
input wire PS2KeyboardClk,
input wire PS2KeyboardData,
input wire [4:0] btn,
output wire Hsync,
output wire Vsync,
output wire [2:0] vgaRed,
output wire [2:0] vgaGreen,
output wire [2:0] vgaBlue
);
wire clk25;
wire [7:0] data;
wire win;
wire... | 7.877243 |
module top8_2step_CLA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
process... | 8.828885 |
module top8_2step_RCA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
process... | 8.164733 |
module top8_2step_CSelA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
proce... | 8.199148 |
module top8_2step_CSkipA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
proc... | 8.199148 |
module top8_2step_KSA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
process... | 7.841116 |
module top8_2step_CLA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P... | 8.828885 |
module top8_2step_RCA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P... | 8.164733 |
module top8_2step_CSelA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
... | 8.199148 |
module top8_2step_CSkipA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
... | 8.199148 |
module top8_2step_KSA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P... | 7.841116 |
module top16_2step_CLA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 7.320932 |
module top16_2step_RCA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 7.496826 |
module top16_2step_CSelA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
... | 7.320932 |
module top16_2step_CSkipA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
... | 7.320932 |
module top16_2step_KSA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 6.952091 |
module top16_2step_CLA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.320932 |
module top16_2step_RCA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.496826 |
module top16_2step_CSelA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.320932 |
module top16_2step_CSkipA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.320932 |
module top16_2step_KSA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 6.952091 |
module mux (
sel,
res
);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel) begin
case (sel)
3'b000: res = 8'b00000001;
// unused decoder output
3'b001: res = 8'bxxxxxxxx;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00... | 7.856429 |
module top16_3step_CLA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 7.41128 |
module top16_3step_RCA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 7.817139 |
module top16_3step_CSelA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
... | 7.41128 |
module top16_3step_CSkipA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
... | 7.41128 |
module top16_3step_KSA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
pr... | 7.122312 |
module top16_3step_CLA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.41128 |
module top16_3step_RCA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.817139 |
module top16_3step_CSelA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.41128 |
module top16_3step_CSkipA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.41128 |
module top16_3step_KSA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
... | 7.122312 |
module mux (
sel,
res
);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res) begin
case (sel)
3'b000: res = 8'b00000001;
3'b001: res = 8'b00000010;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00010000;
3'b101: r... | 7.856429 |
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