code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module vstore_data_translator (
write_data, // data in least significant position
d_address,
store_size, // 0-byte, 1-16bits, 2-32bits, 3-64bits
d_byteena,
d_writedataout
); // shifted data to coincide with address
parameter WIDTH = 32;
input [WIDTH-1:0] write_data;
input [1:0] d_address;
... | 9.156778 |
module dpram1_26_67108864_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteen_a,
byteen_b,
out_a,
out_b
);
// parameter AWIDTH=10;
// parameter NUM_WORDS=1024;
// parameter DWIDTH=32;
// parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input ... | 6.955389 |
module vlane_barrelshifter_16_4(clk, resetn,
opB, sa,
op,
result);
//parameter 16=32;
//parameter 4=5;
//Shifts the first 2 bits in one cycle, the rest in the next cycle
//parameter (4-2)=4-2;
input clk;
input resetn;
input [16-1:0] opB;
input [4-1:0] sa; ... | 7.537708 |
module vregfile_base_32_16_4 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input [4-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input a_en, c_we;
ram_wrapper_4_16_32 reg_file1 (
... | 7.008004 |
module bfloat_mult_16 (
input clk,
input resetn,
input en,
input stall,
input [16-1:0] a,
input [16-1:0] b,
output reg [16-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a * b;
end
endmodule
| 6.919654 |
module activation_16 (
input clk,
input resetn,
input en,
input stall,
input [16-1:0] a,
output reg [16-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en)
if (a > 0) out <= a;
else out <= 0;
end
endmodule
| 7.789715 |
module PDO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.68925 |
module PDO12CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.566034 |
module PDO24CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.504196 |
module PRO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.516191 |
module PRT24DGZ (
I,
OEN,
PAD
);
input I, OEN;
output PAD;
bufif0 (PAD, I, OEN);
always @(PAD) begin
if (!$test$plusargs("bus_conflict_off"))
if ($countdrivers(PAD) && (PAD === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime);
end
specify
(I => PAD) = (0, 0);
(OEN => PAD)... | 6.709022 |
module PRO08CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.516191 |
module PRT24DGZ (
I,
OEN,
PAD
);
input I;
input OEN;
output PAD;
endmodule
| 6.709022 |
module PDO08CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.68925 |
module PDO12CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.566034 |
module PDO24CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.504196 |
module PDO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.68925 |
module PDO12CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.566034 |
module PDO24CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.504196 |
module PRO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.516191 |
module PRT24DGZ (
I,
OEN,
PAD
);
input I, OEN;
output PAD;
bufif0 (PAD, I, OEN);
always @(PAD) begin
if (!$test$plusargs("bus_conflict_off"))
if ($countdrivers(PAD) && (PAD === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime);
end
specify
(I => PAD) = (0, 0);
(OEN => PAD)... | 6.709022 |
module tp_lpf_heavy (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0041276697, 0.0041... | 7.215321 |
module tp_lpf_light (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.017174022, 0.01717... | 7.237937 |
module tp_lpf_medium (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0053024160, 0.005... | 7.013674 |
module tq_dequant2x2_dc (
qpmod6_i,
qpdiv6_i,
scale00_i,
scale01_i,
scale10_i,
scale11_i,
coeff00_o,
coeff01_o,
coeff10_o,
coeff11_o
);
parameter IN_WIDTH = 15;
parameter OUT_WIDTH = 15;
input [2:0] qpmod6_i;
input [3:0] qpdiv6_i;
input signed [IN_WIDTH-1:0] scale0... | 6.937702 |
module tq_quant2x2_dc (
qpmod6_i,
qpdiv6_i,
intra,
coeff00_i,
coeff01_i,
coeff10_i,
coeff11_i,
scale00_o,
scale01_o,
scale10_o,
scale11_o
);
parameter IN_WIDTH = 15;
parameter OUT_WIDTH = 15;
input [2:0] qpmod6_i;
input [3:0] qpdiv6_i;
input intra;
input [IN_... | 7.081817 |
module tq_ram_sp_32x16 (
data_o,
clk,
cen_i, // low active
wen_i, // low active
addr_i,
data_i
);
//--- input/output ------------------------------------------------
input clk;
input cen_i;
input wen_i;
input [5 -1 : 0] addr_i;
input [16-1 : 0] data_i;
output [16-1 : 0] data_o;
... | 7.218486 |
module JK (
output reg Q,
output wire nQ,
input wire J,
input wire K,
input wire C
);
initial Q = 0;
not (nQ, Q);
always @(negedge C)
case ({
J, K
})
2'b01: Q = 0;
2'b10: Q = 1;
2'b11: Q = ~Q;
endcase
endmodule
| 8.11998 |
module CAMBIO (
output wire [3:0] Q,
input wire [3:0] I
);
wire [3:0] nI;
wire aQ2_1, aQ2_2, aQ2_3;
wire aQ1_1, aQ1_2, aQ1_3, aQ1_4;
wire aQ0_1, aQ0_2, aQ0_3;
not n4 (nI[0], I[0]);
not n5 (nI[1], I[1]);
not n6 (nI[2], I[2]);
not n7 (nI[3], I[3]);
//CAMBIOS 3->4; 5->0; 8->10
//Q3
assign Q... | 6.500928 |
module trab8 (
input CLOCK_50,
output VGA_HS,
output VGA_VS,
output VGA_R,
output VGA_G,
output VGA_B
);
reg [ 3:0] Red;
reg [ 3:0] Green;
reg [ 3:0] Blue;
reg [11:0] V_Sync;
reg [11:0] H_Sync;
reg [11:0] i;
reg [11:0] j;
reg [ 3:0] count = 0;
assign VGA_R = Red;
assign ... | 6.594484 |
module trace (
input wire clk,
input wire rst,
input wire [136:0] dbg_i
);
wire [31:0] pc;
wire [31:0] sp;
wire [31:0] tos;
wire [31:0] nos;
wire [7:0] inst;
wire valid_dbg;
integer tracefile;
assign pc = dbg_i[31:0]; //pc
assign sp = dbg_i[63:32]; //sp
assign tos = dbg_i[95:64]; /... | 6.769849 |
module traceback_compare (
curr_index,
top_score,
diag_score,
left_score,
current_score,
//seq1,
// seq2,
// seq1_out,
// seq2_out,
next_index
);
parameter n = 4;
input [31:0] top_score, diag_score, left_score, current_score;
input [n:0] curr_index;
output [n:0] next_ind... | 6.991434 |
module traceback_prefetch_column_finder (
column_k1,
column_k0,
prefetch_request,
in_block_x_startpoint,
prefetch_x_startpoint,
prefetch_column
);
//I/O
input [0:`MEM_WIDTH*`DIRECTION_WIDTH-1] column_k0, column_k1;
input [1:0] prefetch_request;
input [`POSITION_WIDTH-1:0] in_block_x_sta... | 6.544244 |
module traceback_prefetch_row_dealer (
row_k1,
row_k0,
prefetch_request,
in_block_y_startpoint,
prefetch_y_startpoint,
prefetch_row
);
//I/O
input [`N*`DIRECTION_WIDTH-1:0] row_k0, row_k1;
input [1:0] prefetch_request;
input [`POSITION_WIDTH-1:0] in_block_y_startpoint, prefetch_y_startp... | 6.544244 |
module testbench (
input clk,
mem_ready_0,
mem_ready_1
);
// set this to 1 to test generation of counter examples
localparam ENABLE_COUNTERS = 0;
reg resetn = 0;
always @(posedge clk) resetn <= 1;
(* keep *) wire trap_0, trace_valid_0, mem_valid_0, mem_instr_0;
(* keep *) wire [3:0] mem_wstrb_... | 6.751666 |
module testbench (
input clk,
input [31:0] mem_rdata_in,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready
);
reg resetn = 0;
always @(posedge clk) resetn <= 1;
wire cpu0_trap;
wire cpu0_mem_valid;
wire cpu0_mem_instr;
... | 6.751666 |
module traced_objects (
input clk,
input [2:0] obj_id,
output reg [2:0] sub_id,
output reg [0:0] type_id
);
parameter TYPE_SPHERE = 0;
parameter TYPE_PLANE = 1;
always @(posedge clk) begin
case (obj_id)
3'd0: begin
sub_id <= 0;
type_id <= TYPE_SPHERE;
end
... | 6.523174 |
module traced_planes (
input clk,
input [2:0] obj_id,
output reg [95:0] plane_origin,
output reg [95:0] plane_normal,
output reg [ 2:0] mat_id
);
always @(posedge clk) begin
case (obj_id)
3'd0: begin
plane_origin[31:0] <= 0;
plane_origin[63:32] <= $signed(-33554432); /... | 7.324007 |
module TraceROM (
input clock,
input reset,
output stream_valid,
input stream_ready,
output [63:0] stream_bits_data,
output [ 7:0] stream_bits_keep,
output stream_bits_last,
output [47:0] macAddr,
output [31:0] length
);
bit __strea... | 6.546507 |
module trace_reg #(
parameter p_width = 6
) (
input [p_width - 1:0] i_tr,
input i_clk,
input i_rst_n,
output [p_width - 1:0] o_tr
);
reg [p_width - 1:0] r_tr;
assign o_tr = r_tr;
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) r_tr <= {p_... | 7.778591 |
module sim (
input clk,
input rst_n,
output reg [31:0] pc,
output reg pc_valid
);
initial begin
pc <= 0;
pc_valid <= 0;
end
always @(posedge clk) begin
if (rst_n) begin
pc <= pc + 4;
pc_valid <= 1;
end
end
endmodule
| 6.626082 |
module tracking (
input clk,
input rst_n,
input t_en,
input i_en,
input [10:0] c_min_i,
input [10:0] c_max_i,
input [10:0] r_min_i,
input [10:0] r_max_i,
input cmd_full,
input data_empty,
input [10:0] h_i,
input [10:0] w_i,
input [7:0] h_value... | 7.251841 |
module tracking_iq_fifo (
input clock,
input [(WIDTH-1):0] data,
input rdreq,
input sclr,
input wrreq,
output wire empty,
output wire [(WIDTH-1):0] q
);
parameter WIDTH = 108;
parameter D... | 6.571644 |
module tracking_loop_ram (
input clock,
input [(ADDR_WIDTH-1):0] address_a,
input [(ADDR_WIDTH-1):0] address_b,
input [(DATA_WIDTH-1):0] data_a,
input [(DATA_WIDTH-1):0] data_b,
input wren_a,
input ... | 6.574553 |
module TrackManager (
input iFpgaClock,
iFpgaReset
, input [7:0] iPianoCommand
, output reg [5:0] track0
, output reg [5:0] track1
, output reg [5:0] track2
, output reg [5:0] track3
);
always @(posedge iFpgaClock or posedge iFpgaReset) begin
if (iFpgaReset) begin
track0 <= 0;
... | 6.684485 |
module TrackMarkDetector (
clock,
cke,
reset,
index,
threshold,
detect
);
input clock; // clock input, positive-edge-triggered
input cke; // clock enable, positive-true
input reset; // reset input, positive-edge-triggered
input index; // index pulse input, active high
input [7:0] t... | 7.21522 |
module Traductor (
in,
out,
clk,
rst
);
input wire clk, rst;
input wire [2:0] in;
output reg [6:0] out;
always @(posedge clk, posedge rst)
if (rst) begin
out <= 7'd0;
end else
case (in)
4'b0000: out <= 7'd104; //30k
4'b0001: out <= 7'd62; //50k
4'b... | 7.101518 |
module traducto_addr_rtc_addr_mem_local (
input reset,
input [7:0] addr_rtc,
output reg [3:0] addr_mem_local
);
always @* begin
if (reset) addr_mem_local = 4'b1111;
else begin
case (addr_rtc)
8'h21: addr_mem_local = 4'b0000;
8'h22: addr_mem_local = 4'b0001;
8'h23:... | 8.237331 |
module traf3 (
input wire clk,
input wire clr,
output reg [5:0] lights
);
reg [ 2:0] state;
reg [24:0] count = 26'd11111111;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, // states
S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
parameter SEC5 = 26'd33333333, SEC1 = 26'd22222222; // delays
always @... | 6.855346 |
module nBitCounter (
count,
clk,
rst_n,
stop_v,
max_num
);
parameter n = 7;
output reg [n:0] count;
input clk;
input rst_n;
input stop_v;
input [n:0] max_num;
// Set the initial value
initial count = 90;
// Increment count on clock
always @(posedge clk or negedge rst_n)
if... | 6.668753 |
module nBitCounter_1 (
count,
clk,
rst_n,
stop_v,
max_num
);
parameter n = 7;
output reg [n:0] count;
input clk;
input rst_n;
input stop_v;
input [n:0] max_num;
// Set the initial value
initial count = 90;
// Increment count on clock
always @(posedge clk or negedge rst_n)
... | 6.512867 |
module get the 8-bits input and makes hundreds, tens, ones from the input
module binaryToBCD(number, hundreds, tens, ones);
// I/O Signal Definitions
input [7:0] number;
output reg [3:0] hundreds;
output reg [3:0] tens;
output reg [3:0] ones;
// Internal variable for storing bits
reg [19:0] sh... | 6.529157 |
module the core of program that get the inputs and predict nextStates from the input ...
// ... and presentStates and determine the output of machine
module stateMachine (R, A, B, CLK, RST, Counter,CounterValue, A_TIME_L, A_TIME_H, B_TIME_L, B_TIME_H, A_LIGHT, B_LIGHT, TEMP);
input R, A, B, CLK, RST, Counter;
input[... | 6.506388 |
module: TrafficControllerMain
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Run this module for at least 0.004ms
module TrafficControllerMain_test;
// Inputs
reg Reset;
reg Sensor... | 7.078693 |
module testbench;
reg ar, ag, ay, br, bg, by;
wire a_move, b_move;
traffic_four t (
ar,
ag,
ay,
br,
bg,
by,
a_move,
b_move
);
initial begin
$dumpfile("vcd/TrafficLightsTwo.vcd");
$dumpvars(0, testbench);
$display("ar\tag\tay\t\tbr\tbg\tby\t\ta_move\... | 7.015571 |
module Mux2x1 (
out,
in1,
in2,
s
);
output reg [1:0] out;
input [1:0] in1, in2;
input s;
always @(in1, in2, s) begin
if (s == 0) out = in1;
else if (s == 1) out = in2;
else out = 2'bxx;
end
endmodule
| 6.963017 |
module Xor (
out,
a,
b
);
output out;
input a, b;
wire x, y, z;
nand (x, a, b);
nand (y, a, x);
nand (z, b, x);
nand (out, y, z);
endmodule
| 7.144897 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/traffic_cl_comb/traffic_cl_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad;
output f_pad;
wire new_n9_, new_n10_;
assign f_pad = d_pad | ((new_n9_... | 6.939825 |
module trattic_control (
Clk,
Reset,
Done_NS,
Done_EW,
Red1,
Yellow1,
Green1,
Red2,
Yellow2,
Green2,
Sload_NS,
Sload_EW,
State_cnt
);
input Clk, Reset;
input Done_NS, Done_EW;
output Red1, Yellow1, Green1, Red2, Yellow2, Green2;
output Sload_NS, Sload_EW;
ou... | 6.777755 |
module divider (
clk100Mhz,
slowClk
);
input clk100Mhz; //fast clock
output slowClk; //slow clock
reg [27:0] counter;
// switch to 27 for visible division
assign slowClk = counter[24]; //(2^27 / 100E6) = 1.34seconds
initial begin
counter <= 0;
end
always @(posedge clk100Mhz) begin
... | 7.389371 |
module top (
RST,
lighta,
lightb,
lightw,
clk100Mhz
);
input RST, clk100Mhz;
output lighta, lightb, lightw;
wire slowClk;
wire [2:0] lighta, lightb;
wire [1:0] lightw;
divider divide (
clk100Mhz,
slowClk
);
traffic_controller traffic (
RST,
slowClk,
l... | 6.735964 |
module nsCounter (
input clk,
output [4:0] count
);
wire clk;
reg [4:0] count;
initial count = 0;
always @(negedge clk) count[0] <= ~count[0];
always @(negedge count[0]) count[1] <= ~count[1];
always @(negedge count[1]) count[2] <= ~count[2];
always @(negedge count[2]) count[3] <= ~count[3];... | 6.866158 |
module ewCounter (
input clk,
output [3:0] count
);
wire clk;
reg [3:0] count;
initial count = 0;
always @(negedge clk) count[0] <= ~count[0];
always @(negedge count[0]) count[1] <= ~count[1];
always @(negedge count[1]) count[2] <= ~count[2];
always @(negedge count[2]) count[3] <= ~count[3];... | 6.917313 |
module injection_ratio_ctrl #(
parameter MAX_PCK_SIZ = 10,
parameter MAX_RATIO = 100
) (
en,
pck_size, // average packet size in flit
clk,
reset,
inject, // inject one packet
freez,
ratio // 0~100 flit injection ratio
);
function integer log2;
input integer number;
... | 7.08373 |
module packet_gen #(
parameter P = 5,
parameter T1 = 4,
parameter T2 = 4,
parameter T3 = 4,
parameter RAw = 3,
parameter EAw = 3,
parameter TOPOLOGY = "MESH",
parameter DSTPw = 4,
parameter ROUTE_NAME = "XY",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter MAX_PCK_NUM = 100... | 8.086403 |
module distance_gen #(
parameter TOPOLOGY = "MESH",
parameter T1 = 4,
parameter T2 = 4,
parameter T3 = 4,
parameter EAw = 2,
parameter DISTw = 4
) (
src_e_addr,
dest_e_addr,
distance
);
input [EAw-1 : 0] src_e_addr;
input [EAw-1 : 0] dest_e_addr;
output [DISTw-1 : 0] distance... | 7.138576 |
module traffic_generator (
clk,
reset,
i__config,
i__generate_phase,
i__phase_count,
i__pifo_ready,
o__packet_flow_id,
o__packet_priority,
o__valid_packet_generated,
o__num_pkts_sent
);
`include "common_tb_headers.vh"
//----------------------------------------------------... | 6.512301 |
module traffic_led(
input sys_clk , //系统时钟信号
input sys_rst_n , //系统复位信号
input [3:0] key ,
output [7:0] bit , //数码管位选信号
output [7:0] segment , //数码管段选信号
output [23:0] led //LED使能信号
... | 7.407 |
module sevensegment (
clk,
in,
out
);
input clk;
input [2:0] in;
output reg [7:0] out;
always @(posedge clk) begin
case (in)
0: out <= 8'b00000011;
1: out = 8'b10011111;
2: out = 8'b00100101;
3: out = 8'b00001101;
4: out = 8'b10011001;
5: out = 8'b01001001;
... | 7.484815 |
module Display_fd (
clk_in,
reset,
clk_out
);
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `DisplayTime) begin
count <= 0;
clk_ou... | 7.522834 |
module Second_fd (
clk_in,
reset,
clk_out
);
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `SecondTime) begin
count <= 0;
clk_out ... | 6.88559 |
module
//
//////////////////////////////////////////////////////////////////////////////////
module traffic_light_top(
output wire red_light_nrth_s10th_st,
output wire ylw_light_nrth_s10th_st,
output wire grn_light_nrth_s10th_st,
output wire red_light_west_s10th_st,
output wire ylw_light_west_s10th_st,
output wire g... | 6.643738 |
module traffic_signal_controller (
clk,
x,
reset,
hwy,
cntry
);
input clk, reset, x;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
parameter green = 2'b00, red = 2'b01, yellow = 2'b10;
reg [2:0] state, next_state;
output reg [1:0] hwy, cntry;
initial begin
... | 6.677289 |
module tb_traffic_signal_controller;
// Inputs
reg clk;
reg x;
reg reset;
// Outputs
wire [1:0] hwy;
wire [1:0] cntry;
// Instantiate the Unit Under Test (UUT)
traffic_signal_controller uut (
.clk(clk),
.x(x),
.reset(reset),
.hwy(hwy),
.cntry(cntry)
);
always
#5 clk ~= clk;
initial begi... | 6.723729 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules... | 6.668911 |
module ram(
// read domain
input rd_clk,
input [ADDR_WIDTH-1:0] rd_addr,
output [DATA_WIDTH-1:0] rd_data,
// write domain
input wr_clk,
input wr_enable,
input [ADDR_WIDTH-1:0] wr_addr,
input [DATA_WIDTH-1:0] wr_data,
);
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=8;
parameter NUM_BYTES=256;
reg [DATA_WID... | 7.686454 |
module display_mapper (
input [12:0] linear_addr,
output [12:0] ram_addr
);
parameter PANEL_SHIFT_WIDTH = (13 * 32) / 32;
wire y_bank = linear_addr[4];
wire [4:0] y_addr = linear_addr[3:0] + (y_bank ? 0 : 16);
wire [12:0] x_value = linear_addr[12:5];
wire [12:0] x_offset;
reg [2:0] x_minor;
reg... | 6.82078 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n... | 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n... | 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n... | 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n... | 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n... | 6.892153 |
module add_mul_1_bit (
a,
b,
operation,
Result
);
input a, b, operation;
output Result;
wire Result_add, Result_mul, n3, n4;
INV_X1 U4 (
.I (Result_add),
.ZN(n4)
);
NAND2_X1 U5 (
.A1(Result_mul),
.A2(operation),
.ZN(n3)
);
OAI21_X1 U6 (
.A1(n4),
... | 6.690052 |
module add_mul_2_bit (
a,
b,
operation,
Result
);
input [0:1] a;
input [0:1] b;
output [0:3] Result;
input operation;
wire n6, n7, n8, SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
\adder_1/n2 , \adder_1/n1 , \multiplier_1/n3 , \multiplier_1/n2 ,
\multiplier_1/n1 ;
wire... | 6.768282 |
module add_mul_combine_2_bit (
a,
b,
Result_mul,
Result_add
);
input [0:1] a;
input [0:1] b;
output [0:3] Result_mul;
output [0:1] Result_add;
wire \adder_1/n2 , \adder_1/n1 , \multiplier_1/n3 , \multiplier_1/n2 , \multiplier_1/n1 ;
XOR2_X1 \adder_1/U4 (
.A1(a[1]),
.A2(b[1]),
... | 6.911403 |
module add_mul_comp_2_bit (
a,
b,
Result
);
input [0:1] a;
input [0:1] b;
output [0:3] Result;
wire n6, n7, n8, n9, n12, SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
\adder_1/n2 , \adder_1/n1 , \multiplier_1/n3 , \multiplier_1/n2 ,
\multiplier_1/n1 , \comparator_1/n5 , \compar... | 6.970429 |
module add_mul_mix_2_bit (
a,
b,
c,
d,
Result
);
input [0:1] a;
input [0:1] b;
input [0:1] c;
input [0:1] d;
output [0:3] Result;
wire \adder_1/n3 , \adder_1/n2 , \adder_1/n1 , \adder_2/n7 , \adder_2/n6 ,
\adder_2/n5 , \adder_2/n4 , \adder_2/n3 , \adder_2/n2 , \adder_2/n1 ,
... | 6.645763 |
module Train_Display_Generator (
clock,
act_D,
addr16[15:0],
disp10[9:0]
);
// PI and PO
input act_D;
input clock;
input [15:0] addr16;
output [9:0] disp10;
reg [9:0] disp10;
always @(posedge clock)
if (act_D == 1) begin
case (addr16)
16'b0000000000000000: disp10 <= ... | 6.726888 |
module: topFile
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module trajectoryTest;
// Inputs
reg CLK_50MHZ;
// Outputs
wire [0:7] LED;
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wi... | 8.26225 |
module Tran (
input wire reset_n,
clk,
start,
byte,
[7 : 0] data_in,
output wire [7 : 0] data_o,
wire data_en
);
reg state;
parameter S_0 = 0;
parameter S_4 = 1;
reg [7 ... | 6.852328 |
module Tran2 (
input wire Rst,
Clk,
start,
byt,
input wire [7:0] DB,
output reg Out_en,
output reg [7:0] Out
);
reg [3:0] DB_reg; //hold the valid bits
reg empty; //there is data in DB_reg, 0 no, 1 yes
always @(posedge Clk, negedge Rst)
if (!Rst) empty <... | 6.755404 |
module main;
// Model a pin with a weak keeper circuit. The way this works:
// If the pin value is 1, then attach a weak1 pullup, but
// if the pin value is 0, attach a weak0 pulldown.
wire pin;
pullup (weak1) (keep1);
pulldown (weak0) (keep0);
tranif1 (pin, keep1, pin);
tranif0 (pin, keep0, pin);
... | 6.7632 |
module Trans (
input clk,
reset,
transmitir,
bandera,
output reg salidaTx,
input [7:0] entradaSw
);
reg [5:0] estado;
always @(posedge clk, posedge reset) begin
if (reset) begin
estado <= 0;
salidaTx <= 1;
end else
case (estado)
0: begin
if (tran... | 6.577126 |
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