code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
// List of primary aliased buses
cell_1x1 m7 (
.bl(bl[7]),
.wr(wr),
.wp(wp)
);
c... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
// List of primary aliased buses
nvcm_cell_1x8 m6 (
.wp(wp[6]),
.wr(w... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
// List of primary aliased buses
nvcm_cell_8x8 m1 (
.bl(bl[15:8]),
... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_test;
inout [5:0] bl_dummyr;
inout [327:0] bl;
inout [1:0] bl_dummyl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
supply0 vss... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module i2c_wmux_bolt (
I2C_IRQ,
I2C_WKUP,
MRDCMPL,
SB_ACK_O,
SB_DAT_O,
SB_RW_O,
SCL_O,
SCL_OE,
SDA_O,
SDA_OE,
rxfifo_ae,
rxfifo_e,
rxfifo_f,
txfifo_ae,
txfifo_e,
txfifo_f,
FIFORST,
POR,
SB_ADR_I,
SB_CLK_I,
SB_CS_I,
SB_DAT_I,
SB_... | 6.871921 |
module bolt_ir_barcode (
i200uref,
barcode_pad,
drivergnd,
ir_pad,
barcode_en,
barcode_pwm,
cbit_barcode,
cbit_barcode_en,
cbit_ir500,
cbit_ir,
cbit_ir_en,
cbit_ir_half_cur,
cbit_rgb_en,
icc40u,
ir_pwm,
irled_en,
poc,
rgbled_en,
vccio
);
outp... | 6.632127 |
module irtcv_ip (
ir_out,
irtcv_busy,
irtcv_drdy,
irtcv_err,
irtcv_rdat,
VDD,
VSS,
ir_in,
irtcv_adr,
irtcv_clk,
irtcv_cs,
irtcv_den,
irtcv_exe,
irtcv_learn,
irtcv_rst_async,
irtcv_wdat,
irtcv_we
);
output ir_out, irtcv_busy, irtcv_drdy, irtcv_err;
... | 6.998323 |
module sb_ir_ip (
busy,
drdy,
err,
irout,
rdata,
VDD,
VSS,
adri,
clki,
csi,
deni,
exe,
irin,
learn,
rst,
wdata,
wei
);
output busy, drdy, err, irout;
inout VDD, VSS;
input clki, csi, deni, exe, irin, learn, rst, wei;
output [7:0] rdata;
i... | 6.805951 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
bdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
input [1:0] reset_b;
in... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
bdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] r;
inout [11:0] b;
inout [9:0] bl;
inout [11:0] t;
input [1:0] pgate;
inpu... | 6.508953 |
module span4_switchandmem_v3 (
c,
cc,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
bdd_cntl,
wl
);
input prog;
output [15:8] cc;
output [7:0] c;
inout [11:0] r;
inout [11:0] b;
inout [11:0] t;
inout [9:0] bl;
inout [11:0] l;
input [15:0] pgate;
input [15... | 7.107335 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_r_v_b;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_h_r;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I32 (
.nn (net25),
.pp (sel),
.out(out),
.in (in0)
... | 7.095052 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
bdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
bdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
bdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit[7:5],
sp4_out[4:0],
bl[3:0],
pgate[1:0],
prog,
reset[1:0],
slfop,
bdd_cntl[1:0],
wl[1:0]
);
input prog, slfop;
output [7:0] cbit;
output [4:0] sp4_out;
inout [3:0] bl;
input [1:0] wl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] bdd_... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf[23:0],
bl[3:0],
sp4_h_l[47:0],
sp4_v_b[15:0],
dout0[0],
dout0[1],
dout1[0],
dout1[1],
pgate[15:0],
prog,
reset[15:0],
bdd_cntl[15:0],
wl[15:0]
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inou... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.nn (net10),
.pp (sel),
.out(net16),
.in (in0)
);
... | 6.698244 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module MUX6502 #(
parameter N = 1
) (
output wire o,
input wire i,
input wire [N-1:0] s,
input wire [N-1:0] d
);
assign o = (|s) ? &(d | (~s)) : i;
endmodule
| 8.079194 |
module MUX #(
parameter N = 1
) (
output wire o,
input wire i,
input wire [N-1:0] s,
input wire [N-1:0] d
);
assign o = (|s) ? &(d | (~s)) : i;
endmodule
| 8.189064 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module chip_74ls245 (
input clk,
input [7:0] in,
input [7:0] bus,
input oe, // Active low
output [7:0] out
);
reg [7:0] data_out;
assign out = data_out;
always @(posedge clk) begin
if (oe == 1'b0) begin
data_out <= in;
end else begin
data_out <= bus;
end
end
endm... | 6.843052 |
module chip_74lv165 (
input SH_LDn, // high for shift, low for load
input CLK, // clock
input CLK_INH, // clock inhibit
input SER, // serial input
input [7:0] D, // parallel input, A-H for 0-7
output QH // serial output
);
reg [7:0... | 6.542371 |
module of your design, you cannot modify this module!!
`include "./RISCV_hasHazard2.v"
`include "./FORWARDING_UNIT.v"
`include "./HAZARD_DETECTION_UNIT.v"
`include "./cache_dm.v"
`include "./cache_ro_2way.v"
`include "./DECOMPRESSIONUNIT.v"
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_rea... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//---------... | 8.453083 |
module IFID (
clk,
rst_n,
IFID_stall,
IFID_flush,
IFID_in_instruction,
IFID_out_instruction,
IFID_in_PC,
IFID_out_PC,
IFID_in_PC4,
IFID_out_PC4,
IFID_in_FSM_states, //modified for branch prediction
IFID_out_FSM_states,
IFID_in_is_change,
IFID_out_is_change,
I... | 8.278578 |
module Reg32 (
clk,
rst_n,
RegWrite,
read_register1,
read_register2,
write_register,
write_data,
read_data1,
read_data2
);
input clk, rst_n, RegWrite;
input [4:0] read_register1;
input [4:0] read_register2;
input [4:0] write_register;
input [31:0] write_data;
output [31:0... | 7.20141 |
module ImmGen (
ImmGen_instruction,
ImmGen_imm
);
input [31:0] ImmGen_instruction;
output [31:0] ImmGen_imm;
reg [31:0] ImmGen_imm;
always @(*) begin
case (ImmGen_instruction[6:0])
7'b0010011: begin // ADDI, SLTI, XORI, ORI, ANDI, SLLI, SRLI, SRAI,
case (ImmGen_instruction[14:12])
... | 6.657692 |
module MUX21 (
MUX21_ctrl,
MUX21_normaldata,
MUX21_forwdata,
MUX21_out
);
input MUX21_ctrl;
input [31:0] MUX21_normaldata;
input [31:0] MUX21_forwdata;
output [31:0] MUX21_out;
assign MUX21_out = MUX21_ctrl ? MUX21_forwdata : MUX21_normaldata;
endmodule
| 7.205289 |
module PC (
clk,
rst_n,
PC_jump,
PC_stall,
PC_jumpaddr,
PC_r_pred_addr, //modified for branch prediction
PC_addr,
PC_PC4
);
input clk, rst_n, PC_jump, PC_stall;
input [31:0] PC_jumpaddr, PC_r_pred_addr;
output [31:0] PC_addr, PC_PC4;
reg [31:0] PC_addr, n_PC_addr;
assign PC_P... | 7.737094 |
module HazardUnit (
IDEX_MemRead,
IDEX_rd,
IFID_rs,
IFID_rs_eff,
IFID_rt,
IFID_rt_eff,
HU_stall
);
//======I/O Declaration================
input IDEX_MemRead;
input [4:0] IDEX_rd;
input [4:0] IFID_rs;
input IFID_rs_eff;
input [4:0] IFID_rt;
input IFID_rt_eff;
output HU_stal... | 8.02365 |
module JAL (
ID_opcode,
JAL_flush
);
//======I/O Declaration================
input [6:0] ID_opcode;
output JAL_flush;
//=====Combinational Part=============
assign JAL_flush = ID_opcode[3];
endmodule
| 6.975285 |
module JALR (
ID_opcode,
ID_rs,
EX_rd,
EX_rd_eff,
JALR_stall,
JALR_flush //is JALR
);
//======I/O Declaration===============
input [6:0] ID_opcode;
input [4:0] ID_rs;
input [4:0] EX_rd;
input EX_rd_eff;
output JALR_stall;
output JALR_flush;
wire match;
//======Combinational... | 7.199326 |
module JumpBranch (
ID_opcode,
ID_funct3,
ID_rs,
ID_rt,
ID_is_equal,
EX_rd,
EX_rd_eff,
ID_Imm,
ID_PC,
ID_PC4, //modified for branch prediction
ID_data1,
in_branch_addr, //modified for branch prediction
ID_br_taken, //
out_miss, //
out_miss_addr, //
Ju... | 7.939655 |
module ForwardUnit (
rs_valid,
rt_valid,
in_rs,
in_rt,
EXMEM_en,
EXMEM_rd,
EXMEM_data,
MEMWB_en,
MEMWB_rd,
MEMWB_data,
rs_forward,
rs_forward_data,
rt_forward,
rt_forward_data
);
//==== in/out declaration =================================
input [31:0] EXMEM_da... | 6.879476 |
module StallUnit_Normal (
JumpBranch_stall,
HU_stall,
JumpBranch_flush,
InsCache_stall,
DataCache_stall,
IFID_is_forward,
ID_is_bubble,
EX_is_bubble,
MEM_is_lw,
has_stall,
has_zero
);
//==== in/out declaration =================================
input JumpBranch_stall, HU_s... | 7.494643 |
module PredictionUnit_2AL(
is_branch, //is branch or not
miss, //whether last prediction is correct or not
PC_addr,
PC4_addr,
br_Imm,
FSM_states_f,
nxt_FSM_states_f,
is_change, //whether change state or not
nxt_is_change,
br_history,
nxt_br_histor... | 7.98293 |
module FSM_2bit (
miss,
FSM_state,
FSM_last_state,
FSM_out_state,
out_is_taken
);
//==== in/out declaration =================================
input [1:0] FSM_state, FSM_last_state;
input miss;
output [1:0] FSM_out_state;
output out_is_taken;
//==== reg/wire declaration ==================... | 6.508097 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//---------... | 8.453083 |
module IFID(
clk,
rst_n,
IFID_stall,
IFID_flush,
IFID_in_instruction,
IFID_out_instruction,
IFID_in_PC,
IFID_out_PC,
IFID_in_PC4,
IFID_out_PC4,
IFID_in_FSM_states,//modified for branch prediction
IFID_out_FSM_states,
IFID_in_is_change,
IFID_out_is_change,
IFID... | 8.020444 |
module Reg32 (
clk,
rst_n,
RegWrite,
read_register1,
read_register2,
write_register,
write_data,
read_data1,
read_data2
);
input clk, rst_n, RegWrite;
input [4:0] read_register1;
input [4:0] read_register2;
input [4:0] write_register;
input [31:0] write_data;
output [31:0... | 7.20141 |
module ImmGen (
ImmGen_instruction,
ImmGen_imm
);
input [31:0] ImmGen_instruction;
output [31:0] ImmGen_imm;
reg [31:0] ImmGen_imm;
always @(*) begin
case (ImmGen_instruction[6:0])
7'b0010011: begin // ADDI, SLTI, XORI, ORI, ANDI, SLLI, SRLI, SRAI,
case (ImmGen_instruction[14:12])
... | 6.657692 |
module MUX21 (
MUX21_ctrl,
MUX21_normaldata,
MUX21_forwdata,
MUX21_out
);
input MUX21_ctrl;
input [31:0] MUX21_normaldata;
input [31:0] MUX21_forwdata;
output [31:0] MUX21_out;
assign MUX21_out = MUX21_ctrl ? MUX21_forwdata : MUX21_normaldata;
endmodule
| 7.205289 |
module PC (
clk,
rst_n,
PC_jump,
PC_stall,
PC_jumpaddr,
PC_r_pred_addr, //modified for branch prediction
PC_addr,
PC_PC4
);
input clk, rst_n, PC_jump, PC_stall;
input [31:0] PC_jumpaddr, PC_r_pred_addr;
output [31:0] PC_addr, PC_PC4;
reg [31:0] PC_addr, n_PC_addr;
assign PC_P... | 7.737094 |
module HazardUnit (
IDEX_MemRead,
IDEX_rd,
IFID_rs,
IFID_rs_eff,
IFID_rt,
IFID_rt_eff,
HU_stall
);
//======I/O Declaration================
input IDEX_MemRead;
input [4:0] IDEX_rd;
input [4:0] IFID_rs;
input IFID_rs_eff;
input [4:0] IFID_rt;
input IFID_rt_eff;
output HU_stal... | 8.02365 |
module JAL (
ID_opcode,
JAL_flush
);
//======I/O Declaration================
input [6:0] ID_opcode;
output JAL_flush;
//=====Combinational Part=============
assign JAL_flush = ID_opcode[3];
endmodule
| 6.975285 |
module JALR (
ID_opcode,
ID_rs,
EX_rd,
EX_rd_eff,
JALR_stall,
JALR_flush //is JALR
);
//======I/O Declaration===============
input [6:0] ID_opcode;
input [4:0] ID_rs;
input [4:0] EX_rd;
input EX_rd_eff;
output JALR_stall;
output JALR_flush;
wire match;
//======Combinational... | 7.199326 |
module JumpBranch (
ID_opcode,
ID_funct3,
ID_rs,
ID_rt,
ID_is_equal,
EX_rd,
EX_rd_eff,
ID_Imm,
ID_PC,
ID_PC4, //modified for branch prediction
ID_data1,
in_branch_addr, //modified for branch prediction
ID_br_taken, //
out_miss, //
out_miss_addr, //
Ju... | 7.939655 |
module ForwardUnit (
rs_valid,
rt_valid,
in_rs,
in_rt,
EXMEM_en,
EXMEM_rd,
EXMEM_data,
MEMWB_en,
MEMWB_rd,
MEMWB_data,
rs_forward,
rs_forward_data,
rt_forward,
rt_forward_data
);
//==== in/out declaration =================================
input [31:0] EXMEM_da... | 6.879476 |
module StallUnit_Normal (
JumpBranch_stall,
HU_stall,
JumpBranch_flush,
InsCache_stall,
DataCache_stall,
IFID_is_forward,
ID_is_bubble,
EX_is_bubble,
MEM_is_lw,
has_stall,
has_zero
);
//==== in/out declaration =================================
input JumpBranch_stall, HU_s... | 7.494643 |
module PredictionUnit_2bit(
is_branch, //is branch or not
miss, //whether last prediction is correct or not
PC_addr,
PC4_addr,
br_Imm,
FSM_states,
nxt_FSM_states,
is_change, //whether change state or not
nxt_is_change,
nxt_is_taken,
out_br_addr,
... | 7.98293 |
module FSM_2bit (
miss,
FSM_state,
FSM_out_state,
out_is_taken
);
//==== in/out declaration =================================
input [1:0] FSM_state;
input miss;
output [1:0] FSM_out_state;
output out_is_taken;
//==== reg/wire declaration ===============================
reg [1:0] FSM_out_st... | 6.508097 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module PredictionUnit (
BrPre,
clk,
rst_n,
stall,
PreWrong,
B
);
output BrPre; // Prediction Output
// 1/0 stands for a positive/negative prediction on branching
input clk, rst_n, //input clock and reset signal
stall, //stall signal from cache or hazard detection unit
... | 7.98293 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module chip_case (
p1a,
p1b,
p1c,
p1d,
p2a,
p2b,
p2c,
p2d,
p1y,
p2y
);
input wire p1a;
input wire p1b;
input wire p1c;
input wire p1d;
input wire p2a;
input wire p2b;
input wire p2c;
input wire p2d;
output wire p1y;
output wire p2y;
assign p1y = ~(p1a & p1b... | 7.360495 |
module name - chip_clock_control
// Version: COC_V1.0.0_20220110
// Created:
// by - fenglin
// at - 1.2022
////////////////////////////////////////////////////////////////////////////
// Description:
// chip_clock_control
////////////////////////////////////////////////////////////////////////... | 7.063498 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
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