code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module chip_data_parser (
input clk,
input [7:0] r,
input [7:0] g,
input [7:0] b,
input valid,
output reg [11:0] chip_data,
output reg chip_data_enable
);
reg [23:0] pixel;
always @(posedge clk) begin
pixel <= {r, g, b};
chip_data_enable <= valid;
end
/* Double-pumped flip... | 7.589965 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module IFID (
clk,
rst_n,
IFID_stall,
IFID_flush,
IFID_in_instruction,
IFID_out_instruction,
IFID_in_PC,
IFID_out_PC,
IFID_in_PC4,
IFID_out_PC4
);
localparam NOP = 32'd0;
input clk, rst_n, IFID_stall, IFID_flush;
input [31:0] IFID_in_instruction;
input [31:0] IFID_in_PC4;... | 8.278578 |
module Reg32 (
clk,
rst_n,
RegWrite,
read_register1,
read_register2,
write_register,
write_data,
read_data1,
read_data2
);
input clk, rst_n, RegWrite;
input [4:0] read_register1;
input [4:0] read_register2;
input [4:0] write_register;
input [31:0] write_data;
output [31:0... | 7.20141 |
module ImmGen (
ImmGen_instruction,
ImmGen_imm
);
input [31:0] ImmGen_instruction;
output [31:0] ImmGen_imm;
reg [31:0] ImmGen_imm;
always @(*) begin
case (ImmGen_instruction[6:0])
7'b0010011: begin // ADDI, SLTI, XORI, ORI, ANDI, SLLI, SRLI, SRAI,
case (ImmGen_instruction[14:12])
... | 6.657692 |
module MUX21 (
MUX21_ctrl,
MUX21_normaldata,
MUX21_forwdata,
MUX21_out
);
input MUX21_ctrl;
input [31:0] MUX21_normaldata;
input [31:0] MUX21_forwdata;
output [31:0] MUX21_out;
assign MUX21_out = MUX21_ctrl ? MUX21_forwdata : MUX21_normaldata;
endmodule
| 7.205289 |
module PC (
clk,
rst_n,
PC_jump,
PC_stall,
PC_jumpaddr,
PC_plus_4or2,
PC_addr,
PC_PC4
);
input clk, rst_n, PC_jump, PC_stall, PC_plus_4or2;
input [31:0] PC_jumpaddr;
output [31:0] PC_addr, PC_PC4;
reg [31:0] PC_addr, n_PC_addr;
assign PC_PC4 = PC_plus_4or2 ? PC_addr + 2 : PC_a... | 7.737094 |
module Compression_ctrl (
clk,
rst_n,
jump, //jump or branch taken
PC_stall, // PC_stall form stall unit
PC_reg, // Data from the PC register
ICACHE_data, // data from Icache in big indian form
ICACHE_addr, // address to read from Icache
Ins_out, // the decompressed Ins.
PC_plu... | 7.636922 |
module HazardUnit (
IDEX_MemRead,
IDEX_rd,
IFID_rs,
IFID_rs_eff,
IFID_rt,
IFID_rt_eff,
HU_stall
);
//======I/O Declaration================
input IDEX_MemRead;
input [4:0] IDEX_rd;
input [4:0] IFID_rs;
input IFID_rs_eff;
input [4:0] IFID_rt;
input IFID_rt_eff;
output HU_stal... | 8.02365 |
module JAL (
ID_opcode,
JAL_flush
);
//======I/O Declaration================
input [6:0] ID_opcode;
output JAL_flush;
//=====Combinational Part=============
assign JAL_flush = ID_opcode[3];
endmodule
| 6.975285 |
module JALR (
ID_opcode,
ID_rs,
EX_rd,
EX_rd_eff,
JALR_stall,
JALR_flush //is JALR
);
//======I/O Declaration===============
input [6:0] ID_opcode;
input [4:0] ID_rs;
input [4:0] EX_rd;
input EX_rd_eff;
output JALR_stall;
output JALR_flush;
wire match;
//======Combinational... | 7.199326 |
module JumpBranch (
ID_opcode,
ID_funct3,
ID_rs,
ID_rt,
ID_is_equal,
EX_rd,
EX_rd_eff,
ID_Imm,
ID_PC,
ID_data1,
JumpBranch_addr,
JumpBranch_jump,
JumpBranch_stall,
JumpBranch_flush,
JumpBranch_link,
JumpBranch_branch,
JumpBranch_JALR
);
//=====I/O D... | 7.939655 |
module ForwardUnit (
rs_valid,
rt_valid,
in_rs,
in_rt,
EXMEM_en,
EXMEM_rd,
EXMEM_data,
MEMWB_en,
MEMWB_rd,
MEMWB_data,
rs_forward,
rs_forward_data,
rt_forward,
rt_forward_data
);
//==== in/out declaration =================================
input [31:0] EXMEM_da... | 6.879476 |
module StallUnit_Normal (
JumpBranch_stall,
HU_stall,
JumpBranch_flush,
InsCache_stall,
DataCache_stall,
IFID_is_forward,
ID_is_bubble,
EX_is_bubble,
MEM_is_lw,
has_stall,
has_zero,
Comp_stall,
Comp_stalled
);
//==== in/out declaration ==============================... | 7.494643 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module Hazard_dection_Unit (
rs1,
rs2,
equal,
rd_Ex,
reg_write_Ex,
jal,
jalr,
beq,
bneq,
mem_read_,
pc_mux,
IF_mux,
control_mux
); //variable ending with '_' means next stage value
input [4:0] rs1, rs2, rd_Ex;
input equal, jal, jalr, beq, bneq, mem_read_, reg_wri... | 8.37264 |
module Forward_Unit (
regwrite_1,
rd_1,
regwrite_2,
rd_2,
rs1,
rs2,
muxA,
muxB
); //EX|1(MEM)|2(WB)
input regwrite_1, regwrite_2;
input [4:0] rs1, rs2, rd_1, rd_2;
output reg [1:0] muxA, muxB;
always @(*) begin
if ((regwrite_1) && (rd_1 == rs1)) muxA = 2'b10;
else if ((r... | 7.314655 |
module Control_Unit (
in,
rd,
RegWrite,
DataToReg,
jal,
jalr,
MemRead,
MemWrite,
Alusrc,
beq,
bneq
); //
input [7:0] in;
input [4:0] rd;
output reg RegWrite, jal, jalr, MemRead, MemWrite, Alusrc, beq, bneq;
output reg [1:0] DataToReg;
always @(*) begin
beq = ({... | 8.640647 |
module ImmGen (
in,
out
);
input [31:0] in;
output reg [31:0] out;
reg t1, t2, garbage;
always @(*) begin
t1 = ((!in[5]) & (!in[3])) | in[2];
t2 = ((!in[6]) | in[2]) & (!in[3]);
case ({
t1, t2
})
2'b00: out = {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; //beq,bneq
... | 6.657692 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
);
txgate I31 (
... | 6.698244 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_drv),
... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
inout [327:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate I32... | 7.095052 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
);
txgate I31 (
... | 6.698244 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_drv),
... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
inout [327:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate I32... | 7.095052 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
);
txgate I31 (
... | 6.698244 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_drv),
... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
inout [327:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate I32... | 7.095052 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
);
txgate I31 (
... | 6.698244 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_drv),
... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
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