code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
inout [327:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate I32... | 7.095052 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
);
txgate I31 (
... | 6.698244 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_drv),
... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
inout [327:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module span4_switchandmem_v3 (
c,
cc,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [7:0] c;
output [15:8] cc;
inout [11:0] r;
inout [9:0] bl;
inout [11:0] t;
inout [11:0] l;
inout [11:0] b;
input [15:0] reset_b;
input [... | 7.107335 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate I32... | 7.095052 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] pgate_l;
input [1:0] wl_r;
input [1:0] r_gnd_r;
input [1:0] pgate_r;
input [1:0] wl_l;
... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
input [1:0] reset_b;
in... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] r;
inout [11:0] b;
inout [9:0] bl;
inout [11:0] t;
input [1:0] pgate;
inpu... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_r_v_b;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_h_r;
input [11:0] cbitb;
supply1 vdd_;
//wire vddp_ = t... | 6.657756 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
//wire vddp_ = test.cds_glo... | 7.048968 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x4 (
bl,
wp,
wr
);
inout [7:0] bl;
input [3:0] wp;
input [3:0] wr;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 6.673664 |
module nvcm_cell_16x4 (
bl,
wp,
wr
);
inout [15:0] bl;
input [3:0] wr;
input [3:0] wp;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x4 m0 (
.wr(wr[3:0]),
.wp(wp[3:0]),
.bl(bl[7:0])
);
nvcm_cell_8x4... | 7.518892 |
module nvcm_cell_336x4 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [327:0] bl;
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
input [3:0] wr;
input [3:0] wp;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
... | 6.666213 |
module nvcm_cell_16x2 (
bl,
wp,
wr
);
inout [15:0] bl;
input [1:0] wr;
input [1:0] wp;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 Inst_0 (
.bl(bl[7:0]),
.wr(wr[1]),
.wp(wp[1])
);
nvcm_cell_1x8... | 7.518892 |
module nvcm_cell_336x2 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [327:0] bl;
inout [1:0] bl_test;
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
input [1:0] wp;
input [1:0] wr;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
... | 6.666213 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_test;
inout [5:0] bl_dummyr;
inout [327:0] bl;
inout [1:0] bl_dummyl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 gnd_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply0 gnd_;
supply1 vdd_;
supply0 GND_;
txgate I32 (
.nn (net25),
.pp (sel),
.out(out),
.in (in0)
);
txgate I31 (
.nn (sel),
.pp (net25),
.out(out),
... | 7.095052 |
module ioe_logic_v3_nooe (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, r... | 6.602506 |
module fabric_outbuf12p (
cout,
fabric_out
);
output cout;
input fabric_out;
supply0 gnd_;
supply1 vdd_;
supply0 GND_;
inv I_inv2 (
.Y(cout),
.A(net19)
);
inv I_inv1 (
.Y(net19),
.A(fabric_out)
);
endmodule
| 6.604346 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply0 gnd_;
supply1 vdd_;
supply0 GND_;
txgate I31 (
.nn (net10),
.pp (sel),
.out(net16),
.in (in0)
);
txgate Itg20 (
.nn (sel),
.pp (net10),
.out(net16),
... | 6.698244 |
module io_odrv4x5 (
cbit[7:5],
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [7:0] cbit;
output [4:0] sp4_out;
inout [3:0] bl;
input [1:0] wl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] vdd_cntl;
supply0 gnd_;
suppl... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0[0],
dout0[1],
dout1[0],
dout1[1],
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [1:0] dout1;
inpu... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, s... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio,... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb... | 6.759959 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
input [1:0] reset_b;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] r;
inout [11:0] b;
inout [9:0] bl;
inout [11:0] t;
input [1:0] pgate;
inp... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
supply0 gnd_;
supply1 vdd_;
supply0 GND_;
cram2x2 Imstake_5_ (
.wl(... | 6.651239 |
module i2c_wmux_v2 (
I2C_IRQ,
I2C_WKUP,
SB_ACK_O,
SB_DAT_O,
SCL_O,
SCL_OE,
SDA_O,
SDA_OE,
ADDR_LSB_USR,
POR,
SB_ADR_I,
SB_CLK_I,
SB_DAT_I,
SB_ID,
SB_RW_I,
SB_STB_I,
SCL_I,
SDA_I,
alt_in_scl,
alt_in_sda,
cbit2usealt_in,
scan_test_mod... | 6.886481 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_r_v_b;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_h_r;
input [11:0] cbitb;
supply0 gnd_;
supply1 vdd_;
... | 6.657756 |
module CHIP (
clk,
rst_n,
in_valid,
in_image,
out_valid,
out_image
);
input clk;
input rst_n;
input in_valid;
input [7:0] in_image;
output out_valid;
output [7:0] out_image;
// Internal wires
wire C_clk;
wire C_rst_n;
wire C_in_valid;
wire [7:0] C_in_data;
wire C_out_val... | 8.331638 |
module CHIP (
clk,
rst_n,
in_valid,
in_image,
out_valid,
out_image
);
input clk;
input rst_n;
input in_valid;
input [7:0] in_image;
output out_valid;
output [7:0] out_image;
// Internal wires
wire C_clk;
wire C_rst_n;
wire C_in_valid;
wire [7:0] C_in_image;
wire C_out_va... | 8.331638 |
module chip_interface (
priv_scl,
priv_sda,
main_scl,
main_sda,
sysclk, //y_button,
dac_level,
dac_clk,
LED_out,
reset,
debug_port,
seedclock,
pulldown_trans
);
input reset;
input priv_scl, priv_sda, main_sda, main_scl, sysclk; //y_button;
reg clk;
output [7:0] ... | 6.849092 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_add... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_add... | 8.453083 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_34 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_35 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_36 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_37 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_38 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n1;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n1)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_30 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_31 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_32 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_33 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n1;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n1)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_20 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_21 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX2_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_22 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_23 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_24 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X... | 6.575704 |
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