code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n1;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n1)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net23937;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net23937),
.CLK(n2)
);
AND2X2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_31 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_32 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_33 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_34 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_35 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n1;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n1)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_18 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_30 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24014;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24014),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_value_correct_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24210;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24210),
.CLK(n2)
);
AND2X... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_value_correct_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24210;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24210),
.CLK(n2)
);
AND2X... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_57 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_58 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_59 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n1;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n1)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_49 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24245;
wire n1;
wire n2;
NBUFFX2_HVT U2 (
.A(net24245),
.Y(n1)
);
AND2X2_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.A2(CLK)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_50 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_51 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_52 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24245;
wire n1;
wire n2;
NBUFFX4_HVT U2 (
.A(net24245),
.Y(n1)
);
AND2X2_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.A2(CLK)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_53 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24245;
wire n1;
wire n2;
NBUFFX4_HVT U2 (
.A(net24245),
.Y(n1)
);
AND2X4_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.A2(CLK)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_54 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24245;
wire n1;
wire n2;
NBUFFX4_HVT U2 (
.A(net24245),
.Y(n1)
);
AND2X4_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.A2(CLK)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_55 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_56 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_41 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24245;
wire n3;
wire n2;
NBUFFX4_HVT U2 (
.A(net24245),
.Y(n3)
);
LATCHX2_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_42 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_43 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_44 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_45 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24245;
wire n1;
wire n2;
NBUFFX4_HVT U2 (
.A(net24245),
.Y(n1)
);
AND2X2_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.A2(CLK)
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_46 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_47 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_48 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X4_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_33 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_34 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_35 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_36 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_37 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_38 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_39 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_40 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_30 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_31 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_32 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_18 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_19 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_20 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_21 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_22 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_23 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_24 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X4_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT ... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
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