code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24245;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24245),
.CLK(n2)
);
AND2X2_HVT m... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24560;
wire n1;
wire n2;
NBUFFX2_HVT U2 (
.A(net24560),
.Y(n1)
);
AND2X2_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.A2... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX2_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX2_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AND... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire net24637;
wire n1;
wire n2;
NBUFFX2_HVT U2 (
.A(net24637),
.Y(n1)
);
AND2X1_HVT main_gate (
.Y (ENCLK),
.A1(n1),
.... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
A... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_21 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_22 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_23 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_24 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX2_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_18 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_19 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_20 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24560;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24560),
.CLK(n2)
);
AN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_18 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_19 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK;
input EN;
output ENCLK;
/* wire declarations */
wire n2;
wire net24637;
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
LATCHX1_HVT latch (
.D (EN),
.Q (net24637),
.CLK(n2)
);
... | 6.575704 |
module ex_circuit (
A,
B,
C,
f
);
input A, B, C;
output f;
// Not wires
wire ap, bp, cp;
not a_not (ap, A);
not b_not (bp, B);
// First xor
wire ap_B, bp_A;
and ap_B_or (ap_B, ap, B);
and bp_A_or (bp_A, bp, A);
wire r, rp; // An output holder
or xor_ab (r, ap_B, bp_A); // First... | 8.368697 |
module: ex_circuit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module chip_master_tb;
// Inputs
reg A;
reg B;
reg C;
// Outputs
wire f;
// Instantiate the Unit Under Test (UUT... | 7.316492 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module Alu (
ctrl,
x,
y,
result
);
input [3:0] ctrl;
input signed [31:0] x;
input signed [31:0] y;
output reg [31:0] result;
always @(*) begin
case (ctrl[2:0])
3'b000: result = (ctrl[3] == 1'b0) ? x + y : x - y;
3'b111: result = x & y;
3'b110: result = x | y;
3'b... | 6.891033 |
module register_file (
Clk,
rst_n,
WEN,
RW,
busW,
RX,
RY,
busX,
busY
);
input Clk, WEN, rst_n;
input [4:0] RW, RX, RY;
input [31:0] busW;
output reg [31:0] busX, busY;
reg [31:0] r[0:31];
always @(*) begin
busX = r[RX];
busY = r[RY];
end
integer i;
alway... | 6.605344 |
module CHIP (
clk_p_i,
reset_n_i,
data_i,
start_i,
data_o,
done_o
);
input [20:0] data_i;
output [4:0] data_o;
output done_o;
input clk_p_i, reset_n_i, start_i;
wire [20:0] i_data_i;
wire [ 4:0] i_data_o;
wire i_clk_p_i, i_reset_n_i, i_start_i, i_done_o;
wire n_logic0, n_logic... | 8.331638 |
module CHIP (
clk,
rst_n,
boot_up,
boot_addr,
boot_datai,
boot_web,
peri_web,
peri_addr,
peri_datao
);
input [7:0] boot_addr;
input [31:0] boot_datai;
output [15:0] peri_addr;
output [15:0] peri_datao;
input clk, rst_n, boot_up, boot_web;
output peri_web;
top_pipe U0 (... | 8.331638 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module inv_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.281121 |
module exor2_25 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.63069 |
module nor4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A | B | C | D);
endmodule
| 7.961286 |
module exor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 9.259946 |
module nand4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.931189 |
module nand3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.69723 |
module nor3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.780348 |
module nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.297456 |
module anor21_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C) assign Y = ~(C | (B * A));
endmodule
| 6.919113 |
module mux2_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.126877 |
module oai21x2_lvt (
Y,
A0,
A1,
B0
);
output Y;
input A0;
input A1;
input B0;
reg Y;
always @(A0 or A1 or B0)
if (B0 == 1'b0) begin
Y = 1'b1;
end else begin
Y = !(A0 | A1);
end
endmodule
| 6.690466 |
module anor21_lvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C) assign Y = ~(C | (B * A));
endmodule
| 6.881661 |
module nor2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.594783 |
module mux2x1_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.134428 |
module mux2x1_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.134428 |
module carry_logic_nand (
cout,
a,
a_bar,
b,
b_bar,
carry_in,
vg_en
);
output cout;
input a;
input a_bar;
input b;
input b_bar;
input carry_in;
input vg_en;
endmodule
| 6.500349 |
module clut4vic (
lut4,
lut4vic,
cbit,
in0,
in0b,
in1,
in1b,
in2,
in2b,
in3,
in3b
);
output lut4;
output lut4vic;
input [15:0] cbit;
input in0;
input in0b;
input in1;
input in1b;
input in2;
input in2b;
input in3;
input in3b;
endmodule
| 7.068048 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.175282 |
module nand2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.392288 |
module inv_lvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.525807 |
module nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.113032 |
module nand2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.305138 |
module inv (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.1601 |
module inv_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.281121 |
module nor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.725239 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 VDD_;
supply0 GND_;
txgate I32 (
.nn (net25),
.pp (sel),
.out(out),
.in (in0)
... | 7.095052 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
input [1:0] reset_b;
in... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] r;
inout [11:0] b;
inout [9:0] bl;
inout [11:0] t;
input [1:0] pgate;
inpu... | 6.508953 |
module span4_switchandmem_v3 (
c,
cc,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [15:8] cc;
output [7:0] c;
inout [11:0] r;
inout [11:0] b;
inout [11:0] t;
inout [9:0] bl;
inout [11:0] l;
input [15:0] pgate;
input [15... | 7.107335 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_r_v_b;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_h_r;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module io_odrv4x5 (
cbit[7:5],
sp4_out[4:0],
bl[3:0],
pgate[1:0],
prog,
reset[1:0],
slfop,
vdd_cntl[1:0],
wl[1:0]
);
input prog, slfop;
output [7:0] cbit;
output [4:0] sp4_out;
inout [3:0] bl;
input [1:0] wl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] vdd_... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf[23:0],
bl[3:0],
sp4_h_l[47:0],
sp4_v_b[15:0],
dout0[0],
dout0[1],
dout1[0],
dout1[1],
pgate[15:0],
prog,
reset[15:0],
vdd_cntl[15:0],
wl[15:0]
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inou... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 VDD_;
supply0 GND_;
txgate I31 (
.nn (net10),
.pp (sel),
.out(net16),
.in (in0)
);
... | 6.698244 |
module i2c_wmux_v3 (
I2C_IRQ,
I2C_WKUP,
SB_ACK_O,
SB_DAT_O,
SCL_O,
SCL_OE,
SDA_O,
SDA_OE,
ADDR_LSB_USR,
POR,
SB_ADR_I,
SB_CLK_I,
SB_DAT_I,
SB_ID,
SB_RW_I,
SB_STB_I,
SCL_I,
SDA_I,
alt_in_scl,
alt_in_sda,
cbit2usealt_in,
delaysel,
... | 7.288029 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
supply0 vss... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 VDD_;
supply0 GND_;
// List of primary aliased buses
nvcm_cell_2x1 m0 (
.wp(wp[0]),
.wr(w... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 VDD_;
supply0 GND_;
// List of primary aliased buses
cell_1x1 m7 (
.bl(bl[7]),
.wr(wr),
.wp(wp)
);
c... | 7.009947 |
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