code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 VDD_;
supply0 GND_;
// List of primary aliased buses
nvcm_cell_1x8 m6 (
.wp(wp[6]),
.wr(w... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 VDD_;
supply0 GND_;
// List of primary aliased buses
nvcm_cell_8x8 m1 (
.bl(bl[15:8]),
... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_test;
inout [5:0] bl_dummyr;
inout [327:0] bl;
inout [1:0] bl_dummyl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
... | 6.666213 |
module yutorina_chip_top (
input wire clk_ref,
input wire rst_sw
);
wire clk;
wire clk_;
wire chip_rst;
yutorina_clk_gen clk_gen (
.clk_ref(clk_ref),
.rst_sw(rst_sw),
.clk(clk),
.clk_(clk_),
.chip_rst(chip_rst)
);
yutorina_chip chip (
.clk (clk),
.clk_(clk_)... | 6.969892 |
module chip_top_tb;
reg clk;
reg rst;
wire hsync;
wire vsync;
wire r;
wire g;
wire b;
chip_top chip_top0 (
.clk_i(clk),
.rst_i(rst),
.hsync_o(hsync),
.vsync_o(vsync),
.r_o(r),
.g_o(g),
.b_o(b)
);
initial begin
clk = 1'b0;
forever begin
#20... | 6.785222 |
module chip_top_test;
/********** I/O signal **********/
// Clock & Reset
reg clk_ref; // Reference clock
reg reset_sw; // Global reset
// UART
`ifdef IMPLEMENT_UART // UART implementation
wire uart_rx; // UART RX
wire uart_tx; // UART TX
`endif
// GPIO
`ifdef IMPLEMENT_GPIO // GPIO implementation... | 7.685995 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_I,
mem_wd... | 8.453083 |
module of your design, you cannot modify this module!!
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
mem_write_D,
mem_addr_D,
mem_wdata_D,
mem_rdata_D,
mem_ready_D,
//----------for slow_memI------------
mem_read_I,
mem_write_I,
mem_addr_... | 8.453083 |
module chirp (
input clk,
input rst_n,
output [13:0] chirp_out
);
reg [13:0] reg_chirp_out;
assign chirp_out = douta;
reg [ 8:0] addra;
wire [15:0] douta;
ip_chirp_data_rom uut (
.clka (clk),
.addra(addra),
.douta(douta)
);
always @(posedge clk or negedge rst_n) begin
... | 8.185735 |
module chirpgen #(
parameter DDS_LATENCY = 2
) (
input clk,
input rst,
output [15:0] chirp_out_i,
output [15:0] chirp_out_q,
output chirp_out_valid,
output chirp_out_last,
output chirp_ready,
output chirp_done,
output chirp_active,
input chirp_init,
input chirp_enable,... | 8.131245 |
module chirp_driver #(
parameter DD_SHIFT = 8,
parameter AMP_WI = 20,
parameter PH_WI = 32,
parameter LEN_WI = 32,
parameter CHIRP_RATE = 8
) (
input clk,
input chirp_start, // Edge-triggered
// Chirp parameters
input chirp_en,
input [LEN_WI-1:0] chirp... | 8.055543 |
module chirp_sim_tb;
localparam FMC_TCLK_PERIOD = 4069; // 245.76 MHz
localparam RESET_PERIOD = 16276; //in pSec
reg fmc_tresetn_i;
reg fmc_tclk_i;
reg fmc_tclk_fast_i;
wire fmc_tclk;
wire fmc_tclk_fast;
wire fmc_tresetn;
wire [127:0] chirp_parame... | 8.343505 |
module, since input data is sampled
// periodically, at a fixed rate. In order to control what data gets sent over the line,
// latching of input data with a valid/strobe must be done externally.
//
// See README.md for protocol specification.
//
// ------------------------------------
module chitchat_tx... | 7.005255 |
module chi_link_credit_manager (
input clk,
input resetn,
input dec_credits,
input incr_credits,
input [4:0] refill_credits,
output reg credits_available,
output [3:0] cur_credits,
output credit_maxed
);
wire credit_update;
wire [3:0] incremented_credits;
wire [3:0] decremented... | 7.581217 |
module, to store incoming flits
*
*/
module chi_rxflit_ram
#(
parameter AWIDTH = 12, // Address Width
parameter WWIDTH = 128, // Data Width
parameter RWIDTH = 32, // Data Width
parameter OREG_A = "TRUE", // Optional Port A output pipeline registers
parameter OREG_B = "TRUE" // Optional P... | 9.674427 |
module chi_txflit_mgmt (
input clk,
input rst_n,
//to/from register interface
input [14:0] own_flit,
input credit_avail,
input link_up,
input clear_ownership,
output reg read_req,
output reg flit_pending,
output reg [ 3:0] r... | 7.55464 |
module, to store flits before giving to DUT
*
*/
module chi_txflit_ram #(
parameter AWIDTH = 12, // Address Width
parameter WWIDTH = 128, // Data Width
parameter RWIDTH = 128, // Data Width
parameter OREG_A = "TRUE", // Optional Port A output pipeline registers
parameter OREG_B = "TRUE" // Optio... | 9.136395 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module chn_arb (
input clk,
input rst,
// CHN0 trn
output reg chn0_trn,
input chn0_drvn,
input chn0_reqep,
// REGIF trn
output reg regif_trn,
input regif_drvn,
input regif_reqep
);
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b0000000... | 6.84199 |
module Chn_filtr (
input Chn_in,
input clk,
output reg Chn_out = 0
);
reg [7:0] cnt_u = 0, cnt_d = 0, filtr_const = 80;
initial begin
Chn_out = 0;
cnt_u = 0;
cnt_d = 0;
filtr_const = 80;
end
always @(negedge clk) begin
if (Chn_in > 0) begin
cnt_u = cnt_u + 1;
cnt_d ... | 6.762076 |
module choice (
SW,
SEG,
AN,
LED
);
input [15:0] SW; // 16λ
output [7:0] SEG; // 7͵ƽЧ
output [7:0] AN; // 7Ƭѡźţ͵ƽЧ
output [15:0] LED; // 16λLEDʾ
assign LED = SW;
selector(
SW, SEG, AN, LED
); decoder(
SW, SEG, AN, LED
);
endmodule
| 6.696951 |
module ChooseBestFixed (
input wire iClock,
input wire iEnable,
input wire iReset,
input wire signed [15:0] FE0_residual,
input wire signed [15:0] FE1_residual,
input wire signed [15:0] FE2_residual,
input wire signed [15:0] FE3_residual,
input wire signed [15:0] FE4_residual,
outp... | 7.506079 |
module ChooseBestFixedTB;
reg clk, ena, rst;
reg signed [15:0] sample;
wire [2:0] best;
integer infile, i;
wire signed [15:0] FE0_residual;
wire signed [15:0] FE1_residual;
wire signed [15:0] FE2_residual;
wire signed [15:0] FE3_residual;
wire signed [15:0] FE4_residual;
ChooseBestFixed cbf (
... | 7.506079 |
module chooseCMD (
isData,
SPI_data,
N,
CMD1,
CMD2,
Eth_I_max,
Eth_I_min,
Eth_Temp_max,
Eth_I_work,
Eth_kor,
Eth_Imp_time,
Eth_Start,
Eth_Full_stop,
Eth_Calibr,
Eth_Ch_num
);
input isData;
input [15:0] SPI_data;
input [7:0] N;
output reg [15:0] CMD1;... | 7.911989 |
module ChooseInput (
input [31:0] Data1,
input [31:0] Data2,
input control,
output [31:0] OutData
);
assign OutData = control ? Data2 : Data1;
endmodule
| 8.636912 |
module Choosepc (
Outimm,
JPC,
PCPlus4,
PCIn,
PCSrc,
RD1,
zero
);
input [31:0] Outimm, JPC, PCPlus4, RD1;
input wire zero;
input wire [1:0] PCSrc;
output reg [31:0] PCIn;
always @(*) begin
case (PCSrc)
2'b00: begin
PCIn = PCPlus4;
end
2'b01://beq
begin... | 8.99785 |
module ChooseWriteData (
input [31:0] PC4,
input [31:0] DB,
input WrRegDSrc,
output [31:0] WriteData
);
assign WriteData = WrRegDSrc ? DB : PC4;
endmodule
| 8.528087 |
module choosewritereg (
input [4:0] rtE,
rdE,
input regwriteE,
regdstE,
output reg [4:0] writeregE
);
always @(*) begin
if (regwriteE)
if (regdstE) writeregE = rdE;
else writeregE = rtE;
else writeregE = 5'b00000;
end
endmodule
| 7.724532 |
module choose_ASK (
input [7:0] data_in,
input sel,
output [7:0] data_out
);
reg [7:0] daout;
always @(sel) begin
if (sel) daout <= data_in;
else daout <= 8'd0;
end
assign data_out = daout;
endmodule
| 6.594786 |
module choose_from_4_symbols (
input [9:0] SW,
output [9:0] LEDR,
output [6:0] HEX0
);
assign LEDR = SW;
wire [1:0] muxOut;
mux_4_1_2_bits ex0 (
SW[7:0],
~SW[9:8],
muxOut[1:0]
);
decoder_7_seg ex1 (
muxOut[1:0],
HEX0[6:0]
);
endmodule
| 7.647266 |
module choose_FSK (
input [7:0] data_in1,
input [7:0] data_in2,
input sel,
output [7:0] data_out
);
reg [7:0] daout;
always @(sel) begin
if (sel) daout <= data_in1;
else daout <= data_in2;
end
assign data_out = daout;
endmodule
| 7.063564 |
module choose_PSK (
input [7:0] data_in,
input sel,
output [7:0] data_out
);
reg [7:0] daout;
always @(sel) begin
if (sel) daout <= data_in;
else daout <= ~data_in;
end
assign data_out = daout;
endmodule
| 6.657123 |
module choose_rin (
input [4:0] rrs1,
input [4:0] rrs2,
input [4:0] irs1,
input [4:0] srs1,
input [4:0] brs1,
input [4:0] brs2,
input r,
input i,
input s,
input b,
output reg [4:0] rs1_out,
output reg [4:0] rs2_out,
output reg enrs1,
output reg enrs2
);
always ... | 7.362462 |
module FreqtoNote(
input reg [3:0] chord,
input wire [3:0] key,
output wire [15:0] notes_for_chord);
reg [3:0] note1;
reg [3:0] note2;
reg [3:0] note3;
reg [3:0] note4;
wire [3:0] C = 0;
wire [3:0] CS = 1;
wire [3:0] D = 2;
wire [3:0] DS = 3;
wire [3:0] E = 4;
wire [3:0] F = 5;
wire [3:0] F... | 6.834358 |
module ChoseByte (
input Select,
output [7:0] OutputByte,
input [7:0] InputByte1,
input [7:0] InputByte2,
output OutputByteReady,
input InputByteReady1,
input InputByteReady2
);
assign OutputByteReady = Select == 1'b0 ? InputByteReady1 : InputByteReady2;
assign OutputByte = Select == 1'... | 6.531933 |
module Chr2Bin (
chr,
bin
);
input [7:0] chr;
output reg bin;
always @(*) begin
case (chr)
8'd48: bin <= 0;
8'd49: bin <= 1;
default: bin <= 0;
endcase
end
endmodule
| 6.602952 |
module chroma_key (
input clk,
input [7:0] blue_video,
input [7:0] green_video,
input [7:0] red_video,
input [7:0] blue_comp,
input [7:0] green_comp,
input [7:0] red_comp,
output [7:0] blue_blend,
output [7:0] green_blend,
output [7:0] red_blend,
input [23:0] cipher_strea... | 6.930826 |
module chroma_qp (
qp_i,
sel_i,
qp_o
);
//---- input/output declaration -----------------------------
input [6 -1 : 0] qp_i;
input [2 -1 : 0] sel_i; // YUV
output [6 -1 : 0] qp_o;
//---- wire/reg declaration -------------------------------
reg [6 -1 : 0] qpc; // chroma qp
wire [6 ... | 6.712731 |
module chrono2 #(
// Frecuencia del reloj del sistema en Hz
parameter FREQ = 50000000
) (
input wire ck, // reloj
input wire cl, // puesta a cero (activo en alto)
input wire start, // habilitación (activo en alto)
output reg [3:0] c0, // centésimas de segundo
... | 7.692941 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/cht_comb/cht_comb.opt (
a0_pad,
a_pad,
b0_pad,
c0_pad,
c_pad,
d0_pad,
d_pad,
e0_pad,
e_pad,
f0_pad,
f_pad,
g0_pad,
g_pad,
h0_pad,
h_pad,
i0_pad,
i_pad,
j... | 6.939825 |
module chuli (
input clk,
input rst_n,
input [7:0] angle,
output reg [1:0] led
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) led <= 2'b00;
else if (angle >= 6'd45) //大于45度盲人将要摔倒
led <= 2'b01;
else led <= 2'b10;
end
endmodule
| 6.52091 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module ch_sel (
input wire clk,
input wire reset,
input wire strobe,
input wire en,
output reg req_data,
input [2:0] channels,
output reg [2:0] sel
);
//localparam IDLE = 1'b0;
//localparam COUNT = 1'b1;
//reg state;
wire data_enable = strobe && en;
always @(posedge clk) begin
... | 6.763863 |
module ci7448 (
input [3:0] a,
output reg [6:0] segmentos
);
///7 declarar clables y registros
// descripcion de circuito
always @(a) ///
begin
case (a)
4'b0000: segmentos = 7'b0111111;
4'b0001: segmentos = 7'b0000110;
4'b0010: segmentos = 7'b1011011;
4'b0011: segmentos... | 8.271579 |
module ci75155 (
input [0:2] x,
output reg [0:3] y
);
always @(y) ///
begin
case (y)
3'b000: y = 4'b1111;
3'b001: y = 4'b0111;
3'b011: y = 4'b1011;
3'b101: y = 4'b1101;
3'b111: y = 4'b1110;
3'b000: y = 4'b1111;
default: y = 4'b000;
endcase
end
... | 7.018162 |
module cia (
input clk,
input rst,
input clk_1mhz_ph1_en,
input i_cs,
input [3:0] i_addr,
input i_we,
input [7:0] i_data,
output reg [7:0] o_data,
output reg [7:0] o_pa,
input [7:0] i_pb,
output reg o_irq
);
reg [15:0] timer_a_cntr;
reg [7:0] timer_a_lo_latch;
reg [7:0... | 6.777047 |
module CIA32Bit (
input [31:0] A,
input [31:0] B,
input Cin,
output [31:0] S,
output Cout
);
wire [4:0] carry_prop;
assign carry_prop[0] = Cin;
CIA8Bit CIA8Bit0 (
A[7:0],
B[7:0],
carry_prop[0],
S[7:0],
carry_prop[1]
);
CIA8Bit CIA8Bit1 (
A[15:8],
... | 8.198513 |
module: CIA32Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CIA32Bit_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg Cin;
// Outputs
wire [31:0] S;
wire Cout;
// Instan... | 7.034873 |
module timerd (
input clk, // clock
input wr, // write enable
input reset, // reset
input tlo, // timer low byte select
input tme, // timer mid byte select
input thi, // timer high byte select
... | 6.701198 |
module CIA8Bit (
input [7:0] A,
input [7:0] B,
input Cin,
output [7:0] S,
output Cout
);
wire RCA4Bit_COUT_1;
wire RCA4Bit_COUT_2;
wire [3:0] RCA4Bit_SOUT_1;
wire [3:0] RCA4Bit_SOUT_2;
wire net0;
wire net1;
wire net2;
wire net3;
RCA4Bit RCA4Bit0 (
A[3:0],
B[3:0],
... | 7.091488 |
module: CIA8Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CIA8Bit_tb;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg Cin;
// Outputs
wire [7:0] S;
wire Cout;
// Instantiate... | 6.75526 |
module cia_block (
in1,
in2,
cin, //carry or the previous adder
cout,
sum
);
input [3:0] in1, in2;
input cin;
output [3:0] sum;
output cout;
wire [3:0] internal_sum; // sum of rca that's wired to the ha's
wire c; //cout of the rca
wire [3:0] ha_cout;
ripple_carry_adder_4_bit rc... | 7.289378 |
module cia_timerd (
input clk, // clock
input clk7_en,
input wr, // write enable
input reset, // reset
input tlo, // timer low byte select
input tme, // timer mid byte select
input thi, ... | 6.996831 |
module cic (
clock,
in_strobe,
out_strobe,
in_data,
out_data
);
//design parameters
parameter STAGES = 3;
parameter DECIMATION = 10;
parameter IN_WIDTH = 18;
//computed parameters
//ACC_WIDTH = IN_WIDTH + Ceil(STAGES * Log2(DECIMATION))
//OUT_WIDTH = IN_WIDTH + Ceil(Log2(DECIMATION) ... | 6.918107 |
module cic3r32 //----> Interface
(
input clk, // System clock
input reset, // Asynchronous reset
input signed [7:0] x_in, // System input
output signed [9:0] y_out, // System output
output reg clk2
); // Clock divider
// -----------------------------... | 6.675919 |
module cic3s32 //----> Interface
(
input clk, // System clock
input reset, // Asynchronous reset
input signed [7:0] x_in, // System input
output signed [9:0] y_out, // System output
output reg clk2
); // Clock divider
// ------------------------------... | 6.720613 |
module implements a CIC interpolator or two CIC decimators. Interpolation
// and decimation by 8-2896 is possible. RDI and TDO are the input from the mixer and
// output to the mixer for receiving and transmitting, respectively. Data is sampled
// synchronous to DCLK and 2 channels may be multiplexed. RDO and TDI are d... | 6.904081 |
module CICDecimationFilter (
clk,
din,
din_valid,
dout,
dout_valid
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Parameter declarations
parameter IN_WIDTH = 1; //Width of the input data stream
parameter TEMP_WIDT... | 6.699512 |
module CicFilter (
clk,
clken,
reset_n,
in_data,
in_valid,
out_ready,
in_error,
out_data,
in_ready,
out_valid,
out_error
);
input clk;
input clken;
input reset_n;
input [9:0] in_data;
input in_valid;
input out_ready;
input [1:0] in_error;
output [16:0] out_d... | 6.563601 |
module CicFilter_cntr_ao7 (
counter_reg_bit_1,
updown,
counter_reg_bit_2,
counter_reg_bit_0,
_,
clock,
reset_n
) /* synthesis synthesis_greybox=1 */;
output counter_reg_bit_1;
input updown;
output counter_reg_bit_2;
output counter_reg_bit_0;
input _;
input clock;
input reset_n... | 6.536613 |
module CicFilter_cntr_tnb (
counter_reg_bit_0,
counter_reg_bit_1,
_,
clock,
reset_n
) /* synthesis synthesis_greybox=1 */;
output counter_reg_bit_0;
output counter_reg_bit_1;
input _;
input clock;
input reset_n;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc =... | 6.536613 |
module CicFilter_cntr_unb (
sink_staterun1,
counter_reg_bit_0,
counter_reg_bit_1,
counter_reg_bit_2,
clock,
reset_n
) /* synthesis synthesis_greybox=1 */;
input sink_staterun1;
output counter_reg_bit_0;
output counter_reg_bit_1;
output counter_reg_bit_2;
input clock;
input reset_n;
... | 6.536613 |
module CICIP (
clk,
clken,
reset_n,
in_data,
in_valid,
out_ready,
in_error,
out_data,
in_ready,
out_valid,
out_error
);
input clk; //系统时钟/数据输入频率/FPGA工作时钟
input clken; //时钟允许信号，高电平有效
input reset_n; //复位信号，低电平有效
input [9:0] in_data; //输入数据
input in_valid; //输入数... | 7.454982 |
module Ciclo_Fetch (
input clk,
input [31:0] DirEntrada,
output reg [31:0] out,
output reg [31:0] Fetch,
output [31:0] Sal
);
reg [31:0] DirSalida;
reg [7:0] pc;
reg [7:0] MEM[149:0];
initial begin
pc = 8'd0;
end
always @(posedge clk) begin
if (DirEntrada >= 32'd0) begin
... | 8.076916 |
module cic_4stage (
clock,
reset,
dec_clk,
dec_rate,
din,
dout
);
// Input/Output bit-widths and gain bit definitions.
localparam INPUT_WIDTH = 16;
localparam OUTPUT_WIDTH = 16;
localparam GAIN_WIDTH = 28;
input wire clock;
input wire reset;
input wire dec_clk;
input wire [7:0]... | 7.215657 |
module cic_5stage (
clock,
reset,
dec_clk,
dec_rate,
din,
dout
);
// Input/Output bit-widths and gain bit definitions.
localparam INPUT_WIDTH = 16;
localparam OUTPUT_WIDTH = 16;
input wire clock;
input wire reset;
input wire dec_clk;
input wire [7:0] dec_rate;
input wire [INPUT... | 6.815097 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module cic_comb #(parameter idw = 8, odw = 9, N = 15)(
02 input clk,
03 input reset_n,
04 input in_dv,
05 input signed [idw-1:0] data_in,
06 output reg signed [odw-1:0] data_out );
07 reg signed [idw-1:0] data_reg[N-1:0];
08 integer i;
09 always @(posedge clk)
10 if (!reset_n) begin
11 ... | 6.935439 |
module cic_decim #(
parameter bw = 16,
parameter N = 4,
parameter log2_of_max_rate = 7
) (
input clock,
input reset,
input enable,
input [7:0] rate,
input strobe_in,
input strobe_out,
input [bw-1:0] signal_in,
output reg [bw-1:0] signal_out
);
localparam maxbitgain = N * l... | 7.702142 |
module cic_decimator #(
parameter WIDTH = 16,
parameter RMAX = 2,
parameter M = 1,
parameter N = 2,
parameter REG_WIDTH = WIDTH + $clog2((RMAX * M) ** N)
) (
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [WIDTH-1:0] input_tdata,
input wire ... | 6.607506 |
module cic_decim_tb;
parameter WIDTH = 25;
parameter CLK_PERIOD = 100;
parameter MAXRATE = 1000;
// testbench signals
integer in_data_file;
integer out_data_file;
integer dump;
integer cnt = 0;
integer data_out_int;
// UUT inputs
reg clk_i;
reg rst_i;
reg en_i;
reg act_i;
reg act_out_i;... | 7.500585 |
module cic_differentiator (
clock,
reset,
d_in,
d_out
);
parameter INPUT_WIDTH = 16;
parameter OUTPUT_WIDTH = 16;
localparam SHIFT = INPUT_WIDTH - OUTPUT_WIDTH;
input wire clock;
input wire reset;
input wire [INPUT_WIDTH-1:0] d_in;
output reg [OUTPUT_WIDTH-1:0] d_out;
reg [INPUT_WIDTH... | 6.909858 |
module cic_differentiator_tb;
//test vector to load data from file
parameter TEST_VECTOR_LENGTH = 500;
parameter CLK_PER_2 = 10;
parameter ENABLE_PER = 5000;
parameter STROBE_PER = 50;
parameter SIM_TIME = 3e5;
parameter INPUT_WIDTH = 16;
parameter OUTPUT_WIDTH = 16;
parameter NUM_STAGES = 4;
reg... | 6.909858 |
module low_cut (
input CLK,
input i_vld,
input [31:0] i_data,
output o_vld,
output [31:0] o_data
);
reg signed [39:0] avr = 0;
reg signed [31:0] o_reg = 0;
always @(posedge CLK) if (i_vld) o_reg <= $signed($signed(i_data) - $signed(avr[39:8]));
reg vld1 = 0;
always @(posedge CLK) vld1 <= i... | 7.998437 |
module cic_filter #(
parameter DATA_IN_WIDTH = 16,
parameter DATA_OUT_WIDTH = 16,
parameter FILTER_R = 8,
parameter FILTER_N = 5,
parameter FILTER_M = 1
) (
input reset_n,
input clk_in,
input [DATA_IN_WIDTH-1:0] data_in_I,
input [DATA_IN_WIDTH-1:0] data_in_Q,
input data_in_valid,... | 7.992447 |
module CIC_FILTER_4X2P (
IN,
CLK,
CLK_2,
CLK_4,
RES,
OUT
);
parameter BW = 11;
input CLK, CLK_2, CLK_4, RES;
input signed [BW-1:0] IN;
output signed [BW+3:0] OUT;
wire signed [BW-1:0] OUT01, OUT02, OUT03, OUT04;
POLYPHASE_PATH4 POLYPHASE_01 (
CLK,
CLK_2,
CLK_4,
... | 7.372951 |
module CIC_FILTER_4X2P_ADC_TEG (
IN,
CLK,
CLK_2,
CLK_4,
RES,
ENABLE,
OUT
);
parameter BW = 6;
input CLK, CLK_2, CLK_4, ENABLE, RES;
input signed [BW-1:0] IN;
output signed [BW+3:0] OUT;
wire signed [BW-1:0] OUT01, OUT02, OUT03, OUT04;
POLYPHASE_PATH4_ADC_TEG POLYPHASE_01 (
... | 7.372951 |
module CIC_FILTER_4X3 (
IN,
CLK,
CLK_4,
RES,
OUT
);
parameter BW = 15;
input signed [BW-1:0] IN;
input CLK, CLK_4, RES;
output signed [BW+5:0] OUT;
wire signed [BW+5:0] OUT01, OUT02, OUT03, OUT04, OUT05, OUT06, OUT_Z, ON1, ON2;
INTE_1 inte01 (
IN,
CLK,
RES,
OUT... | 7.372951 |
module CIC_FILTER_VCO (
IN,
CLK,
RES,
ENABLE,
OUT
);
parameter BW = 5;
input [BW:0] IN;
input CLK, RES, ENABLE;
output [BW-1:0] OUT;
wire [BW:0] OUT01, ON;
DFFR_6B_3 DFF01 (
IN,
CLK,
RES,
ENABLE,
OUT01,
ON
);
diff_2 diff01 (
OUT01,
C... | 8.174968 |
module CIC_FILTER_VCO_DIFFERENTIAL (
IN_p,
IN_m,
CLK,
RES,
ENABLE,
OUT
);
parameter BW = 5;
input [BW:0] IN_p, IN_m;
input CLK, RES, ENABLE;
output signed [BW:0] OUT;
wire [BW-1:0] OUT01, OUT02;
CIC_FILTER_VCO
CIC_p (
IN_p,
CLK,
RES,
E... | 8.174968 |
module CIC_FREQS_TB;
reg clk = 0;
reg rst = 0;
wire [13:0] WAVE;
wire [13:0] COS_WAVE;
reg [31:0] FREQ_WORD = 32'd343597384;
reg [31:0] DITHER_SCALE = 32'd2097151;
NCO_V4 #(
.AXIS_TDATA_WIDTH(32),
.ACCUM_WIDTH(32),
.PHASE_BITS(14), //>= AMP+2
.AMPLITUDE_BITS(14),
.BRAM(0)... | 6.773592 |
module cic_gain_bank #(
parameter WIDTH = 16,
parameter MAX_BIT_GAIN = 21
) (
input clk,
input [7:0] rate,
input [WIDTH+MAX_BIT_GAIN-1:0] data_in,
output [WIDTH-1:0] data_out
);
// N \log_{2}(RM)
function [4:0] bit_gain;
input [7:0] rate;
case (rate)
// Exact Cases
8'd1: ... | 7.020607 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module cic_integrator (
clock,
strobe,
in_data,
out_data
);
parameter WIDTH = 64;
input clock;
input strobe;
input signed [WIDTH-1:0] in_data;
output reg signed [WIDTH-1:0] out_data;
//initial out_data = 0; // this is NOT a valid RTL statement! Kirk Weedman KD7IRS
always @(posedge cl... | 6.968123 |
module cic_integrator_tb;
//test vector to load data from file
parameter TEST_VECTOR_LENGTH = 500;
parameter CLK_PER_2 = 10;
parameter ENABLE_PER = 5000;
parameter STROBE_PER = 50;
parameter SIM_TIME = 1e5;
parameter INPUT_WIDTH = 16;
parameter OUTPUT_WIDTH = 12;
reg [ INPUT_WIDTH-1:0] d_in;
wir... | 6.968123 |
module cic_integrator #(parameter idw = 8 , odw = 9)(
02 input clk,
03 input reset_n,
04 input signed [idw-1:0] data_in,
05 output reg signed [odw-1:0] data_out );
06 always @(posedge clk)
07 if (!reset_n)
08 data_out <= 'h0;
09 else //ۼӻ
10 data_out <= data_out + data_in;
11 endmodule
| 6.968123 |
module cic_interp #(
parameter bw = 16,
parameter N = 4,
parameter log2_of_max_rate = 7
) (
input clock,
input reset,
input enable,
input [7:0] rate,
input strobe_in,
input strobe_out,
input [bw-1:0] signal_in,
output reg [bw-1:0] signal_out
);
integer i;
localparam maxb... | 8.029091 |
module cic_interpolate #(
parameter WIDTH = 16,
parameter N = 4,
parameter MAX_RATE = 128
) (
input clk,
input reset,
input rate_stb,
input [$clog2(MAX_RATE+1)-1:0] rate, // +1 due to $clog2() rounding
input strobe_in,
output reg strobe_out,
input [WIDTH-1:0] signal_in,
outp... | 6.63209 |
module cic_interpolator #(
parameter WIDTH = 16,
parameter RMAX = 2,
parameter M = 1,
parameter N = 2,
parameter REG_WIDTH = 18 //WIDTH+$max(N, $clog2(((RMAX*M)**N)/RMAX))
) (
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [WIDTH-1:0] input_tdata,
... | 6.63209 |
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