code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cic_int_shifter (
rate,
signal_in,
signal_out
);
parameter bw = 16;
parameter maxbitgain = 21;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case (rate)
// Exact Cases
8'd1: ... | 6.637672 |
module with gain correction and output slicer.
//
//
/*****************************************************************************/
module cic_M256_N1_R1_iw5_0
(
input sync_reset, // reset
input clk,
input [8:0] msetting,
input s_axis_tvalid,
input [4:0] s_axis_tdata,
output s_axis_tready,
output ... | 6.5499 |
module cic_msb_adjust (
dec_rate,
msb
);
parameter WIDTH = 6'd16;
input wire [7:0] dec_rate;
output reg [5:0] msb;
always @(dec_rate) begin
case (dec_rate)
8'd8: msb <= WIDTH + 6'd15 - 6'd16;
8'd16: msb <= WIDTH + 6'd20 - 6'd16;
8'd32: msb <= WIDTH + 6'd25 - 6'd16;
... | 7.698972 |
module CIC_N1_M1_16bit_fixed (
audio_out,
rf_in,
rf_clk,
lr_clk,
reset
);
// The filter is a
// single integrator/comb CIC filter
//
// one audio sample, 16 bit, 2's complement
output reg signed [15:0] audio_out;
input signed [15:0] rf_in;
input wire rf_clk, lr_clk, reset;
reg sign... | 6.774707 |
module cic_op_fsm #(
parameter WIDTH = "mandatory", // 23
parameter CHANNELS = "mandatory" // 8
) (
input clk,
input resetn,
input enable,
output reg read_en,
output reg wr_en,
output reg [$clog2(CHANNELS)-1:0] channel
);
wire channel_en;
always @(posedge clk or posedge resetn) b... | 7.935801 |
module is configured with unsigned input and output!
module cic_simple_us #(
parameter ext_roll=0, // if set, use roll port instead of internal divider
parameter dw=16,
parameter ex=10 // decimate by 2^ex, up to 2^ex when using ext_roll
) (
input clk,
input [dw-1:0] data_in,
input data_in_gate,
input roll, //... | 7.241357 |
module cic_strober #(
parameter WIDTH = 8
) (
input clock,
input reset,
input enable,
input [WIDTH-1:0] rate, // Rate should EQUAL to your desired divide ratio, no more -1 BS
input strobe_fast,
output wire strobe_slow
);
reg [WIDTH-1:0] counter;
wire now = (counter == 1);
... | 7.241005 |
module cic_sync #(
parameter SYS_FREQ_HZ = "mandatory", // 150_000_000
parameter PDM_FREQ_HZ = "mandatory", // 3_000_000
parameter CHANNELS = "mandatory", // 8
parameter DATA_WIDTH = "mandatory", ... | 8.838767 |
module cic_top (
input wire sclk,
input wire rst_n
);
wire signed [ 7:0] data_con;
wire data_v;
wire signed [22:0] data_out;
gen_sin gen_sin_instance (
.sclk (sclk),
.rst_n (rst_n),
.data_o(data_con),
.data_v(data_v)
);
cic_interpolate cic_interpolate_insta... | 6.969173 |
module CIC_v3_tb;
reg clk = 0;
reg rst = 0;
wire [13:0] WAVE;
wire [13:0] WAVE2;
reg [31:0] FREQ_WORD = 32'd343597384;
reg [31:0] FREQ_WORD_2 = 32'd340161409;
NCO_v3 #(
.AXIS_TDATA_WIDTH(32),
.ACCUM_WIDTH(32),
.PHASE_BITS(16),
.AMPLITUDE_BITS(14)
) UUT1 (
.clk(clk),
... | 6.528065 |
module CID #(
parameter cid
) (
output [15:0] data_out
);
assign data_out = cid;
endmodule
| 7.929794 |
module cikarma (
input blok_aktif_i,
input [31:0] sayi1_i,
input [31:0] sayi2_i,
output [31:0] sonuc_o
);
reg [31:0] sonuc_r;
assign sonuc_o = sonuc_r;
always @* begin
if (blok_aktif_i) begin
sonuc_r = sayi1_i - sayi2_i;
end else begin
sonuc_r = 32'd0;
end
end... | 6.922954 |
module cilantro_rv_top (
input clk,
input rst,
input [31:0] instr_in,
output [31:0] data_out
);
// Register File
reg [31:0] reg_file[0:31];
reg [4:0] rs1, rs2, rd; // Reg address
reg [31:0] imm;
reg [6:0] opcode;
reg [31:0] PC;
// ALU Output
reg [31:0] alu_out;
reg [31:0] data_out;... | 6.736115 |
module cim_12 (
clk,
adca,
adcb,
adcc,
adcd,
outm,
adcx,
cosa,
sina,
cosb,
sinb,
sample,
// unprocessed double-integrator output
sr_out,
sr_val
);
parameter dw = 32; // data width of mon_chan output
// should be CIC input data width (18), plus 2 * log2(... | 6.911602 |
module cim_12x #(
parameter dw = 32, // data width of mon_chan output
// should be CIC input data width (18), plus 2 * log2(max sample period)
// also should match width of sr_out port
parameter scale = 18'd65536 // applies to non-downconverted channels
// (inm and outm), opportunity to use values... | 8.262206 |
module cim_16 (
clk,
din01,
cos01,
sin01,
din02,
cos02,
sin02,
din03,
cos03,
sin03,
din04,
cos04,
sin04,
din05,
cos05,
sin05,
din06,
cos06,
sin06,
din07,
cos07,
sin07,
din08,
cos08,
sin08,
sample,
// unprocessed... | 6.64126 |
module cinadd #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] opA,
input [WIDTH-1:0] opB,
input addsub,
output reg [WIDTH-1:0] result,
output reg overflow
);
reg [WIDTH-1:0] temp;
reg [WIDTH+1:0] addsub_result;
always @* begin
temp = opB ^ {WIDTH{addsub}};
end
always @* begin
... | 7.308952 |
module Cin_logic (
FS0,
FS1,
FS2,
FS3,
C0
);
input FS0, FS1, FS2, FS3;
output C0;
wire notFS1_and_FS0, notFS3_and_notFS2_and_notFS1, notFS2_and_FS0, notFS3_and_FS2_and_FS1_and_notFS0;
wire notFS0, notFS1, notFS2, notFS3;
not not1 (notFS0, FS0);
not not2 (notFS1, FS1);
not not3 (notF... | 6.506483 |
module can be interfaced to preload keys, IVs and input
// plaintext bits to obtain the corresponding ciphertext bits.
//
// Dependencies: /
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - Minor modification to initialize register C
//
/////////////////////////////////////////... | 8.217738 |
module cipher_if (
input RSTn, // Reset input
input CLK, // Clock input
input HRRDYn, // Host read ready
input HWRDYn, // Host write ready
output reg HDRE, // Host data read enable
output reg HDWE, // Host data write enable
input [7:0] HDIN,... | 6.976488 |
module calculates the positive circle coordinate Y given X
// with a radius of R
// It is not very well written, but this provides students with
// an opportunity to improve the design :-)
//
// Equation is that of a circle X^2 + Y^2 = R^2
// module calculates Y=sqrt(R^2-X^2)
// It performs no rounding...
// X and Y ar... | 7.448165 |
module top (
input CLK,
input BTN_N,
output [15:0] LED_PANEL
);
led_main #(
.FRAME_BITS(7),
.DELAY(3)
) main (
.CLK(CLK),
.resetn_btn(BTN_N),
.LED_PANEL(LED_PANEL)
);
endmodule
| 7.233807 |
module circle #(
parameter RADIUS = 35
) // default radius: 35 pixels
(
input [10:0] x,
hcount,
input [9:0] y,
vcount,
input [23:0] color,
output reg [23:0] pixel
);
reg [10:0] x_length;
reg [ 9:0] y_length;
always @* begin
x_length <= hcount - x;
y_length <= vcount - y;
... | 8.773103 |
module: circleSize
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module circleSize_tb;
// Inputs
reg [10:0] g;
reg clk;
// Outputs
wire [1:0] sizeLevel;
// Instantiate the Unit U... | 6.735971 |
module circle_buf2 (
wclk,
stb_w,
data_w,
data_gate_in,
trig_ext,
trig_internal,
trigger_location,
rclk,
stb_r,
data_r,
addr_r,
trig_out,
data_gate,
reset,
buf_count,
buf_stat
);
parameter aw = 13; // for each half of the double-buffered memory
param... | 8.082595 |
module circle_buffers #(
parameter CHANS = 7,
parameter DWIDTH = 16,
parameter AWIDTH = 14,
parameter WID_CHANS = clog2(CHANS),
parameter BUF_AW = 13
) (
input dsp_clk,
input signed [DWIDTH*CHANS-1:0] wave,
input [CHANS-1:0] wave_strobe,
output [DWIDTH*CHANS-1:0] wave_result,
ou... | 6.536146 |
module circle_visualiser (
input clk20k,
input [11:0] mic_in,
input [12:0] pixel_index,
output reg [15:0] oled_data
);
reg [12:0] counter;
reg [5:0] radius, max_radius; // from 0 to 48
reg [11:0] max_mic;
reg [6:0] x, new_x;
reg [5:0] y, new_y;
reg [15:0] screen_colour = 16'b11111_111111... | 6.595311 |
module circuit (
input [T_IO_PAIRS*2-1:0] in,
output [T_IO_PAIRS*2-1:0] out
);
assign serialPrim[0].pIn = in;
assign out = serialPrim[T_DEPTH-1].pOut;
genvar gi, gj;
for (gi = 0; gi < T_DEPTH; gi = gi + 1) begin : serialPrim
wire [T_IO_PAIRS*2-1:0] pIn;
wire [T_IO_PAIRS*2-1:0] pOut;
for (... | 6.801902 |
module top_module (
input a,
input b,
output q
); //
assign q = a & b; // Fix me
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output q,
output state
);
always @(posedge clk) begin
if (a == b) state <= a;
else state <= state;
end
assign q = (a == b) ? state : (~state);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = ~(a ^ b ^ c ^ d); // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a | b) & (c | d); // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
);
assign q = b | c;
endmodule
| 7.203305 |
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
4'h0: begin
q <= b;
end
4'h1: begin
q <= e;
end
4'h2: begin
q <= a;
end
4'h3: b... | 7.203305 |
module top_module (
input [ 2:0] a,
output [15:0] q
);
always @(*) begin
case (a)
3'd0: q <= 16'h1232;
3'd1: q <= 16'haee0;
3'd2: q <= 16'h27d4;
3'd3: q <= 16'h5a0e;
3'd4: q <= 16'h2066;
3'd5: q <= 16'h64ce;
3'd6: q <= 16'hc526;
3'd7: q <= 16'h2f19;
en... | 7.203305 |
module Circuit6288_1 (
clk,
out6287,
out6288,
out6280,
out6270,
out6260,
out6250,
out6240,
out6230,
out6220,
out6210,
out6200,
out6190,
out6180,
out6170,
out6160,
out6150,
out6123,
out5971,
out5672,
out5308,
out4946,
out4591,
... | 7.180605 |
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) begin
q <= !a;
end
endmodule
| 7.203305 |
module Circuit74181 (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
TopLevel74181 Ckt74181 (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
endmo... | 6.631759 |
module TopLevel74181 (
S,
A,
B,
M,
CNb,
F,
X,
Y,
CN4b,
AEB
);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
wire [3:0] E, D, C, Bb;
Emodule Emod1 (
A,
B,
S,
E,
Bb
);
Dmodule Dmod2 (
A,
B,
... | 6.940936 |
module top_module (
input clock,
input a,
output p,
output q
);
always @(*) begin
if (clock) begin
p <= a;
end
end
always @(negedge clock) begin
q <= a;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output [3:0] q
);
always @(posedge clk) begin
if (a) begin
q <= 4'd4;
end else begin
if (q == 4'd6) begin
q <= 0;
end else begin
q <= q + 4'd1;
end
end
end
endmodule
| 7.203305 |
module circuitMother_tb ();
reg Clk_tb, Rst_tb;
wire [31:0] Instruction_tb;
circuitMother tb1 (
Clk_tb,
Rst_tb,
Instruction_tb
);
// Clock Procedure
always begin
Clk_tb <= 0;
#100;
Clk_tb <= 1;
#100;
end
initial begin
// Start at initial
Rst_tb <= 1;
@... | 6.834565 |
module Circuito2x2manual (
input [1:0] inp
, output out
);
wire w0, w1, w2, w3;
wire L0, L1, L2, L3;
nand el0 (L0, inp[1], w2);
nand el1 (L1, w0, w2);
xnor el2 (L2, w0, w3);
or el3 (L3, inp[0], w2);
assign out = L1;
LCELL lcell_inst0 (
.in (L0)
, .out(w0)
);
LCELL lcell_i... | 6.796492 |
module circuitoEj1T3;
reg [3:0] r;
wire n1s, a1s, o1s, salida;
// Puertas logicas
not n1 (n1s, r[3]);
and a1 (a1s, n1s, r[2]);
and a2 (salida, o1s, r[0]);
or o1 (o1s, a1s, r[1]);
initial begin
$monitor($time, " | %b %b %b %b | %b", r[3], r[2], r[1], r[0], salida);
r = 0;
while (r != 'b1111... | 7.049839 |
module circuitoEj2T13;
reg [1:0] r;
wire n1s, n2s, a1s, a2s, a3s, o1s, salida;
// Puertas
not n1 (n1s, r[1]);
not n2 (n2s, r[0]);
and a1 (a1s, n1s, n2s);
and a2 (a2s, r[1], n2s);
and a3 (a3s, n1s, r[0]);
or o1 (o1s, a1s, a2s);
or o2 (salida, o1s, a3s);
initial begin
$monitor($time, " | %b... | 6.976428 |
module halfAdder (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.256462 |
module masterAdder (
s0,
s1,
s2,
s3,
a0,
b0,
a1,
b1,
a2,
b2
);
input a0, b0, a1, b1, a2, b2;
output s0, s1, s2, s3;
halfAdder HA1 (
s0,
sa,
a0,
b0
);
fullAdder FA1 (
s1,
sb,
a1,
b1,
sa
);
fullAdder FA2 (
... | 6.500378 |
module circuito_principal (
tecla,
moedas,
clk,
segmentos,
displays,
liberar,
devolver_moedas
);
//Entradas
input clk;
input [1:0] moedas;
input [3:0] tecla;
//Saidas
output [7:0] segmentos;
output [3:0] displays;
output liberar;
output reg devolver_moedas;
//Fios
wi... | 7.611957 |
module circuit_prim (
input in0,
in1,
output out0,
out1
);
assign out1 = in0 ^ in1;
assign out0 = ~in0;
endmodule
| 6.844847 |
module circulant_2 #(
parameter S0 = 1,
parameter S1 = 2,
parameter PORT_SIZE = (37 + 2),
parameter NODES_NUM = 2
) (
input [NODES_NUM*4*PORT_SIZE-1:0] data_i,
output [NODES_NUM*4*PORT_SIZE-1:0] data_o
);
genvar i;
generate
for (
i = 0; i < NODES_NUM; i = i + 1
) // input ... | 6.806726 |
module circular_barrel_shift (
output_val,
input_val,
shift_amt
);
output [39:0] output_val;
input [39:0] input_val;
input [5:0] shift_amt;
wire [39:0] shift_1, shift_2, shift_4, shift_8, shift_16;
assign shift_1 = shift_amt[0] ? (input_val >> 1 | input_val << 39) : input_val;
assign shift_2... | 7.033681 |
module circular_barrel_shift_9b (
output_val,
input_val,
shift_amt
);
output [8:0] output_val;
input [8:0] input_val;
input [3:0] shift_amt;
wire [8:0] shift_1, shift_2, shift_4, shift_8, shift_16;
assign shift_1 = shift_amt[0] ? (input_val >> 1 | input_val << 8) : input_val;
assign shift_2 ... | 7.033681 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//A- input FIFO 1
//B - input FIFO 2
module Fifo_512#(... | 7.088073 |
module circular_LUT #(
parameter DSIZE = 16
) (
input [4:0] I,
output [DSIZE-1:0] Dz
);
localparam [DSIZE-1:0]
Z00 = 45.000000000000000 * (2**DSIZE)/90,
Z01 = 26.565051177077990 * (2**DSIZE)/90,
Z02 = 14.036243467926477 * (2**DSIZE)/90,
Z03 = 7.125016348901798 * (2**DSIZE... | 6.695759 |
module circular_pointer_fifo (
clk,
rst,
push,
pop,
data_in,
full,
empty,
data_out
);
parameter WIDTH = 8;
parameter DEPTH = 8;
parameter PTRWID = $clog2(DEPTH) + 1;
input wire clk;
input wire rst;
input wire push;
input wire pop;
input wire [WIDTH-1:0] data_in;
(* kee... | 6.741485 |
module circular_pointer_fifo (
clk,
rst,
push,
pop,
data_in,
full,
empty,
data_out
);
parameter WIDTH = 8;
parameter DEPTH = 8;
parameter PTRWID = $clog2(DEPTH) + 1;
input wire clk;
input wire rst;
input wire push;
input wire pop;
input wire [WIDTH-1:0] data_in;
(* kee... | 6.741485 |
module circular_pointer_top (
clk,
rst,
start,
push,
data_in,
pop,
empty,
full,
data_out,
prop_signal
);
parameter WIDTH = `WIDTH, DEPTH = `DEPTH + 1; // bug: only supports powers of two
input clk, rst, start, push, pop;
input [WIDTH-1:0] data_in;
output empty;
outpu... | 6.741485 |
module circular_shift (
out,
in,
shift_amount
);
output [15:0] out;
input [15:0] in;
input [3:0] shift_amount;
wire [15:0] shift_1, shift_2, shift_4;
assign shift_1 = shift_amount[0] ? (in >> 1 | in << 15) : in;
assign shift_2 = shift_amount[1] ? (shift_1 >> 2 | shift_1 << 14) : shift_1;
a... | 6.652056 |
module circular_shift (
q,
d,
reset,
clk,
load
);
input reset, clk, load;
input [3:0] d;
output reg [3:0] q;
always @(posedge clk or posedge reset or posedge load) begin
if (load) q <= d;
else if (reset) q <= 0;
else begin
q <= q << 1;
q[0] <= q[3];
end
end
en... | 6.652056 |
module circular_shift_tb ();
reg reset, clk, load;
reg [3:0] d;
wire [3:0] q;
circular_shift tb (
q,
d,
reset,
clk,
load
);
initial begin
clk = 0;
reset = 1;
#20 reset = 0;
load = 1;
#30 load = 0;
end
always #5 clk = ~clk;
initial begin
#25... | 6.652056 |
module circular_shift_register_tb ();
parameter WIDTH = 4;
reg i_clk, i_rst_n;
wire [WIDTH-1:0] o_out;
circular_shift_register register (
.i_clk (i_clk),
.i_rst_n(i_rst_n),
.o_out (o_out)
);
initial begin
i_clk = 0;
i_rst_n = 0;
forever #10 i_clk = ~i_clk;
end
ini... | 6.652056 |
module circular_shift_register (
i_clk,
i_rst_n,
o_out
);
parameter WIDTH = 4;
input i_clk, i_rst_n;
output reg [WIDTH-1:0] o_out;
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) begin
o_out <= 4'b1000;
end else begin
o_out <= {o_out[0], o_out[WIDTH-1:1]};
... | 6.652056 |
module circ_buffer #(
parameter TCQ = 100,
parameter BUF_DEPTH = 5, // valid values are 5, 6, 7, and 8
parameter DATA_WIDTH = 1
) (
output [DATA_WIDTH-1:0] rdata,
input [DATA_WIDTH-1:0] wdata,
input rclk,
input wclk,
input rst
);
... | 7.124027 |
module cisc (
clk1,
clk2,
cword,
ird,
eab,
edb,
dout,
ib,
sb,
state,
di,
t1,
t2,
b,
pc,
irf,
ire,
aluout,
abus,
bbus,
clk,
reset,
clkreset
);
input clk, reset, clkreset;
output clk1, clk2;
output [20:0] cword;
output [7:... | 7.26983 |
module city_select (
input read_city,
input enable,
input [2:0] select,
output reg [1:0] city,
output city_done_out
);
//at the very beginning of the program, the user can choose one from
//the three following locations: NYC Downtown, Toronto Downtown, Missisauga
//NEED TO HAVE A CONFIRMATIO... | 7.518747 |
module spot_select (
input [8:0] select,
output reg [3:0] spot
);
always @(*) begin
case (select[8:0])
9'b000000001: spot = 4'b0000;
9'b000000010: spot = 4'b0001;
9'b000000100: spot = 4'b0010;
9'b000001000: spot = 4'b0011;
9'b000010000: spot = 4'b0100;
9'b000100000: sp... | 6.756107 |
module cjg_alu #(
parameter WIDTH = 32
) (
// sys ports
input reset,
input clk,
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input [3:0] opcode,
output [WIDTH-1:0] result,
output c,
n,
v,
z,
// dft
input scan_in0,
input scan_en,
input test_mode,
out... | 6.62259 |
module cjg_mem_stack #(
parameter WIDTH = 32,
DEPTH = 32,
ADDRW = 5
) (
input clk,
input reset,
input [WIDTH-1:0] d,
input [ADDRW-1:0] addr,
input push,
input pop,
output reg [WIDTH-1:0] q,
// dft
input scan_in0,
input scan_en,
input test_mode,
output sc... | 6.855294 |
module cjg_shifter #(
parameter WIDTH = 32,
MOD_WIDTH = 6
) (
input reset,
input clk,
input signed [WIDTH-1:0] operand,
input carry_in,
input [2:0] opcode,
`ifdef USE_MODIFIER
input [MOD_WIDTH-1:0] modifier,
`endif
output reg [WIDTH-1:0] result,
output reg carry_out,
// df... | 8.017293 |
module cjg_stack #(
parameter WIDTH = 32,
DEPTH = 16
) (
input clk,
input reset,
input [WIDTH-1:0] d,
input push,
input pop,
output [WIDTH-1:0] q,
// dft
input scan_in0,
input scan_en,
input test_mode,
output scan_out0
);
reg [WIDTH-1:0] stack[DEPTH-1:0];
i... | 6.96334 |
module ckey_led (
input wire [3:0] KEY,
output wire [3:0] LED
);
assign LED = KEY;
endmodule
| 7.54497 |
module ck_div (
input ck_in,
output ck_out,
input sys_rst_i
//output locked;
);
parameter DIV_BY = 1;
parameter MULT_BY = 1;
wire ck_fb;
//DCM #(
// .CLKDV_DIVIDE(DIV_BY),
// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
// .DUTY_CYCLE_CORRECTI... | 6.788624 |
module ck_rst_tb (
output reg clk, // semnal de ceas
output reg rst_n // semnal de reset asincron, activ low
);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
rst_n <= 1'b1;
@(posedge clk);
rst_n <= 1'b0;
@(posedge clk);
@(posedge clk);
rst_n <= 1'b... | 7.459768 |
module cl (
output wire out,
input wire a,
b,
input wire [1:0] s
);
wire c00, c01, cxor, cnot; // DECLARANDO CABLES DE SALIDA PARA CADA PUERTA RESPECTIVAMENTE
and and1 (c00, a, b); //DECLARANDO PUERTA AND
or or1 (c01, a, b); //DECLARANDO PUERTA OR
xor puertaxor (cxor, a, b); //DECLARANDO PU... | 7.239388 |
module carry_look_ahead_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit cla... | 6.511278 |
module carry_look_ahead_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b;
assign g = a & b;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & g[0]) | p[1] & p[0] & ... | 6.511278 |
module carry_look_ahead_16bit_tb;
reg [15:0] a, b;
reg cin;
wire [15:0] sum;
wire cout;
carry_look_ahead_16bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
a = 0;
b = 0;
cin = 0;
#20 a = 16'd2;
b = 16'd2;
cin = 1'd1;
... | 6.511278 |
module cla128 (
a,
b,
ci,
s,
co
); //single 128 bit carry lookahead adder = 32 cla4 modules
input [127:0] a, b;
input ci;
output [127:0] s;
output co;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c... | 7.250984 |
module CLA16bits (
input wire [15:0] A,
input wire [15:0] B,
input wire c,
output wire [15:0] sum,
output wire [16:1] carry
);
wire [3:0] pp;
wire [3:0] gg;
wire [4:1] mc;
wire [16:1] mmc;
wire p;
wire g;
assign carry[4] = mc[1];
assign carry[8] = mc[2];
assign carry[12] = mc[3]... | 7.799033 |
module CLA2 (
input [3:0] A,
B,
input c0,
output GG,
PP,
c4,
output [3:0] S
);
wire [4:0] cc;
genvar i;
generate
for (i = 0; i <= 3; i = i + 1) begin : row
assign #(86) S[i] = A[i] ^ B[i] ^ cc[i];
assign #(62) cc[(i+1)] = ((A[i]) & (B[i])) | ((A[i]) & (cc[i])) | ((B[i])... | 7.086682 |
module CLA2Lvl (
A,
B,
ci,
co,
S
);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
input [15:0] A;
input [15:0] B;
wire [4:0] C;
wire [3:0] GG;
wire [3:0] PG;
output [15:0] S;
input ci;
output co;
AOI21X1 _06_ (
.A(PG[0]),
.B(ci),
.C... | 7.121285 |
module CLA2Lvl(A, B, ci, co, S);
input [15:0] A, B;
input ci;
output co;
output [15:0] S;
wire [4:0] C;
wire [3:0] PG, GG;
assign C[0] = ci;
assign co = C[4];
genvar i;
generate
for(i = 0; i < 4; i = i + 1 ) begin: addbit
assign C[i + 1] = GG[i] | (PG[i] & C[i]);
CLA bit(.A(A[(i+1)*4 - 1:i * 4]... | 6.773445 |
module cla32 (
pc,
x1,
x2,
p4
);
input [31:0] pc;
input [31:0] x1;
input [31:0] x2;
output [31:0] p4;
//reg [31:0] adr;
assign p4 = pc + 32'h4;
//assign adr = p4 + offset;
endmodule
| 7.388014 |
module CLA32bits (
input wire [31:0] A,
input wire [31:0] B,
input wire op,
output wire [31:0] sum,
output wire sf,
output wire cf,
output wire of
);
wire [31:0] c_B;
wire [32:1] carry;
wire p; //useless
wire g;
xor (c_B[0], op, B[0]);
xor (c_B[1], op, B[1]);
xor (c_B[2], o... | 7.511568 |
module: CLA32Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CLA32Bit_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg Cin;
// Outputs
wire [31:0] S;
wire Cout;
// Instan... | 8.224726 |
module cla32_ov (
a,
b,
ci,
s,
co_prev,
co
);
input [31:0] a, b; //32bits 2 input
input ci; //carry in
output [31:0] s; //32bits sum(output)
output co_prev;
output co; //carry out
wire c1, c2, c3, c4, c5, c6, c7; //use 7 wires
cla4 U0_cla4 (
.a (a[3:0]),
.b (b[3:... | 7.166311 |
module cla32TB ();
reg [31:0] a = 32'd0;
reg [31:0] b = 32'd0;
reg carryInput = 1'b0;
wire [31:0] sum;
wire [0:0] carryOutput;
cla32 cla1 (
.a(a),
.b(b),
.carryInput(carryInput),
.sum(sum),
.carryOutput(carryOutput)
);
initial begin
$monitor("a = %d, b = %d, carry-... | 6.720622 |
module to make 8 bits or 16 bits ... CLA, should use Connect this signal to CLA_Logic
// PG: group generate, If you want to Instantiation this module to make 8 bits or 16 bits ... CLA, should use Connect this signal to CLA_Logic
module CLA4(
input [3 : 0] A, B,
input Ci,
output [3 : 0] S,
output C... | 7.571611 |
module cla4b (
a,
b,
cin,
sum,
G,
P
);
localparam w = 4; //width
input [w-1:0] a, b;
input cin;
output [w-1:0] sum;
output G, P;
wire [w-1:0] a, b, sum, g, p;
wire [w-1:1] carry;
wire cin, cout, G, P;
cgl4b cgl_u (
cin,
g,
p,
carry,
G,
P... | 7.043932 |
module CLA4bits (
input wire [3:0] A,
input wire [3:0] B,
input wire c,
output wire [3:0] sum,
output wire [4:1] carry,
output wire p,
output wire g
);
wire [3:0] pp;
wire [3:0] gg;
PFA pf0 (
A[0],
B[0],
c,
sum[0],
pp[0],
gg[0]
);
PFA pf1 (
... | 7.731846 |
module cla4bit (
input [3:0] a,
input [3:0] b,
output [3:0] r,
input cin,
output cout
);
wire [3:0] c, g, p;
// Gi=Ai.Bi
assign g = a & b;
// Pi=Ai^Bi
assign p = a ^ b;
// Ci=Gi+Pi.Ci-1
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & g[0]) | (p[1... | 7.135215 |
module cla_adder (
a,
b,
c_in,
c_out,
sum
);
parameter width = 4;
input [width-1:0] a, b;
input c_in;
output [width-1:0] sum;
output c_out;
wire [width:0] c_int;
wire [width-1:0] a, b, sum;
wire c_in, c_out, G, P;
assign c_int[0] = c_in;
genvar i;
generate
for (i = 0; i ... | 7.282972 |
module cla4_ov (
a,
b,
ci,
s,
c3,
co
); // to detect Overflow
input [3:0] a, b; //input a, b
input ci; //input carry in
output [3:0] s; //output sum
output c3, co; //output carry out
wire c1, c2; //use 2 wires
fa_v2 U0_fa (
.a (a[0]),
.b (b[0]),
.ci(ci),
... | 6.770417 |
module cla64 (
a,
b,
ci,
s,
co
); //single 128 bit carry lookahead adder = 32 cla4 modules
input [63:0] a, b;
input ci;
output [63:0] s;
output co;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15;
cla4 cla4_1 (
a[3:0],
b[3:0],
ci,
s[3:0],
... | 8.059964 |
module finaladderr (
output Si,
input ai,
bi,
Ci
);
wire w;
xor (w, ai, bi);
xor (Si, w, Ci);
endmodule
| 7.712775 |
module calcblock (
output G,
P,
input Gi,
Pi,
Gip,
Pip
);
wire w;
and (w, Pi, Gip);
or (G, w, Gi);
and (P, Pi, Pip);
endmodule
| 8.025708 |
module dff (
d,
clk,
clear,
q
);
input d, clk, clear;
output reg q;
always @(posedge clk) begin
if (clear == 1) q <= 0;
else q <= d;
//$display("%d\n",$time);
end
endmodule
| 7.361383 |
module cla8 (/*AUTOARG*/
G, //8 bit
P, //8 bit
cin,//1 bit
cout,//1 bit
Pout,//1 bit
Gout,//1 bit
) ;
input [8-1:0] G, P;
input cin;
output [8-1:0] cout;
wire pw, gw;
output Pout, Gout;
assign cout[0] = G[0] | (P[0]... | 7.591078 |
module CLA8bit (
in1,
in2,
sum,
cin,
cout
);
input [7:0] in1, in2;
input cin;
output [7:0] sum;
output cout;
wire cnxt;
CLA_N_bit #4 nbit_cla_inst3to0 (
.in1 (in1[3:0]),
.in2 (in2[3:0]),
.sum (sum[3:0]),
.cin (cin),
.cout(cnxt)
);
CLA_N_bit #4 nbit_c... | 7.011248 |
module ha (
output p,
g,
input a,
b
);
and G1 (g, a, b);
xor G3 (p, a, b);
endmodule
| 7.833251 |
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