code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fa(output s,c
input a,b,c0
);
wire p1,g1,g;
ha HA1(p1,g1,a,b),
HA2 (s,g,p1,co);
or G1 (c,g,g1);
endmodule
| 7.227385 |
module ClaAdder #(
parameter INPUT_BIT_WIDTH = 8
) (
input [INPUT_BIT_WIDTH-1:0] InputA,
input [INPUT_BIT_WIDTH-1:0] InputB,
input InputCarry,
output [INPUT_BIT_WIDTH-1:0] Sum,
output OutputCarry
);
// Internal state
wire [INPUT_BIT_WIDTH-1:0] CarryPropagate, CarryGenerate;
wire [INPUT_BI... | 8.563522 |
module claAdder4 (
input [3:0] in_a,
input [3:0] in_b,
input c_in,
output [3:0] s,
output c_out
);
wire [3:0] p, g, c;
// Level 1
assign c[0] = c_in;
assign p[3:0] = in_a[3:0] ^ in_b[3:0];
assign g[3:0] = in_a[3:0] & in_b[3:0];
// Level 2
assign c[1] = g[0] | (p[0] & c_... | 6.729129 |
module CLAAdder8b_TB ();
reg [7:0] A, B, correctS;
reg [8:0] Sum; // Variável responsável por armazenar a soma A + B
reg CIN, correctCOUT;
wire COUT;
wire [7:0] S;
integer errors, i, j;
// task que verifica se a saída do módulo é igual ao valor esperado
task Check;
input [7:0] xpectS;
input ... | 6.73054 |
module: adder_4bit_cla
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module adder_4bit_cla_tb();
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire Cout;
adder_4bit_cla uut(.sum(sum), .Cout(C... | 7.74015 |
module CLAHE_AXI (
input ACLK_in,
input ARESTN_in,
input [7:0] TDATA_in,
input TSTRB_in,
input TLAST_in,
input TVALID_in,
input TUSER_in,
output TREADY_out,
input [10:0] width_in,
input [10:0] height_in,
input [15:0] constract_th_in,
input CLAHE_EN,
output ACLK_out,... | 6.894805 |
module claLogicBlock (
G,
P,
C_in,
C_out
);
// input / output instantiation
input [3:0] G, P;
input C_in;
output [3:0] C_out;
// Determine Carry In's per respective full adder
// c1 = g0 + p0*c0
wire pc0_nand, pc0_and;
nand2 nand_pc0 (
.in1(P[0]),
.in2(C_in),
.out(pc... | 6.73622 |
module clampSPositive #(
parameter INW = 16, // -32768..+32767
parameter OUTW = 8 // 0..+255
) (
input signed [ INW-1:0] valueIn,
output [OUTW-1:0] valueOut
);
// Neg Sign => 0
wire isPos = !valueIn[INW-1];
wire [OUTW-1:0] andStage = {OUTW{isPos}};
// Pos > 255 => ... | 6.804764 |
module clampSRange #(
parameter INW = 16, // -32768..+32767
parameter OUTW = 8 // -128..+127
) (
input signed [ INW-1:0] valueIn,
output signed [OUTW-1:0] valueOut
);
// Overflow
wire overF = |valueIn[INW-2:OUTW-1];
wire isOne = &valueIn[INW-2:OUTW-1];
//
wire sgn = valueIn[INW-1];
... | 7.108638 |
module clampUPositive #(
parameter INW = 16, // 0..+65535
parameter OUTW = 8 // 0..+255
) (
input [ INW-1:0] valueIn,
output [OUTW-1:0] valueOut
);
wire isNZero = |valueIn[INW-1:OUTW];
wire [OUTW-1:0] orStage = {OUTW{isNZero}};
assign valueOut = valueIn[OUTW-1:0] | orSta... | 7.299521 |
module */
/*author:carloy */
/*version:v0.0 */
/*date:2022/2/18 */
/****************************/
module clarke #(parameter width=32)
(
input clk,
input rst_n,
input [width-1:0] ia,
input [width-1:0] ib,
input [width... | 7.749522 |
module clark_tr (
input wire rstn,
input wire clk,
input wire i_en,
input wire signed [15:0] i_ia,
i_ib,
i_ic, // range -8191 ~ 8191
output reg o_en,
output reg signed [15:0] o_ialpha,
o_ibeta
);
// registers for pipel... | 7.728468 |
module clasficador_flujo (
input clk,
input [7:0] cola_sn,
cola_eo,
input [4:0] c_29,
c_17,
output reg flujo_alto
);
reg siguiente;
wire clock;
clk_divider(
clk, clock
);
always @(posedge clock) flujo_alto <= siguiente;
always @(*)
case (flujo_alto)
0: if (c_29 =... | 6.634241 |
module classic16 (
input [15:0] a,
input [15:0] b,
output [31:0] out
);
wire [15:0] out1, out2, out3, out4, out5, out6, out7, out8;
classic8 w1 (
a[7:0],
b[7:0],
out1[15:0]
);
classic8 w2 (
a[15:8],
b[7:0],
out2[15:0]
);
classic8 w3 (
a[7:0],
b[... | 7.042822 |
module classic2 (
input [1:0] a,
input [1:0] b,
output [3:0] out
);
wire w1, w2, w3;
wire carry1, carry2;
and #1 a1 (out[0], a[0], b[0]);
and #1 a2 (w1, b[0], a[1]);
and #1 a3 (w2, b[1], a[0]);
halfadder h1 (
w1,
w2,
out[1],
carry1
);
and #1 a4 (w3, a[1], b[1]);
h... | 7.188652 |
module classic32 (
input [31:0] a,
input [31:0] b,
output [63:0] out
);
wire [31:0] out1, out2, out3, out4, out5, out6, out7, out8;
classic16 w11 (
a[15:0],
b[15:0],
out1[31:0]
);
classic16 w12 (
a[31:16],
b[15:0],
out2[31:0]
);
classic16 w13 (
a[15:0... | 6.866921 |
module classic4 (
input [3:0] a,
input [3:0] b,
output [7:0] out
);
wire [3:0] out1, out2, out3, out4, out5, out6, out7, out8;
classic2 c1 (
a[1:0],
b[1:0],
out1[3:0]
);
classic2 c2 (
a[3:2],
b[1:0],
out2[3:0]
);
classic2 c3 (
a[1:0],
b[3:2],
... | 7.673109 |
module classic8 (
input [ 7:0] a,
input [ 7:0] b,
output [15:0] out
);
wire [7:0] out1, out2, out3, out4, out5, out6, out7, out8;
classic4 c11 (
a[3:0],
b[3:0],
out1[7:0]
);
classic4 c12 (
a[7:4],
b[3:0],
out2[7:0]
);
classic4 c13 (
a[3:0],
b[7:4... | 7.627524 |
module classify (
opcode,
is_r_type,
is_i_type,
is_j_type
);
input wire [5:0] opcode;
output wire is_r_type;
output wire is_i_type;
output wire is_j_type;
// R-type: addu, div, mfhi, mflo, sll, sra, subu, jr, syscall, break
// Instructions under "SPECIAL" opcode: addu, div, mfhi, mflo, sra,... | 7.090525 |
module dcdr24 (
input x,
y,
en,
output d0,
d1,
d2,
d3
);
assign d0 = en & ~x & ~y;
assign d1 = en & ~x & y;
assign d2 = en & x & ~y;
assign d3 = en & x & y;
endmodule
| 7.406481 |
module class_bit (
clk,
rst,
we,
re,
hit,
write_addr,
access_addr,
classificationBit
);
input clk;
input rst;
input re;
input we;
input hit;
input [4:0] write_addr;
input [4:0] access_addr;
output reg [31:0] classificationBit;
reg classification_bit[0:31];
///////... | 7.184789 |
module class_ovc_table #(
parameter C = 4, //number of class
parameter V = 4, //VC number per port
parameter CVw = (C == 0) ? V : C * V,
parameter [CVw-1:0] CLASS_SETTING = {CVw{1'b1}} // shows how each class can use VCs
) (
class_in,
candidate_ovcs
);
function integer log2;
inp... | 7.28365 |
module vc_priority_based_dest_port #(
parameter P = 5,
parameter V = 4
) (
dest_port,
vc_pririty
);
localparam P_1 = (P - 1), OFFSET = V / (P_1);
input [P_1-1 : 0] dest_port;
reg [V-1 : 0] vc_pririty_init;
output [V-1 : 0] vc_pririty;
genvar i;
integer j;
generate
if (P_1 == V) beg... | 8.05564 |
module clas_4bit (
sel,
a,
b,
result,
c_in,
c_out
);
input sel;
input [3:0] a, b;
input c_in;
output c_out;
output [3:0] result;
wire [3:0] b_bits;
wire [3:0] carry;
inverting_bit leaf_0 (
.data(b),
.sel (sel),
.out (b_bits)
);
clb block_0 (
.a(a),
... | 7.471441 |
module clb (
c_in,
a,
b,
c_out
); //Carry Look-Ahead Block
input c_in;
input [3:0] a;
input [3:0] b;
output [3:0] c_out;
wire [3:0] g; //Generation Signal
wire [3:0] p; //Propagation Signal
wire [3:0] c; //for calc carry
//Generation
and g1 (g[0], a[0], b[0]);
and g2 (g[1], a[1... | 6.589184 |
module adder (
a,
b,
c_in,
sum
); //1-Bit Adder Without Carry_Out
input a, b, c_in;
output sum;
wire s1;
//SUM
xor sum1 (s1, a, b);
xor sum2 (sum, s1, c_in);
endmodule
| 7.4694 |
module clas_8bit (
sel,
a,
b,
result,
c_in,
c_out
);
input sel;
input c_in;
input [7:0] a, b;
output [7:0] result;
output c_out;
wire carry;
clas_4bit unit_0 (
.a(a[3:0]),
.b(b[3:0]),
.sel(sel),
.result(result[3:0]),
.c_in(c_in),
.c_out(carry)
... | 7.929564 |
module clas_16bit (
sel,
a,
b,
result,
c_in,
c_out
);
input sel;
input c_in;
input [15:0] a, b;
output [15:0] result;
output c_out;
wire carry;
clas_8bit unit_0 (
.a(a[7:0]),
.b(b[7:0]),
.sel(sel),
.result(result[7:0]),
.c_in(c_in),
.c_out(carr... | 7.542056 |
module clas_32bit (
sel,
a,
b,
result,
c_out
);
input sel;
input [31:0] a, b;
output [31:0] result;
output c_out;
wire carry;
clas_16bit unit_0 (
.a(a[15:0]),
.b(b[15:0]),
.sel(sel),
.result(result[7:0]),
.c_in(sel),
.c_out(carry)
);
clas_16bit ... | 8.272762 |
module clas_4bit (
sel,
a,
b,
result,
c_out
);
input sel;
input [3:0] a, b;
output c_out;
output [3:0] result;
wire [3:0] b_bits;
wire [3:0] carry;
inverting_bit leaf_0 (
.data(b),
.sel (sel),
.out (b_bits)
);
clb block_0 (
.a(a),
.b(b_bits),
... | 7.471441 |
module clb (
c_in,
a,
b,
c_out
); //Carry Look-Ahead Block
input c_in;
input [3:0] a;
input [3:0] b;
output [3:0] c_out;
wire [3:0] g; //Generation Signal
wire [3:0] p; //Propagation Signal
wire [3:0] c; //for calc carry
//Generation
and g1 (g[0], a[0], b[0]);
and g2 (g[1], a[1... | 6.589184 |
module adder (
a,
b,
c_in,
sum
); //1-Bit Adder Without Carry_Out
input a, b, c_in;
output sum;
wire s1;
//SUM
xor sum1 (s1, a, b);
xor sum2 (sum, s1, c_in);
endmodule
| 7.4694 |
module CLA_16 (
input [15 : 0] A,
B,
input Ci,
output [15 : 0] sum,
output cout
);
wire PG0, PG1, PG2, PG3;
wire GG0, GG1, GG2, GG3;
wire c1, c2, c3;
CLA4 CLA_inst_1 (
.A (A[3 : 0]),
.B (B[3 : 0]),
.Ci(Ci),
.S (sum[3 : 0]),
.Co(),
.PG(PG0),
.GG(GG0)... | 6.903294 |
module
*/
module cla_16b(A, B, C_in, S, C_out);
// declare constant for size of inputs, outputs (N)
parameter N = 16;
input [N-1: 0] A, B;
input C_in;
output [N-1:0] S;
output C_out;
//Carry outs for each bit
wire C_out0, C_out1, C_out2, G0, P0, G1, P1, G2, P2, G3,... | 7.789228 |
module CLA_16bits (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire [3:0] p0, p1, p2, p3, g0, g1, g2, g3, g4;
wire c1, c2, c3, c4;
assign p0 = a[3:0] ^ b[3:0],
p1 = a[7:4] ^ b[7:4],
p2 = a[11:8] ^ b[11:8],
p3 = a[15:12] ^ b... | 6.861639 |
module: CLA_16bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CLA_16bits_tb;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// ... | 8.947878 |
module cla_16bit_augmented (
input [15:0] in1,
input [15:0] in2,
input c_in,
output [15:0] s,
output c_out,
output p_out,
output g_out
);
wire [4:0] c; // wires for connecting carries from lookahead carry unit to the 4-bit CLAs
wire [3:0] p, g; // wires for connecting block propagate a... | 10.501894 |
module CLA_16bit_ripple (
input [15:0] in1,
input [15:0] in2,
input c_in,
output [15:0] sum,
output c_out
);
wire [2:0] carry; // wires for rippling internal carries
// 16 bit adder by cascading 4 4bit CLAs and ripple the carry
CLA_4bit cla1 (
.in1 (in1[3:0]),
.in2 (in2[3:0]),... | 7.118705 |
module CLA_16bit_rippleTestbench;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg c_in;
// Outputs
wire [15:0] sum;
wire c_out;
// Instantiate the Unit Under Test (UUT)
CLA_16bit_ripple uut (
.in1 (in1),
.in2 (in2),
.c_in (c_in),
.sum (sum),
.c_out(c_out)
);
init... | 7.118705 |
module CLA_16bit_withLCU (
input [15:0] in1,
input [15:0] in2,
input c_in,
output [15:0] sum,
output c_out,
output p,
output g
);
wire [4:1] carry; // wires for connecting carries from lookahead carry unit to the 4-bit CLAs
wire [3:0] P, G; // wires for connecting block propagate and g... | 6.977328 |
module CLA_16bit_withLCUTestbench;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg c_in;
// Outputs
wire [15:0] sum;
wire c_out;
wire p;
wire g;
// Instantiate the Unit Under Test (UUT)
CLA_16bit_withLCU uut (
.in1(in1),
.in2(in2),
.c_in(c_in),
.sum(sum),
.c_out(c_ou... | 6.977328 |
module cla_16b_bench;
reg [16:0] A;
reg [16:0] B;
reg [16:0] Sumcalc;
reg C_in;
wire [15:0] SUM;
wire CO;
wire Clk;
//2 dummy wires
wire rst;
wire err;
clkrst my_clkrst (
.clk(Clk),
.rst(rst),
.err(err)
);
cla_16b DUT (
.A(A[15:0... | 6.674277 |
module CLA_16b_tb ();
wire [16:0] out0;
reg [15:0] in0;
reg [15:0] in1;
reg in2;
integer i, file, mem, temp;
CLA_16b U0 (
in0,
in1,
in2,
out0
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./CLA_16b.vcd");
$dumpvars(0, CLA_16b_tb);
file = ... | 7.396192 |
module CLA_16_4_tb ();
reg [15:0] A = 0, B = 0;
wire [15:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 16'h00FF;
#30 A = 16'h0000;
#30 A = 16'h80FF;
#30 A = 16'h0000;
#30 A = 16'h00FF;
#30 A = 16'h0000;
#30 A = 16'h1111;
end
initial begin ... | 7.408836 |
module CLA_16_8_tb ();
reg [15:0] A = 0, B = 0;
wire [15:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 16'h00FF;
#30 A = 16'h0000;
#30 A = 16'h80FF;
#30 A = 16'h0000;
#30 A = 16'h00FF;
#30 A = 16'h0000;
#30 A = 16'h1111;
end
initial begin ... | 7.623868 |
module CLA_16_bit_lookahead (
a,
b,
cin,
cout,
sum
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire [3:0] c;
wire [3:0] p, g;
wire blockp, blockg;
CLA_4_bit_block cla1 (
a[3:0],
b[3:0],
cin,
p[0],
g[0],
sum[3:0]
);
CLA_4_bi... | 7.468218 |
module: CLA_16_bit_lookahead
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cla_16_bit_lookahead_testbench;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg cin;
// Outputs
wire co... | 8.296699 |
module CLA_16_bit_ripple (
a,
b,
cin,
cout,
sum
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire [2:0] c;
CLA_4_bit cla1 (
a[3:0],
b[3:0],
cin,
c[0],
sum[3:0]
);
CLA_4_bit cla2 (
a[7:4],
b[7:4],
c[0],
c[1],
... | 7.186315 |
module: CLA_16_bit_ripple
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cla_16_bit_ripple_testbench;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg cin;
// Outputs
wire cout;
w... | 7.645126 |
module carry_look_ahead_4bit_acc_0 (
a,
b,
cin,
sum,
cout
);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
input cin;
output cout;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15;
AND2X1 U1 (
.A(a[3]),
.B(b[3]),
.Y(n12)
);
INVX1 U2 (
... | 6.511278 |
module carry_look_ahead_4bit_acc_1 (
a,
b,
cin,
sum,
cout
);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
input cin;
output cout;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15;
AND2X1 U1 (
.A(a[3]),
.B(b[3]),
.Y(n12)
);
INVX1 U2 (
... | 6.511278 |
module carry_look_ahead_4bit_acc_2 (
a,
b,
cin,
sum,
cout
);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
input cin;
output cout;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15;
AND2X1 U1 (
.A(a[3]),
.B(b[3]),
.Y(n12)
);
INVX1 U2 (
... | 6.511278 |
module carry_look_ahead_4bit_acc_3 (
a,
b,
cin,
sum,
cout
);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
input cin;
output cout;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15;
AND2X1 U1 (
.A(a[3]),
.B(b[3]),
.Y(n12)
);
INVX1 U2 (
... | 6.511278 |
module carry_look_ahead_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a;
input [15:0] b;
output [15:0] sum;
input cin;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit_acc_0 cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carr... | 6.511278 |
module carry_look_ahead_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit_app cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit... | 6.511278 |
module cla_2 (
a,
b,
c_in,
g_out,
p_out,
s
);
input [1:0] a, b;
input c_in;
output g_out, p_out;
output [1:0] s;
wire [1:0] g, p;
wire c_out;
add add0 (
a[0],
b[0],
c_in,
g[0],
p[0],
s[0]
);
add add1 (
a[1],
b[1],
c_out,
... | 6.607265 |
module cla_32bit (
S,
c32,
a,
b,
c0
);
input [31:0] a, b;
input c0;
output [31:0] S;
output c32;
wire [31:0] g, p;
wire c8, c16, c24, G0, P0, G1, P1, G2, P2, G3, P3, c8temp, c161, c162, c241, c242, c243, c321, c322, c323, c324;
// calculate all the g' --- only use bits 0-7
and32 ... | 6.703777 |
module CLA_32_4 (
input [31:0] a_inp,
input [31:0] b_inp,
output reg [31:0] s_out,
output reg c_out,
input clock,
input reset
);
wire Cin_1, Cin_2, Cin_3, Cin_4, Cin_5, Cin_6, Cin_7, Cin_8;
wire Cout_1, Cout_2, Cout_3, Cout_4, Cout_5, Cout_6, Cout_7,... | 7.993192 |
module CLA_32_4_tb ();
reg [31:0] A = 0, B = 0;
wire [31:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 32'h00FF_00FF;
#30 A = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 A = 32'h8080_8080;
#30 A = 32'h0000_0000; // Making inp... | 7.828759 |
module CLA_32_8_tb ();
reg [31:0] A = 0, B = 0;
wire [31:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 32'h00FF_00FF;
#30 A = 32'h0000_0000; // Making input = 0 so that next transition can be noted
#30 A = 32'h8080_8080;
#30 A = 32'h0000_0000; // Making inp... | 7.486768 |
module CLA_32_plus4 (
X,
S,
En
);
input [31:0] X;
input En;
output [31:0] S;
assign S = X + 'b00000000000000000000000000000100;
endmodule
| 7.418066 |
module CLA_32_plus4_TEST;
reg [31:0] X;
wire [31:0] S;
CLA_32_plus4 CLA_32_plus4_test (
.X(X),
.S(S)
);
initial begin
;
X = 'b00000000000000000000000000000100;
#20;
X = 'b00000000000000000000000000000000;
#20;
X = 'b00000000000000000000000000001000;
end
endmodule
| 6.788531 |
module cla_4 (
a,
b,
c_in,
g_out,
p_out,
s
);
input [3:0] a, b;
input c_in;
output g_out, p_out;
output [3:0] s;
wire [1:0] g, p;
wire c_out;
cla_2 cla0 (
a[1:0],
b[1:0],
c_in,
g[0],
p[0],
s[1:0]
);
cla_2 cla1 (
a[3:2],
b[3:2],
... | 7.412617 |
module
*/
module cla_4b(A, B, C_in, S, C_out, G, P);
// declare constant for size of inputs, outputs (N)
parameter N = 4;
input [N-1: 0] A, B;
input C_in;
output [N-1:0] S;
output C_out, G, P;
//Carry outs for each bit
wire C_out0, C_out1, C_out2;
//Get carry ... | 7.789228 |
module cla_4bit_augmented (
input [3:0] in1,
input [3:0] in2,
input c_in,
output [3:0] s,
// output c_out,
output p_out,
output g_out
);
//////////////////// calculate bitwise generate and propogate ////////////////////
// pi --> in1 ^ in2
// gi --> in1 & in2
wire [3:0] p, g, c; ... | 7.549205 |
module: CLA_4bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CLA_4bits_tb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
// Insta... | 8.591102 |
module CLA_4bitTestbench;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg c_in;
// Outputs
wire [3:0] sum;
wire c_out;
// Instantiate the Unit Under Test (UUT)
CLA_4bit uut (
.in1 (in1),
.in2 (in2),
.c_in (c_in),
.sum (sum),
.c_out(c_out)
);
initial begin
$moni... | 7.804521 |
module CLA_4bit_augmented (
input [3:0] in1,
input [3:0] in2,
input c_in,
output [3:0] sum,
output p,
output g
);
/*
Logic:
G[i] = in1[i] & in2[i], 0 <= i <= 3
P[i] = in1[i] ^ in2[i], 0 <= i <= 3
Take c_in to be carry[0] then
sum[i] = P[i] ^ carry[i], 0 <= i <= 3
carry[i] = G[i-1] |... | 7.93351 |
module CLA_4bit_augmentedTestbench;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg c_in;
// Outputs
wire [3:0] sum;
wire p;
wire g;
// Instantiate the Unit Under Test (UUT)
CLA_4bit_augmented uut (
.in1(in1),
.in2(in2),
.c_in(c_in),
.sum(sum),
.p(p),
.g(g)
);
... | 7.93351 |
module CLA_4_bit (
a,
b,
cin,
cout,
sum
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign g[0] = a[0] & b[0];
assign g[1] = a[1] &... | 6.592807 |
module CLA_4_bit_block (
a,
b,
cin,
blockp,
blockg,
sum
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output blockp, blockg;
wire [3:0] p, g, c;
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign g[0]... | 7.870212 |
module: CLA_4_bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cla_4bit_testbench;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire cout;
wire [3:0] sum;
//... | 8.474977 |
module CLA_4_tb;
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire [3:0] Sum;
wire Cout;
reg [3:0] i;
reg [3:0] j;
wire c3;
CLA_4 cla (
.a(A),
.b(B),
.c_in(Cin),
.s(Sum),
.c_out(Cout),
.c3(c3)
);
initial begin
$monitor("A=%b B=%b, Cin=%b -> Sum=%b, Cout=%b", A, B, C... | 6.904525 |
module CLA_64bits (
input wire [63:0] A,
input wire [63:0] B,
input wire c,
output wire [63:0] S,
output wire P,
output wire G
);
wire [3:1] carry;
wire [3:0] pp;
wire [3:0] gg;
CLA_16bits c16b0 (
A[15:0],
B[15:0],
c,
S[15:0],
pp[0],
gg[0]
);
CLA_1... | 8.011325 |
module CLA_64_4_tb ();
reg [63:0] A = 0, B = 0;
wire [63:0] Sum;
wire Cout;
reg reset, clock;
initial begin : A_TB
A = 0;
#10 A = 64'h00FF_00FF_00FF_00FF; // Worst case delay - carry generated via propogate
#30 A = 64'h0000_0000_0000_0000; // Making input = 0 so that next transition can be no... | 6.682625 |
module CLA_8 (
S8,
X8,
Y8,
Cin8,
G,
P
);
input [7:0] X8, Y8;
input Cin8;
output [7:0] S8;
output P, G;
wire gw0, gw1, gw2, gw3, gw4, gw5, gw6, G, P;
wire [7:0] g, p;
wire c1w;
wire c1;
wire [1:0] c2w;
wire c2;
wire [2:0] c3w;
wire c3;
wire [3:0] c4w;
wire c4;
w... | 7.074529 |
module cla_8bit (
S,
G,
P,
a,
b,
g,
p,
c0
);
input [7:0] a, b, g, p;
input c0;
output [7:0] S;
output G, P;
wire [7:0] c;
wire c11, c21, c22, c41, c42, c43, c44, c51, c52, c53, c54, c55, c61, c62, c63, c64, c65, c66, c71, c72, c73, c74, c75, c76, c77, g2, g3, g4, g5, g6, g7,... | 6.540216 |
module CLA_4bit (
input [3:0] x,
input [3:0] y,
input cO,
output [3:0] s,
output p,
g
);
assign s = x + y + cO;
assign g =
(x[3]&y[3])|
(x[2]&y[2]&(x[3]|y[3]))|
(x[0]&y[0]&(x[3]|y[3])&(x[2]|y[2]))|
(x[0]&y[0]&(x[3]|y[3])&(x[2]|y[2])&(x[1]|y[1]));
assign p = (x[3] | y[3]) & (x[2] | y[2]) &... | 7.044807 |
module CLA_adder #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input Cin,
output [WIDTH-1:0] Sum,
output Cout,
output Overflow
);
wire [(WIDTH/4):0] Cin_P;
wire [(WIDTH/4)-1:0] w_G, w_P;
genvar j;
generate
for (j = 0; j < WIDTH / 4; j = j + 1) begin
... | 7.48447 |
module cla_adder_16bit (
A,
B,
S,
C0,
C16,
Pg,
Gg
);
//port definitions - customize for different bit widths
input wire [15:0] A, B;
input wire C0;
output wire [15:0] S;
output wire C16, Pg, Gg; //haven't done Pg and Gg
wire [3:0] G, P; //G for generate, P for propagate
wir... | 8.058142 |
module cla_adder_32bit (
A,
B,
S,
C0,
C32,
Pg,
Gg,
overflow
);
//port definitions - customize for different bit widths
input wire [31:0] A, B;
input wire C0;
output wire [31:0] S;
output wire C32, Pg, Gg, overflow;
wire [1:0] G, P;
wire C16;
//Divide inputs/outputs
c... | 7.464419 |
module CLA_adder_8bit (
input [7:0] A,
input [7:0] B,
input c_in,
output reg [7:0] SUM,
output reg c_out
);
wire c_out_from_ADD0;
wire c_out_from_ADD1;
wire [7:0] FINAL_SUM;
wire [3:0] sum1;
wire [3:0] sum2;
wire c_in_from_outside;
wire [8:0] in_A;
wire [8:0] in_B;
assign c_in_fr... | 6.641545 |
module cla_adder_8bit_tb;
parameter A_width = 8, B_width = 8, S_width = 8;
reg [ A_width:0] in_A_tb; //Input A for both adders, MSB is the carry-in bit
reg [B_width - 1:0] in_B_tb; //Input B for both adders
wire [S_width - 1:0] SUM_Inferred_tb; //Output for inferred
wire [S_width - 1:0] SUM_CLA_tb... | 7.36787 |
module CLA_add_16 (
Sum,
Ovfl,
A,
B
);
input [15:0] A, B;
output [15:0] Sum;
output Ovfl;
wire [15:0] carry;
wire [15:0] Sum_temp;
//full_adder_1bit(A, B, Cin, S, Cout);
full_adder_1bit FA1 (
A[0],
B[0],
(1'b0),
Sum_temp[0],
carry[0]
);
full_adder_1bit... | 6.548924 |
module CLA_add_32 (
c,
p,
s,
cOut
);
input [31:0] p;
input [32:0] c;
output [31:0] s;
output cOut;
assign s = p ^ c[31:0];
assign cOut = c[32];
endmodule
| 8.597825 |
module carry_look_ahead_4bit_app (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
wire c11, c21, c22, c31, c32, c33, c41, c42, c43;
//propogate
xor XP0 (p[0], a[0], b[0]);
xor XP1 (p[1], a[1], b[1]);
xor XP2 (p[2], a[2], ... | 6.511278 |
module carry_look_ahead_4bit_acc (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
wire c11, c21, c22, c31, c32, c33, c41, c42, c43;
//propogate
xor XP0 (p[0], a[0], b[0]);
xor XP1 (p[1], a[1], b[1]);
xor XP2 (p[2], a[2], ... | 6.511278 |
module CLA_Array (
a,
b,
cin,
result,
cout
);
parameter width_div_4 = 16;
localparam bits = width_div_4 << 2;
input wire [bits-1:0] a;
input wire [bits-1:0] b;
input wire cin;
output wire [bits-1:0] result;
output wire cout;
wire Pi [width_div_4-1:0];
wire Gi [width_div_4-1:0];... | 7.336764 |
module CLA_Array_32 (
a,
b,
cin,
result,
cout
);
input wire [31:0] a;
input wire [31:0] b;
input wire cin;
output wire [31:0] result;
output wire cout;
wire Pi [7:0];
wire Gi [7:0];
wire Cio[7:0];
wire Cii[7:0];
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : b... | 6.531207 |
module CLA_bit_PG #(
parameter LENGTH = 2
) (
input [LENGTH-1:0] a
, input [LENGTH-1:0] b
, output [LENGTH-1:0] p
, output [LENGTH-1:0] g
);
assign p = a | b;
assign g = a & b;
endmodule
| 7.195602 |
module operator_A (
input A,
input B,
output P,
output G
);
assign P = A ^ B;
assign G = A & B;
endmodule
| 7.999043 |
module operator_B (
input P,
G,
P1,
G1,
output Po,
Go
);
assign Po = P & P1;
assign Go = G | (P & G1);
endmodule
| 7.330211 |
module operator_C (
input P,
G,
G1,
output Go
);
assign Go = G | (P & G1);
endmodule
| 6.604975 |
module cla_flags32 (
op,
result,
co_add,
co_prev_add,
co_sub,
co_prev_sub,
c,
n,
z,
v
);
input [2:0] op;
input [31:0] result;
input co_add, co_prev_add, co_sub, co_prev_sub;
output c, n, z, v;
assign c = (op[2:1] != 2'b11) ? 1'b0 : ((op[0] == 1'b0) ? co_add : co_sub);
... | 7.90554 |
module cla_fulladder (
input wire A,
input wire B,
input wire C,
output wire G,
output wire P,
output wire S
);
assign P = A ^ B; // propagate
assign G = A & B; // generate
assign S = P ^ C; // sum = A xor B xor C = P xor C
endmodule
| 8.031196 |
module cla_full_adder (
input a,
input b,
input c,
output g,
output p,
output s
);
assign g = a & b;
assign p = a ^ b;
assign s = a ^ (b ^ c);
endmodule
| 7.615604 |
module cla_generate (
A,
B,
G
);
input wire A, B;
output wire G;
assign G = A & B;
endmodule
| 7.377545 |
module CLA_group_PG #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
assign Gi[0] = G[0];
genvar i, j;
generate
for (i = GROUP; i <= WIDTH; i = i + GROUP) begin : upp_gc
wire g, p;
Black_cell #(
.... | 7.251772 |
module cla_n (
a,
b,
ci,
s,
co
);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire... | 7.349879 |
module cla_n (
a,
b,
ci,
s,
co
);
parameter n = 4; // Default
input [n-1:0] a, b;
input ci;
output [n-1:0] s;
output co;
wire [n-1:0] g;
wire [n-1:0] p;
wire [ n:0] c;
assign c[0] = ci;
assign co = c[n];
genvar i; /* i - generate index variable */
generate
for (i = 0... | 7.349879 |
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