code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cla_nbit #(
parameter n = 4
) (
input [n-1:0] a,
input [n-1:0] b,
input ci,
output [n-1:0] s,
output co
);
wire [n-1:0] g;
wire [n-1:0] p;
wire [ n:0] c;
assign c[0] = ci;
assign co = c[n];
genvar i; /* i - generate index variable */
generate
f... | 7.61009 |
module CLA_N_bit (
in1,
in2,
sum,
cin,
cout
);
parameter N = 4;
input [N-1 : 0] in1, in2;
input cin;
output [N-1 : 0] sum;
output cout;
reg [N : 0] c;
integer i;
always @(*) begin
c[0] = cin;
for (i = 0; i < N; i = i + 1) begin : CARRY_BLK
c[i+1] = (in1[i] & in2[i]) |... | 6.612583 |
module cla_propagate (
A,
B,
P
);
//port definitions - customize for different bit widths
input wire A, B;
output wire P;
assign P = A | B;
endmodule
| 8.35973 |
module cla_ripple_12bit (
sum,
c12,
a,
b,
c0
);
output [11:0] sum;
output c12;
input [11:0] a, b;
input c0;
wire c4;
wire c8;
wire [11:0] b2;
mux_2x1 m2x1 (
.dout(b2),
.d0 (b),
.d1 ((~b)),
.sel (c0)
);
cla_4bit_2 c4b1 (
.sum(sum[3:0]),
.c4 (c... | 6.537074 |
module tb_cla_ripple_8bit ();
reg [7:0] a, b;
reg c0;
wire [7:0] d;
wire cout;
cla_ripple_8bit uut (
.sum(d),
.c8 (cout),
.a (a),
.b (b),
.c0 (c0)
);
initial begin
#00 a = 8'd10;
b = 8'd10;
c0 = 1'b0; //10-2
#20 a = 8'd30;
b = 8'd20;
c0 = 1'b1;
... | 6.686519 |
module tb_cla_4bit ();
reg [3:0] a, b;
reg c0;
wire [3:0] d;
wire cout;
cla_4bit uut (
.sum(d),
.c4 (cout),
.a (a),
.b (b),
.c0 (c0)
);
initial begin
#00 a = 4'd10;
b = 4'b1101;
c0 = 1'b1; //10-2
#20 a = 4'd10;
b = 4'b0101;
c0 = 1'b1;
#20 a =... | 6.62014 |
module and one 8-bit CLA module with the carries rippling from one to the other
`include "cla_8bit.v"
`include "cla_16bit.v"
module cla_ripple_24bit(sum,c24,a,b,c0);
output [23:0] sum;
output c24;
input [23:0] a,b;
input c0;
wire c16;
cla_16bit c16b1(.sum(sum[15:0]),.c16(c16),.a(a[15:0]),.b(b[15:0]),.c0(c0));
cl... | 8.088031 |
module tb_cla_ripple_24bit ();
reg [23:0] a, b;
reg c0;
wire [23:0] d;
wire cout;
cla_ripple_24bit uut (
.sum(d),
.c24(cout),
.a (a),
.b (b),
.c0 (c0)
);
initial begin
#00 a = 16'd10;
b = 16'd10;
c0 = 1'b0; //10-2
#20 a = 16'd300;
b = 16'd20;
c0 ... | 6.686519 |
module cla_ripple_12bit (
sum,
c12,
a,
b,
c0
);
output [11:0] sum;
output c12;
input [11:0] a, b;
input c0;
wire c4;
wire c8;
wire [11:0] b2;
mux_2x1 m2x1 (
.dout(b2),
.d0 (b),
.d1 ((~b)),
.sel (c0)
);
cla_4bit c4b1 (
.sum(sum[3:0]),
.c4 (c4)... | 6.537074 |
module tb_cla_ripple_8bit ();
reg [7:0] a, b;
reg c0;
wire [7:0] d;
wire cout;
cla_ripple_8bit uut (
.sum(d),
.c8 (cout),
.a (a),
.b (b),
.c0 (c0)
);
initial begin
#00 a = 8'd10;
b = 8'd10;
c0 = 1'b0; //10-2
#20 a = 8'd30;
b = 8'd20;
c0 = 1'b1;
... | 6.686519 |
module tb_cla_4bit ();
reg [3:0] a, b;
reg c0;
wire [3:0] d;
wire cout;
cla_4bit uut (
.sum(d),
.c4 (cout),
.a (a),
.b (b),
.c0 (c0)
);
initial begin
#00 a = 4'd10;
b = 4'b1101;
c0 = 1'b1; //10-2
#20 a = 4'd10;
b = 4'b0101;
c0 = 1'b1;
#20 a =... | 6.62014 |
module CLA_SIM ();
parameter bits = 8;
reg [bits-1:0] A, B;
reg Cin;
wire [bits-1:0] Sum;
wire Cout;
//wire [bits-1:0] carries;
CLA #(bits) UUT (
.A (A),
.B (B),
.Cin(Cin),
.Sum (Sum),
.Cout(Cout)
//.carries(carries)
);
initial begin
/*
//4bit tests
{C... | 6.817879 |
module CLA_sum #(
parameter INPUT_LEN = 4
) (
input [INPUT_LEN-1:0] a
, input [INPUT_LEN-1:0] b
, input [INPUT_LEN-1:0] c
, output reg [INPUT_LEN-1:0] sum
);
integer i;
always @(*) begin
sum[0]=(a[0]&b[0]&c[0])|(a[0]&~b[0]&~c[0])|(~a[0]&b[0]&~c[0])|(~a[0]&~b[0]&c[0]);
for (i = 1; i <= IN... | 6.564331 |
module CLA_test;
parameter N = 8;
// testbench code for carry look ahead adder
reg cin; // To cla1 of cla_adder.v
reg [N-1:0] in1; // To cla1 of cla_adder.v
reg [N-1:0] in2; // To cla1 of cla_adder.v
wire cout; // From cla1 of cla_adder.v
wire [N-1:0] sum; // From cla1 of cla_adder.v
cla_adder... | 7.358432 |
module CLA_testbench (); //written 2/4/18
//ALU input/outputs: A, B, FS, CO, F, status
reg [63:0] A, B; //2 main inputs for ALU
reg Cin;
wire [63:0] Sum;
wire Cout;
initial begin
//FS <= 5'b0;
//CO <= 1'b0;
A <= 64'd0;
B <= 64'd0;
Cin <= 1'b0;
// A <= {$random, $random};
... | 7.681992 |
module CLA_adder_4bit (
input [3:0] A,
input [3:0] B,
input c_in,
output reg [3:0] SUM,
output reg c_out
);
wire [3:0] p_from_ha;
wire [3:0] g_from_ha;
wire [4:1] c_from_CLA;
wire [3:0] SUM_from_HA;
add_half HA0 (
A[0],
B[0],
g_from_ha[0],
p_from_ha[0]
);
add... | 6.796255 |
module cla_tree #(
parameter N = 8
) (
c_out,
s,
a,
b,
c_in
);
output [7:0] s;
output c_out;
input [7:0] a, b;
input c_in;
wire [7:0] c0, g0, p0;
wire [3:0] c1, g1, p1;
wire [1:0] c2, g2, p2;
wire g7, p7;
//A level
genvar i;
generate
for (i = 0; i < N; i = i + 1) b... | 6.70474 |
module cla ( //4 bit carry look ahead adder
output gp,
gg, //outputs are group propogate(gp),group generate(gg),sum and cout
output [3:0] sum,
cout, //inputs are a,b and cin
input [3:0] a,
b,
input cin
);
//output [3:0] cout;
wire [3:0] p, g; //wire to hold value of p... | 6.514456 |
module cla16 ( //module for 16 bit carry lookahead adder
output [15:0] sum,
cout, //sum,cout,gp,gg,xx4(final cout) are initialized as outputs
output gp,
gg,
xx4,
input [15:0] a,
b, //a,b and cin are initialized as inputs
input cin
);
wire x1, x2, x3, x4, xx1, xx2, xx3; //wir... | 7.383525 |
module
// Project Name: Carry Lookahead Adder
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CLA_p_v #(parameter SIZE=1... | 7.088073 |
module CLA_p_v_tb #(
parameter SIZE = 16
);
reg [SIZE:1] A, B;
reg CIN;
wire [SIZE:1] SUM;
wire COUT;
CLA_p_v #(SIZE, 4) INST1 (
.SUM(SUM),
.COUT(COUT),
.A(A),
.B(B),
.CIN(CIN)
);
initial begin
#150 $finish;
end
initial begin
A = 20'b0000000000000000;
... | 7.396481 |
module clb #(
parameter CLBIN = 3,
parameter CLBOUT = 2,
parameter CARRY = 1
) (
input [ CLBIN-1:0] inputs,
output [CLBOUT-1:0] outputs,
input [ CARRY-1:0] cin,
output [ CARRY-1:0] cout
);
endmodule
| 7.932662 |
module clb4 (
a,
b,
ci,
c1,
c2,
c3,
co
);
input [3:0] a, b; //4bits 2 input
input ci; //1bit 1 input
output c1, c2, c3, co; //output c1,c2,c3,co
wire [3:0] g, p; // generate signal, propagate signal
wire w0_c1; //use 1 wire in c1
wire w0_c2, w1_c2; //use 2 wire in c2
wi... | 6.76779 |
module clb_add #(
parameter WIDTH = 32
) (
// Clock, reset and enables
input wire clk,
input wire rst,
input wire en,
// Control path
output wire rdy,
input wire send_data,
// Datapath
input wire [2*WIDTH-1:0] din,
input wire divld,
output wire [WIDTH:0] dout,
outp... | 8.756839 |
module clb_adder_tb;
reg clk, r, en;
reg [2*`WIDTH-1:0] din;
reg divld;
wire [`WIDTH:0] dout;
wire dovld;
wire rdy;
reg send_data;
clb_add #(`WIDTH) dut (
.clk(clk),
.rst(r),
.en (en),
.rdy(rdy),
.send_data(send_data),
.din (din),
.divld(divld),
.dout... | 6.707685 |
module clb_ae (
input b,
input k,
input rst,
output y
);
wire f;
reg q;
assign f = b;
always @(posedge k, negedge rst) begin
if (rst == 1'b0) begin
q <= 1'b0;
end else begin
q <= f;
end
end
assign y = q;
endmodule
| 6.536128 |
module clb_af (
input a,
input b,
input c,
input d,
output x
);
wire f;
assign f = ~a & b | ~c & b | d & b | a & ~c & d;
assign x = f;
endmodule
| 7.040902 |
module clb_ag (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = a & c & d & ~b;
assign y = f;
endmodule
| 7.028847 |
module clb_bf (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = ~d | a & c | a & ~b | c & b;
assign y = f;
endmodule
| 7.003245 |
module clb_bg (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = ~a & b | d & b | a & ~c & ~d & ~b;
assign y = f;
endmodule
| 7.423785 |
module clb_cb (
input a,
input b,
input c,
input d,
output x,
output y
);
wire f, g;
assign f = c | ~a & ~b;
assign g = a & c & ~d;
assign x = f;
assign y = g;
endmodule
| 6.70228 |
module clb_ci (
input a,
input b,
input c,
input d,
output x,
output y
);
wire f, g;
assign f = ~a & ~b & c | a & b & c;
assign g = a & ~d | b & ~d | ~a & ~b & d;
assign x = g;
assign y = f;
endmodule
| 6.913525 |
module clb_ea (
input c,
input k,
input rst,
output y
);
wire f;
reg q;
assign f = c | c;
always @(posedge k, negedge rst) begin
if (rst == 1'b0) begin
q <= 1'b0;
end else begin
q <= f;
end
end
assign y = q;
endmodule
| 6.599579 |
module clb_eb (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = ~a & c & d & ~b;
assign y = f;
endmodule
| 6.839042 |
module clb_ei (
input a,
input b,
input c,
output y
);
wire f;
assign f = a & ~b & c;
assign y = f;
endmodule
| 7.044659 |
module clb_fc (
input a,
input b,
input c,
input d,
output x,
output y
);
wire f, g;
assign f = a & c & ~d;
assign g = b | b | ~d;
assign x = g;
assign y = f;
endmodule
| 6.573543 |
module clb_fg (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = a & ~c & ~d | ~c & ~d & b;
assign y = f;
endmodule
| 6.842735 |
module clb_fi (
input b,
input c,
input d,
output x,
output y
);
wire f, g;
assign f = c | ~d;
assign g = ~b & c;
assign x = g;
assign y = f;
endmodule
| 6.572524 |
module clb_gc (
input a,
input c,
input d,
output x,
output y
);
wire f, g;
assign f = ~a & ~c & d;
assign g = a | d;
assign x = g;
assign y = f;
endmodule
| 6.590471 |
module clb_gg (
input a,
input b,
input c,
input d,
output x,
output y
);
wire f, g;
assign f = ~a & ~d;
assign g = a & b & ~c;
assign x = g;
assign y = f;
endmodule
| 6.838097 |
module clb_gi (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = ~a & d | a & ~c | a & b;
assign y = f;
endmodule
| 7.263292 |
module clb_ha (
input c,
input k,
input rst,
output y
);
wire f;
reg q;
assign f = c | c;
always @(posedge k, negedge rst) begin
if (rst == 1'b0) begin
q <= 1'b0;
end else begin
q <= f;
end
end
assign y = q;
endmodule
| 6.544109 |
module clb_hh (
input a,
input b,
input c,
input d,
output y
);
wire f;
assign f = ~a & d | ~a & b | c & d | c & b | ~d & b;
assign y = f;
endmodule
| 7.025296 |
module clb_ia (
input c,
input k,
input rst,
output y
);
wire f;
reg q;
assign f = c | c;
always @(posedge k, negedge rst) begin
if (rst == 1'b0) begin
q <= 1'b0;
end else begin
q <= f;
end
end
assign y = q;
endmodule
| 6.575021 |
module clb_ic (
input a,
output y
);
wire f;
assign f = ~a;
assign y = f;
endmodule
| 6.524155 |
module clb_ig (
input a,
input c,
output x,
output y
);
wire f, g;
assign f = a & c;
assign g = ~a;
assign x = g;
assign y = f;
endmodule
| 6.654069 |
module clb_ii (
input a,
input b,
input c,
input d,
input rst,
output y
);
wire f, g, clk;
reg q;
assign f = ~d;
assign g = a & b;
assign clk = ~c;
always @(posedge clk, negedge g, negedge rst) begin
if (g == 1'b0 || rst == 1'b0) begin
q <= 1'b0;
end else be... | 6.567626 |
module clb_ja (
input c,
input rst,
output y
);
wire f;
reg q;
assign f = ~q;
always @(posedge c, negedge rst) begin
if (rst == 1'b0) begin
q <= 1'b0;
end else begin
q <= f;
end
end
assign y = q;
endmodule
| 6.526827 |
module clb_jd (
input c,
input d,
output y
);
wire f;
assign f = ~c & ~d;
assign y = f;
endmodule
| 6.531934 |
module clb_splitter #(
parameter IWIDTH = 32,
parameter OWIDTH1 = 16,
parameter OWIDTH2 = 16
) (
input wire [ IWIDTH-1:0] din,
output wire [OWIDTH1-1:0] dout1,
output wire [OWIDTH2-1:0] dout2
);
assign dout1 = din[OWIDTH1-1:0];
assign dout2 = din[OWIDTH2+OWIDTH1-1:OWIDTH1];
endmodule
| 8.506894 |
module clb_switch_box #(
// the number of pairs of in and out for single wires each side
parameter WS = 8,
// the number of pairs of in and out for double wires each side, must be multiple of 2.
parameter WD = 8,
parameter CONF_WIDTH = (WS + WD / 2) * 8
) (
input [ WS-1:0] north_single_... | 9.023894 |
module CLE (
clk,
reset,
rom_q,
rom_a,
sram_q,
sram_a,
sram_d,
sram_wen,
finish
);
input clk;
input reset;
input [7:0] rom_q;
output [6:0] rom_a;
input [7:0] sram_q;
output [9:0] sram_a;
output [7:0] sram_d;
output sram_wen;
output finish;
endmodule
| 6.608184 |
module D_FF (
clk,
rst,
D,
Q
);
input clk, rst, D;
output reg Q;
always @(posedge clk or posedge rst) begin
if (rst) begin
//Reset logic goes here.
Q <= 1'b0;
end else begin
//Sequential logic goes here.
Q <= D;
end
end
endmodule
| 6.601308 |
module Debouncer (
clk,
rst,
sig,
stb
);
input clk, rst, sig;
output stb;
wire q[1:0];
D_FF f1 (
.clk(clk),
.rst(rst),
.D (sig),
.Q (q[0])
);
D_FF f2 (
.clk(clk),
.rst(rst),
.D (q[0]),
.Q (stb)
);
endmodule
| 6.808208 |
module clean_rst (
input clk,
input rsti,
output reg rsto
);
reg rstt;
always @(posedge clk, posedge rsti) begin
rstt <= (rsti) ? 1 : 0;
rsto <= (rsti) ? 1 : rstt;
end
endmodule
| 6.743082 |
module clear (
input i_clk,
input i_start, // assert high to start cleaning
output reg o_running = 0, // busy
output [10:0] o_vram_addr,
output o_vram_w,
output o_vram_ce,
output [ 7:0] o_vram_din
);
parameter [10:0] fir... | 7.073498 |
module ClearBram (
clock,
reset,
enable,
doneclear,
bramdata
);
input clock, reset, enable;
output doneclear;
output [14:0] bramdata;
wire [12:0] address;
assign bramdata = {address, 2'd0};
counter #(13) clear_counter (
.clk(clock),
.rst(reset),
.en(enable | reset),
... | 7.242997 |
module ClearField
(
iCLOCK_50,
iresetn,
ienable,
ocolor_out,
ox,
oy,
owriteEn,
oDoneSignal,
);
input iCLOCK_50, iresetn, ienable;
output [2:0]ocolor_out;
output reg [8:0]ox;
output reg [7:0]oy;
output reg owriteEn;
output reg oDoneSignal;
assign ocolor_out = 3'b111;
reg [8:0]ix_pos = 30;
reg ... | 7.50277 |
module least_bit_decoder (
line_full,
bit_num
);
input [0:`BOARD_HEIGHT-1] line_full;
output reg [4:0] bit_num;
always @(*) begin
bit_num = 5'd0;
if (line_full[19] == 1'b1) bit_num = 5'd19;
if (line_full[18] == 1'b1) bit_num = 5'd18;
if (line_full[17] == 1'b1) bit_num = 5'd17;
if (lin... | 6.668247 |
module ui_clear (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
// The ports below are for the VGA output. Do not change.
output [2:0] color,
output [7:0] x,
output [6:0] y
);
wire enable, reset_datapath, done;
control_UI_clear c0 (
... | 7.427516 |
module control_UI_clear (
input clear,
input clk,
input reset_n,
input enable_unit,
output reg enable,
output reg writeEn,
output reg reset_datapath,
output [2:0] color
);
localparam ENABLE_STATE = 4'b0000, ENABLE_WAIT = 4'b0001, DRAW = 4'b0010, DISABLE = 4'b0011;
reg [1:0] current_... | 6.956513 |
module datapath_clear (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [3:0] increment1, increment2;
// when rate division done, frame enabled
wire [24:0] rate_out... | 6.934756 |
module clefia_128 (
c,
done,
clk,
reset_n,
k,
p,
start,
keygen,
encrypt
);
output [127:0] c; // 128-bit ciphertext
output done; //
input clk;
input reset_n;
input [127:0] k; // 128-bit key
input [127:0] p; // 128-bit plaintext
input start;
input keygen;
inpu... | 6.648563 |
module clg (
p1,
g1,
p0,
g0,
l,
n
);
input p1;
input g1;
input p0;
input g0;
output l;
output n;
nor nor1 (l, p1, p0);
or or1 (o, p1, g0);
nand nand1 (n, o, g1);
endmodule
| 7.126853 |
module D_trigger_rising #(
parameter width = 1
) (
clk,
data,
zero,
data_out
);
input clk;
input [width:1] data;
input zero;
output reg [width:1] data_out;
always @(posedge clk or posedge zero) begin
if (zero) data_out = 0;
else data_out = data;
end
endmodule
| 7.445584 |
module D_trigger_down #(
parameter width = 1
) (
clk,
data,
zero,
data_out
);
input clk;
input [width:1] data;
input zero;
output reg [width:1] data_out;
always @(negedge clk or posedge zero) begin
if (zero) data_out = 0;
else data_out = data;
end
endmodule
| 8.254786 |
module main (
input clk,
input rst,
output c0,
output c1,
output c2,
output c3,
output c4,
output c5,
output c6,
output c7
);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
SB_IO #(
.PIN_TYPE(6'b1010_01),
... | 7.081372 |
module main (
input sysclk,
input clk,
input rst,
output c0,
output c1,
output c2,
output c3,
output c4,
output c5,
output c6,
output c7
);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
... | 7.081372 |
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena)... | 7.858126 |
module click_counter_encaps (
input wire clk,
input wire count_in,
input wire count_enable,
output reg [23:0] count = 0,
output reg count_ready = 0,
input wire count_ack,
input wire [7:0] counter_id,
output reg [7:0] counter_id_out = 0
);
wire [23:0] q;
reg sclr = 0;
click_counte... | 7.720684 |
module Click_Game_tb;
reg clk, reset, en, D, E, start;
reg up;
wire tc, td;
wire [6:0] n;
wire [6:0] k;
wire [6:0] s;
wire [6:0] m;
wire [6:0] l;
wire [6:0] t;
lab1 UUT (
.clk(clk),
.reset(reset),
.en(en),
.D(D),
.E(E),
.up(up),
.n(n),
.k(k),
... | 6.595788 |
module cr_clic_arb_kernel (
// input
prio_in_vec,
// output
sel_out_onehot
);
parameter PRIO_WIDTH = 6;
parameter INT_NUM = 32;
parameter PRIO_EXP_NUM = 1 <<< PRIO_WIDTH;
input [PRIO_WIDTH*INT_NUM-1:0] prio_in_vec;
output [INT_NUM-1:0] sel_out_onehot;
wire [ INT_NUM-1:0] sel_out_oneh... | 7.287492 |
module cr_clic_ff1_onehot (
data_in,
ff1_out_onehot
);
parameter WIDTH = 32;
input [WIDTH-1:0] data_in;
output [WIDTH-1:0] ff1_out_onehot;
wire [WIDTH:0] ff1_tmp;
assign ff1_tmp[WIDTH] = 1'b0;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : FF1_ONEHOT
assign ff1_tmp[i] ... | 7.582297 |
module cr_clic_sel (
// input
data_in,
sel_in_onehot,
// output
data_out
);
parameter DATA_WIDTH = 32;
parameter SEL_NUM = 256;
input [DATA_WIDTH*SEL_NUM-1:0] data_in;
input [SEL_NUM-1:0] sel_in_onehot;
output [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_in_2d [ SEL_NUM... | 8.161387 |
module client_control_logic (
input clk,
input rst,
input ack,
input rq,
output enable_address_counter,
output enable_data_counter,
output enable_lfsr,
output enable_rq,
output wr_ni
);
//State parameters
parameter IDLE = 3'b000; // Idle state
parameter GENERATE_WRITE_TR... | 8.805961 |
module client_ram_test ();
// Parameters
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 4;
parameter ADDR_SPACE_BEGINNING = 0;
parameter ADDR_SPACE_END = 3;
parameter LFSR_SEED = 5'b00011;
parameter DELAY_ACK = 5;
parameter CLOCK_PERIOD = 5;
parameter RST_DELAY = 3;
parameter RST_DURATION = 2;
... | 7.420325 |
module for client simulations
// Creates the master side of the interface shown in clients.eps
// using either a data file, or live from a UDP port
`timescale 1ns / 1ns
module client_sub(
output clk,
// Synthesized data to DUT
output reg [10:0] len_c,
output [7:0] idata,
output raw_l,
output raw_s,
// Data retur... | 7.438103 |
module client_tb #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 4
) (
input clk, // Clock signal
input reset, // Reset signal, active 1
input [ADDR_WIDTH-1 : 0] address, // Address line
input rq, // Request signal
output reg ack, // Acknowledge output
input wr_ni, // Selection... | 8.255563 |
module client_test ();
// Parameters
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 4;
parameter ADDR_SPACE_BEGINNING = 0;
parameter ADDR_SPACE_END = 3;
parameter REQUEST_DELAY = 1;
parameter CLOCK_PERIOD = 5;
parameter RST_DELAY = 30;
parameter RST_DURATION = 2;
// Internal signals
wire ... | 7.33113 |
module CLinkConvert #(
parameter OUT_CLK_MHZ = 40,
parameter LINE_WIDTH = 640,
parameter LINE_DELAY_US = 25
) (
input en,
input rst,
// CameraLink input interface (20 MHz)
input clink_in_clk,
input clink_in_fval,
input clink_in_lval,
input ... | 7.175339 |
module CLinkGenerator #(
parameter DATA_WIDTH = 16,
parameter CLK_MHZ = 20,
parameter FRAME_WIDTH = 512,
parameter LINE_WIDTH = 640,
parameter FRAME_DELAY_US = 2000,
parameter FRAME_PERIOD_US = 38000,
parameter LINE_DELAY_NS = 100
) (
input en,
input ... | 8.365337 |
module cr_clint_busif (
busif_regs_msip_sel,
busif_regs_mtimecmp_hi_sel,
busif_regs_mtimecmp_lo_sel,
busif_regs_wdata,
busif_regs_write_vld,
clint_tcipif_cmplt,
clint_tcipif_rdata,
msip_value,
mtime_hi_value,
mtime_lo_value,
mtimecmp_hi_value,
mtimecmp_lo_value,
tcipi... | 7.035968 |
module clip #(
parameter P_WIDTH = 16
) (
input [P_WIDTH-1:0] a,
input [P_WIDTH-1:0] a0,
input [P_WIDTH-1:0] a1,
output reg [P_WIDTH-1:0] y
);
always @(*) begin
if (a > a1) y = a1;
else if (a < a0) y = a0;
else y = a;
end
endmodule
| 7.309524 |
module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//sub modules
`include "clipping.v"
module clipping_tb#( parameter
data_width = 16 // data width
)();
reg clk = 1'b0;
reg signed [data_widt... | 7.447046 |
module clip_and_round #(
parameter bits_in = 0,
parameter bits_out = 0,
parameter clip_bits = 0
) (
input [ bits_in-1:0] in,
output [bits_out-1:0] out
);
wire [bits_out-1:0] rounded;
round #(
.bits_in (bits_in - clip_bits),
.bits_out(bits_out)
) round (
.in (in[bits_in-... | 6.871313 |
module clip_and_round_reg #(
parameter bits_in = 0,
parameter bits_out = 0,
parameter clip_bits = 0
) (
input clk,
input [bits_in-1:0] in,
output reg [bits_out-1:0] out
);
wire [bits_out-1:0] temp;
clip_and_round #(
.bits_in (bits_in),
.bits_out (bits_out),
.clip_bits... | 6.871313 |
module clip_reg #(
parameter bits_in = 0,
parameter bits_out = 0
) (
input clk,
input [bits_in-1:0] in,
output reg [bits_out-1:0] out
);
wire [bits_out-1:0] temp;
clip #(
.bits_in (bits_in),
.bits_out(bits_out)
) clip (
.in (in),
.out(temp)
);
always @(posedge cl... | 6.896402 |
module clip_signed #(
parameter P_WIDTH = 16
) (
input signed [P_WIDTH-1:0] a,
input signed [P_WIDTH-1:0] a0,
input signed [P_WIDTH-1:0] a1,
output reg signed [P_WIDTH-1:0] y
);
always @(*) begin
if (a > a1) y = a1;
else if (a < a0) y = a0;
else y = a;
end
endmodule
... | 7.916858 |
module clip_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk = 0;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_header();... | 7.779262 |
module clk_counter (
input clk,
output reg [15:0] number
);
reg [20:0] counter;
always @(posedge clk) begin
counter = counter + 1;
number = counter == 0 ? number + 1 : number;
end
endmodule
| 7.09339 |
module clock_divider_tb ();
// Internal signals
wire out;
// Storage elements (set initial values to 0)
reg clk = 0;
reg rst = 0;
// Simulation time: 10000 * 1 ns = 10 us
localparam DURATION = 10000;
// Generate clock signal: 1 / ((2 * 41.67) * 1 ns) = 11,999,040.08 MHz
always begin
// Dela... | 6.818038 |
module name is : Clk_Gen
module <:$mod_name:>
(
input wire <:$clk:>,
input wire rstn,
// You need to change ports to your specific design
input wire <:$en:>,
input wire [2:0] <:$clk_sel:>,
input wire [5:0] <:$divn:... | 7.763155 |
module CLK (
sys_clk,
reset,
clk
);
input sys_clk, reset;
output reg clk;
reg [31:0] sum;
always @(negedge sys_clk or posedge reset) begin
if (reset) begin
sum <= 1;
clk <= 0;
end else clk <= ~clk;
end
endmodule
| 6.612848 |
module clk100_dcm (
CLKIN_IN,
RST_IN,
CLK0_OUT,
CLK2X_OUT,
LOCKED_OUT
);
input CLKIN_IN;
input RST_IN;
output CLK0_OUT;
output CLK2X_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLK0_BUF;
wire CLK2X_BUF;
wire GND1;
assign GND1 = 0;
assign CLK0_OUT = CLKFB_IN;
BUFG CLK0_BUFG... | 6.574568 |
module clk16p67MHz (
input basys_clk,
output clk_signal
);
reg [31:0] count = 32'd0;
reg clk_signal = 0;
always @(posedge basys_clk) begin
count <= (count == 2) ? 0 : count + 1;
clk_signal <= (count == 0) ? ~clk_signal : clk_signal;
end
endmodule
| 6.61667 |
module clk1mhz (
input clkin,
output clkout
);
reg [2:0] counter;
assign clkout = counter[2];
initial begin
counter <= 0;
end
always @(posedge clkin) begin
counter <= counter + 1;
end
endmodule
| 6.72801 |
module clk1seg (
input clk,
output reg clk1s
);
reg [49:0] cont;
initial begin
cont = 0;
clk1s = 0;
end
always @(posedge clk)
if (cont < 50'd50000000) cont <= cont + 1;
else begin
cont <= 0;
clk1s <= ~clk1s;
end
endmodule
| 6.592094 |
module clk2 (
clk,
reset,
out,
out_bar
);
input clk, reset;
output out, out_bar;
//module dffe_reg(q, d, clk, en, clr);
dffe_reg dff1 (
out,
~out,
clk,
1'b1,
reset
);
assign out_bar = ~out;
endmodule
| 6.761265 |
module clk20Hz (
input basys_clk,
output reg clk_signal = 0
);
reg [31:0] count = 32'd0;
always @(posedge basys_clk) begin
count <= (count == 2499999) ? 0 : count + 1;
clk_signal <= (count == 0) ? ~clk_signal : clk_signal;
end
endmodule
| 6.65952 |
module clk20k (
input CLOCK,
output reg CLOCKOUT
);
reg [11:0] COUNTER = 0;
always @(posedge CLOCK) begin
COUNTER <= (COUNTER == 2499) ? 0 : COUNTER + 1;
CLOCKOUT <= (COUNTER == 0) ? ~CLOCKOUT : CLOCKOUT;
end
endmodule
| 6.645732 |
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