code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module clk20kHz (
input basys_clk,
output clk_signal
);
reg [31:0] count = 32'd0;
reg clk_signal = 0;
always @(posedge basys_clk) begin
count <= (count == 2499) ? 0 : count + 1;
clk_signal <= (count == 0) ? ~clk_signal : clk_signal;
end
endmodule
| 6.805613 |
module freqdiv (
clk100M,
clr,
clk1
);
input clr;
input clk100M;
output clk1;
reg clk1;
reg [26:0] count;
parameter all = 99999999, half = 49999999;
always @(posedge clk100M) begin
if (!clr) begin
count <= 0;
clk1 = 1'b0;
end else if (count == half) begin
c... | 6.820964 |
module clk25_250 (
input clk_25mhz,
output locked,
output clko
);
wire clkfb;
wire clkos;
wire clkop;
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *)
(* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY... | 6.515768 |
module clk25_250 (
input clk_25mhz,
output locked,
output clko
);
reg clk = 1;
always #1 clk = !clk;
assign locked = 0;
assign clko = clk;
endmodule
| 6.515768 |
module clk380Hz (
input basys_clk,
output clk_signal
);
endmodule
| 6.882493 |
module clk3hz (
input clock,
output reg clock_out = 0
);
reg [23:0] counter = 0;
always @(posedge clock) begin
counter <= counter + 1;
clock_out <= (counter == 0) ? ~clock_out : clock_out;
end
endmodule
| 6.844269 |
module clk4 (
clk,
rst,
out_convl2,
in_pool2_1,
in_pool2_2,
in_pool2_3,
in_pool2_4
);
input clk;
input rst;
input [223:0] out_convl2;
output reg [223:0] in_pool2_1;
output reg [223:0] in_pool2_2;
output reg [223:0] in_pool2_3;
output reg [223:0] in_pool2_4;
integer count;... | 6.541519 |
module clk400Hz (
input basys_clk,
output clk_signal
);
reg [31:0] count = 32'd0;
reg clk_signal = 0;
always @(posedge basys_clk) begin
count <= (count == 124999) ? 0 : count + 1;
clk_signal <= (count == 0) ? ~clk_signal : clk_signal;
end
endmodule
| 7.075155 |
module clk4to1 (
input clk0,
input reset,
output clk
);
reg [2:0] cnt1;
wire c0;
always @(posedge clk0 or negedge reset)
if (!reset) cnt1 <= 0;
else cnt1 <= cnt1 + 1;
assign c0 = ~cnt1[1];
assign clk = ~c0;
endmodule
| 7.2072 |
module clk50 (
input clk,
input rst,
input select,
output reg [31:0] OUT1,
output reg [31:0] OUT2,
output clkdivided1hz,
output clkdivided2hz,
output clkselect
);
always @(posedge clk or posedge rst) begin
if (rst) OUT1 <= 32'd0;
else if (OUT1 == 32'd4) OUT1 <= 32'd0;
else... | 6.940175 |
module CLK60HZ (
input CLK100MHZ,
output reg stb
);
reg [15:0] counter = 0;
always @(posedge CLK100MHZ) {stb, counter} <= counter + 16'h4000;
endmodule
| 6.600011 |
module clk6Hz (
input CLOCK,
output reg CLOCKOUT = 0
);
reg [22:0] counter = 0;
always @(posedge CLOCK) begin
counter <= counter + 1;
CLOCKOUT <= (counter == 0) ? ~CLOCKOUT : CLOCKOUT;
end
endmodule
| 7.27561 |
module clk6p25Mhz (
input basys_clk,
output clk_signal
);
reg [31:0] count = 32'd0;
reg clk_signal = 0;
always @(posedge basys_clk) begin
count <= (count == 7) ? 0 : count + 1;
clk_signal <= (count == 0) ? ~clk_signal : clk_signal;
end
endmodule
| 6.931545 |
module clkADC_debug_pwm #(
parameter BPS_PARA = 50
) (
input bps_en,
input clk,
input RSTn,
output reg clk_ADC_debug
);
reg [12:0] cnt = 0;
always @(posedge clk or negedge RSTn) begin
if (~RSTn) cnt <= 13'b0;
else if ((cnt >= BPS_PARA - 1) || (!bps_en)) begin
cnt ... | 7.456617 |
module use Handshake module to transfer data
// This module will do handshake continuously.
// Means once previous Handshake is done, a new handshake is started.
module CLKCROSSBUS #(
parameter DATA_WIDTH = 16 ,
parameter OUT_RESET_VALUE = {DATA_WIDTH{1'b0}}
// no reset value here, because ... | 7.162818 |
module from SrcClk to DestClk
// This module use double sync module
module CLKCROSSDFF # (
parameter DATA_WIDTH = 1,
parameter RESET_VALUE = {DATA_WIDTH{1'b0}} //reset value
)
(
input i_s_rst_n ,
input i_src_clk ,
input [DATA_W... | 7.730128 |
module use pulse sync module
module CLKCROSSPLS (
input i_s_rst_n ,
input i_src_clk ,
input i_s_din ,
input i_d_rst_n ,
input i_dest_clk ,
output ... | 7.112862 |
module retimer(clk, din, rst_b, dout);
input din;
input clk;
input rst_b;
output dout;
reg r1_q, r2_q;
assign dout = r2_q & din;
always @ ( `CHANGEDGE clk or negedge rst_b )
if ( !rst_b)
{ r1_q, r2_q} <= 0;
else
{ r1_q, r2_q} <= {din, r1_q};
endmodule
| 6.516677 |
module clkdel (
CLKIN_IN,
RST_IN,
// CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK270_OUT,
LOCKED_OUT
);
input CLKIN_IN;
input RST_IN;
// output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK270_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK27... | 7.048404 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2/8/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module clkDiv16 (
output out, // Output of the clkdiv
input clk, // clock Input
input reset // reset Input
);
reg [15:0] count;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
count <= 16'b0;
end else begin
count <= count + 16'b000000000000000... | 6.675216 |
module clkdiv2 (
input clk,
input reset,
output div2clk
);
wire din;
wire clkdiv;
// Each dff instance divides by 2
adff dff_inst0 ( // div2
.clk(clk),
.reset(reset),
.D(din),
.Q(clkdiv)
);
assign din = ~clkdiv;
assign div2clk = clkdiv;
endmodule
| 6.873635 |
module clkdiv234 (
input clkin,
input rstb,
input div2,
input div3,
input div4,
output reg clkout
);
reg [1:0] p_d;
reg [1:0] p_q;
reg n_q;
always @(*) begin
if (div3) begin
p_d[1] = !p_q[0];
p_d[0] = p_q[1] & !p_q[0];
clkout = !... | 7.545877 |
module clkdiv24 (
input clkin,
input rstb,
input div4not2,
output reg clkout
);
reg [1:0] p_d;
reg [1:0] p_q;
`ifdef ripple_divider
always @(posedge clkin or negedge rstb)
if (!rstb) p_q[1] <= 1'b0;
else p_q[1] <= !p_q[1];
always @(posedge p_q[1] or negedge rstb)
... | 8.159815 |
module clkdiv4 (
input clk,
input reset,
output div4clk
);
wire [1:0] din;
wire [1:0] clkdiv;
// Each dff instance divides by 2
adff dff_inst0 ( // div2
.clk(clk),
.reset(reset),
.D(din[0]),
.Q(clkdiv[0])
);
adff dff_inst1 ( // div2 div2 = div4
.clk(clkdiv[0]... | 6.716955 |
module clkdiv5 #(
parameter integer ACCURATE_NEG_EDGE = 0
) (
input wire reset,
input wire clk_in,
output wire clk_out
);
reg [5:1] main_ctr;
reg half_ctr;
initial begin
main_ctr = 0;
half_ctr = 0;
end
always @(posedge clk_in) begin
if (reset) main_ctr <= 0;
else main_ctr <=... | 6.550792 |
module clkdiv9 (
pixel_en,
Clk,
clock_lcd
);
input Clk, pixel_en;
output reg clock_lcd;
parameter Divisor_DISP = 3;
parameter Bitcnt_DISP = 2;
reg [Bitcnt_DISP:0] Cnt_DISP;
always @(posedge Clk) begin
if (pixel_en == 0) begin
clock_lcd <= 0;
Cnt_DISP <= 0;
end else begi... | 6.822844 |
module: clockDivide
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clkDivide_tb;
// Inputs
reg rst;
reg clk;
// Outputs
wire slowClk;
wire slowPulse;
wire debounceClk;
//... | 7.046484 |
module clkdiv_100M_190_48 (
input wire clk_100M,
input wire clr,
output wire clk_190Hz,
output wire clk_48Hz
);
reg [24:0] q;
always @(posedge clk_100M or posedge clr) begin
if (1 == clr) q <= 0;
else q <= q + 1;
end
assign clk_190Hz = q[18];
assign clk_48Hz = q[20];
endmodule
| 7.222889 |
module clkdiv_190hz (
input wire CLK,
input wire clr,
output wire CLK_190hz
);
reg [19:0] q = 0;
always @(posedge CLK) begin
q = q + 1;
end
assign CLK_190hz = q[18];
endmodule
| 6.977213 |
module CLKDIV_200 (
input CLK,
input RST,
output reg CLK_O
);
parameter cnt_max = 4999999; //value to toggle the clock output
reg [29:0] cnt = 0; //current count
always @(posedge CLK) begin
if (RST) cnt <= 0;
else if (cnt == cnt_max) cnt <= 0;
else cnt <= cnt + 1'b1;
end
always @(p... | 6.934246 |
module CLKDIV_5 (
input CLK, //100MHZ W5 PIN
input RST, //reset
output reg CLK_O //5HZ Clock output
);
parameter cnt_max = 9999999; //value to toggle the clock output
reg [23:0] cnt; //current count
always @(posedge CLK) begin //operations about cnt
if (RST) cnt <= 0;
else if (cnt == c... | 6.606084 |
module CLKDIV_66_67 (
input CLK,
input RST,
output reg CLK_O
);
parameter cnt_max = 749; //value to toggle the clock output
reg [9:0] cnt; //current count
always @(posedge CLK) begin //operations about cnt
if (RST) cnt <= 0;
else if (cnt == cnt_max) cnt <= 10'b0;
else cnt <= cnt + 1'... | 7.038385 |
module ClkDiv_66_67kHz (
CLK, // 100MHz onbaord clock
RST, // Reset
CLKOUT // New clock output
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK... | 7.061724 |
module CLKDIV_800 (
input CLK,
input RST,
output reg CLK_O
);
parameter cnt_max = 1249999; //value to toggle the clock output
reg [29:0] cnt = 0; //current count
always @(posedge CLK) begin
if (RST) cnt <= 0;
else if (cnt == cnt_max) cnt <= 0;
else cnt <= cnt + 1'b1;
end
always @(... | 6.611652 |
module clkdiv_8kHz (
clk_50Mhz,
clk_8khz
);
input clk_50Mhz; // user clock
output clk_8khz; // divided clock
reg [25:0] count; // counter, is bigger then we need in case you wanna play with it
reg clk_8khz; // don't forget the register
initial // This describes what to do as soon as machine turn... | 6.672552 |
module clkdiv_frac #(
parameter W_DIV_INT = 16,
parameter W_DIV_FRAC = 8
) (
input wire clk,
input wire rst_n,
input wire en,
input wire [ W_DIV_INT-1:0] div_int,
input wire [W_DIV_FRAC-1:0] div_frac,
output reg clk_en
);
reg [ W_DIV_INT-1:0] ctr_int;
reg [W_DIV_... | 8.032478 |
module clkdiv_pulse (
input clk,
input rst,
input Sel_CLK,
input pulse,
output CK,
output reg [31:0] clkdiv
);
always @(posedge clk or posedge rst) begin
if (rst) clkdiv <= 0;
else clkdiv <= clkdiv + 1'b1;
end
assign CK = (Sel_CLK) ? ~pulse : clkdiv[26];
endmodule
| 7.512382 |
module clkdlle_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge <= 0;
clock_period <= 0;
end
always @(posedge clock) begin
clock_edge <= $time;
... | 6.540088 |
module clken_gen #(
parameter DIV_RATIO = 16
) (
input clk,
input rst,
output clken
);
parameter WIDTH = $clog2(DIV_RATIO);
reg clken;
reg [(WIDTH-1):0] cnt;
always @(posedge clk) begin
if (rst == 1) begin
cnt <= 8'b0;
clken <= 0;
end else begin
if (cnt == DIV_RA... | 7.066014 |
module clkdiv256 (
input wire clk,
input wire rst_n,
output reg o_clk_div2,
output reg o_clk_div4,
output reg o_clk_div8,
output reg o_clk_div16,
output reg o_clk_div32,
output reg o_clk_div64,
output reg o_clk_div128,
output reg o_clk_div256
);
always @(posedge clk ... | 7.796495 |
module clkdiv (
input wire clk,
input wire rst_n,
input wire i_en,
input wire [2:0] i_div,
output reg o_clk_div,
output wire [7:0] o_clk_all
);
wire clk_pre;
wire clk_div2;
wire clk_div4;
wire clk_div8;
wire clk_div16;
wire clk_div32;
wire clk_div64;
... | 7.689254 |
module mux8 (
input wire [2:0] i_sel,
input wire [7:0] i_in,
output wire o_out
);
assign o_out = i_in[i_sel];
endmodule
| 7.606032 |
module lfsr8 (
input wire clk,
input wire rst_n,
input wire i_en,
input wire i_ptb,
input wire i_ptb_valid,
input wire i_si,
input wire i_sr_valid,
output reg [7:0] o_state,
output wire o_p25,
output wire o_p50,
ou... | 9.232287 |
module clkGen97k656hz (
input clk_i,
input rst,
output reg clk_o
);
reg [8:0] clk_a;
//50MHz
always @(posedge clk_i or posedge rst) begin
if (rst) begin
clk_a[0] <= 1'b0;
end else begin
clk_a[0] <= ~clk_a[0];
end
end
//25MHz
always @(posedge clk_a[0] or posedge rst) begi... | 6.740575 |
module clkgene (
input clk,
input en,
input reset,
output clk1_2,
output clk1_4,
output clk2,
output clk4
);
/////////////////////////////////////////////
/////////////////clk synthesis//////////////
////////////2 * clk= 20MHz/////////////////
dfsinst clk12 (
.CLKIN_IN(clk... | 6.801955 |
module Clk_Generator (
CLK,
RST_N,
CLK_SMP
);
input CLK;
input RST_N;
output CLK_SMP;
wire clk_bps;
reg [31:0] bps_cnt1;
reg [31:0] bps_cnt2;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
bps_cnt1 <= 0;
bps_cnt2 <= 0;
end else begin
bps_cnt1 <= bps_... | 7.016953 |
module clock_generator_parametric #(
parameter OUTPUT_PERIOD = 1000,
parameter INPUT_PERIOD = 10
) (
input clk_i,
input rst,
input en,
output reg clk_o
);
localparam CYCLE_COUNT = (OUTPUT_PERIOD / INPUT_PERIOD) / 2;
localparam COUNTER_SIZE = $clog2(CYCLE_COUNT - 1);
wire countDone;
reg... | 6.801817 |
module clkgen (
inclk0,
c0,
c1,
c2,
c3
);
input inclk0;
output c0;
output c1;
output c2;
output c3;
endmodule
| 6.653049 |
module clkgen (
// Main clocks in, depending on board
sys_clk_in_p,
sys_clk_in_n,
// Wishbone clock and reset out
wb_clk_o,
wb_rst_o,
// JTAG clock
`ifdef JTAG_DEBUG
tck_pad_i,
dbg_tck_o,
`endif
// Asynchronous, active low reset in
rst_n_pad_i
);
input sys_clk_in_p, ... | 6.653049 |
module clkgen_init (
input clock,
input reset,
inout reg SDA,
inout reg SCL
);
reg [7:0] state;
reg [7:0] return_state;
reg [7:0] data;
reg [7:0] bit_cnt;
wire [7:0] i2c_address = 8'hD4;
//
reg [6:0] reg_addr;
wire [7:0] reg_data;
//
i2c_rom reg_set (
reg_addr,
c... | 7.07755 |
module clkgen_pll (
// Clock in
input CLKREF_IN,
// Clock out (from BUFG)
output CLKOUT0G
);
wire CLKREF_INB;
wire CLKOUT0;
wire CLKOUT0_INT;
// Input buffering
IBUFG IBUFG_IN (
.I(CLKREF_IN),
.O(CLKREF_INB)
);
// Clocking primitive
PLL_BASE #(
.BANDWIDTH ("... | 6.551432 |
module OSC0 // clkgen.v(14)
(
osc_dis,
osc_clk
);
input osc_dis; // clkgen.v(16)
output osc_clk; // clkgen.v(15)
EG_PHY_CONFIG #(
.DONE_PERSISTN("ENABLE"),
.INIT_PERSISTN("ENABLE"),
.JTAG_PERSISTN("DISABLE"),
.PROGRAMN_PERSISTN("DISABLE")
) config_inst ();
EG_PHY_OSC #(
... | 6.855966 |
module ClkInverter (
input clk_i,
output clk_o
);
assign clk_o = ~clk_i;
endmodule
| 7.187924 |
module dcm333 (
sclk, // input global clock, 120MHz, phase=0
SDCLK, // positive clock to SDRAM
SDNCLK, // negative clock to SDRAM
sdcl_fb,
xclk, // 60MHz for compressor
phsel, // additional phase control for SDRAM CLK
dcm_rst, // reset DCM phase
dcm_incdec, // variable phase cont... | 7.711712 |
module clkram ( //IM&&RAM
input wena,
input rena,
input clk,
input [31:0] addr,
input [31:0] data_in,
output [31:0] data_out
);
reg [31:0] i;
reg [31:0] state[0:10000];
reg [31:0] whichtoshow;
initial begin
whichtoshow = 32'b0;
end
initial begin
for (i = 0; i < 255; i = i... | 7.447793 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
INVX0 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n3;
XOR2X1 U1 (
.IN1(n3),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
INVX0 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n3;
XOR2X1 U1 (
.IN1(n3),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
INVX0 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n3, n4;
IBUFFX16 U1 (
.INP(n2),
.ZN (n4)
);
NBUFFX2 U2 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U3 (
.INP(X),
.Z (n2)
);
INVX0 U4 (
.INP(n1),
.ZN (n3)
);
XOR... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1;
IBUFFX16 U1 (
.INP(X),
.ZN (n1)
);
XNOR2X1 U2 (
.IN1(Y),
.IN2(n1),
.Q (Sum)
);
AND2X1 U3 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
AND2X1 U1 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
XOR2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n3, n4;
NBUFFX2 U1 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U2 (
.INP(X),
.Z (n2)
);
INVX0 U3 (
.INP(n1),
.ZN (n3)
);
NOR2X0 U4 (
.IN1(n4),
.IN2(n3),
.QN (... | 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
IBUFFX16 U1 (
.INP(X),
.ZN (n2)
);
XOR2X1 U2 (
.IN1(n2),
.IN2(n1),
.Q (Sum)
);
INVX0 U3 (
.INP(Y),
.ZN (n1)
);
AND2X1 U4 (
.IN1(X),
.IN2(Y),
... | 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n4, n5;
IBUFFX16 U1 (
.INP(n1),
.ZN (n4)
);
XNOR2X2 U2 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
INVX0 U4 (
.INP(X),
.Z... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
IBUFFX16 U1 (
.INP(X),
.ZN (n2)
);
XOR2X1 U2 (
.IN1(n2),
.IN2(n1),
.Q (Sum)
);
INVX0 U3 (
.INP(Y),
.ZN (n1)
);
AND2X1 U4 (
.IN1(X),
.IN2(Y),
... | 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X4 U2 (
.IN1(n2),
.IN2(n1),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X4 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
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