code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
IBUFFX16 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
IBUFFX16 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
IBUFFX16 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
IBUFFX16 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
IBUFFX16 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
IBUFFX16 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n2),
.IN2(n1),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1;
XOR2X1 U1 (
.IN1(Y),
.IN2(n1),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(X),
.Z (n1)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
INVX0 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1;
XOR2X1 U1 (
.IN1(Y),
.IN2(n1),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(X),
.Z (n1)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1;
XOR2X1 U1 (
.IN1(Y),
.IN2(n1),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(X),
.Z (n1)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(Y),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
INVX0 U3 (
.INP(X),
.ZN (n1)
);
INVX0 U4 (
.INP(n1),
... | 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
AND2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
XOR2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i3),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1;
XOR2X1 U1 (
.IN1(Y),
.IN2(n1),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(X),
.Z (n1)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n1),
.IN2(n2),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module HalfAdder_7 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n3;
XOR2X1 U1 (
.IN1(n2),
.IN2(n1),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n2),
.IN2(n3),
.Q (Cout)
);
DELLN1X2 U3 (
.INP(n1),
.Z (n3)
);
NBUFFX2 U4 (
.I... | 6.561596 |
module HalfAdder_6 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.769256 |
module FullAdder_3 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_7 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_6 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 7.164723 |
module HalfAdder_0 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(X),
.IN2(Y),
.Q (Cout)
);
endmodule
| 6.839006 |
module HalfAdder_1 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2;
XOR2X1 U1 (
.IN1(n1),
.IN2(n2),
.Q (Sum)
);
AND2X4 U2 (
.IN1(n2),
.IN2(n1),
.Q (Cout)
);
NBUFFX2 U3 (
.INP(Y),
.Z (n1)
);
NBUFFX2 U4 (
.INP(X),... | 6.559134 |
module HalfAdder_2 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.951699 |
module HalfAdder_3 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
wire n1, n2, n3;
XOR2X1 U1 (
.IN1(n2),
.IN2(n1),
.Q (Sum)
);
AND2X1 U2 (
.IN1(n2),
.IN2(n3),
.Q (Cout)
);
DELLN1X2 U3 (
.INP(n1),
.Z (n3)
);
NBUFFX2 U4 (
.I... | 6.890744 |
module FullAdder_1 (
A,
B,
Cin,
Cout,
S
);
input A, B, Cin;
output Cout, S;
wire i1, i2, i3;
HalfAdder_3 HA1 (
.X(A),
.Y(B),
.Cout(i1),
.Sum(i2)
);
HalfAdder_2 HA2 (
.X(i2),
.Y(Cin),
.Cout(i3),
.Sum(S)
);
OR2X1 U1 (
.IN1(i1),
... | 6.801587 |
module HalfAdder_4 (
X,
Y,
Cout,
Sum
);
input X, Y;
output Cout, Sum;
XOR2X1 U1 (
.IN1(Y),
.IN2(X),
.Q (Sum)
);
AND2X1 U2 (
.IN1(Y),
.IN2(X),
.Q (Cout)
);
endmodule
| 6.728341 |
module clkrst_tb;
initial begin
$dumpfile("clkrst_tb.vcd");
$dumpvars(0, clkrst_tb);
end
reg rst = 0;
initial begin
#20 rst = 1;
end
reg clk = 1;
always #5 clk = ~clk;
wire clk_2, clk_32, clk_512;
clkrst #(
.OFFSET(5)
) cs (
.clk(clk),
.rst(rst),
.clk_2(clk_2... | 7.06494 |
module ClkCtrl (
input rst_n,
input CLKIN_100M,
input CLKIN_96M,
output CLK_25M,
output CLK_24M,
output CLK_48M
);
/*
cameraClkGen clkgen(
.CLKIN_100MHz(CLKIN_100MHz), // IN
.CLK_25174kHz(CLK_25174kHz), // OUT
.CLK_80MHz(CLK_80MHz), // OUT
.RE... | 6.739075 |
module clksamplerensync ( /*AUTOARG*/
// Outputs
clksamplerensync_sampler_clksampleren_r_sync,
// Inputs
clk_sampler,
rst_sampler_n_sync,
samplertop_clksamplerensync_clksampleren_sync
);
`include "sync_params.v"
//-------------Input Ports---------------------
input clk_sampler;
input rs... | 7.43433 |
module ClkSpeedSwitcher #(
parameter LEVEL_1_INDEX = 49_999_999, // 1 Hz
parameter LEVEL_2_INDEX = 12_499_999, // 4 Hz
parameter LEVEL_3_INDEX = 3_124_999, // 16 Hz
parameter LEVEL_4_INDEX = 1_562_499, // 32 Hz
parameter LEVEL_5_INDEX = 781_249, // 64 Hz
parameter LEVEL_6_IND... | 8.827583 |
module ClkSpliterN (
input SYSTEM_CLK,
input RST_N,
input [15:0] SPLITER_N,
input CLK_IN,
output CLK_OUT
);
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
reg signal_out_temp;
reg signal_out;
reg locked;
reg dpout;
reg dpout_delay;
reg delclk;
reg addclk;
reg add_del_clkout;
... | 7.069976 |
module clksrc (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
clksrc_0002 clksrc_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0(outclk_0), // outclk0.clk
.locked (... | 7.114325 |
module implements a clock switch. This clock switch will
// switch between one of two incoming clocks to create an outgoing
// clock based upon a switch input. When the input switch is one way,
// the first output clock is selected and output, otherwise the second
// one.
//
// Assume:
// 1. Two clocks, one faster a... | 6.904081 |
module clktick_16 (
clkin, // Clock input to the design
enable, // enable clk divider
N, // Clock division factor is N+1
tick // pulse_out goes high for one cycle (n+1) clock cycles
); // End of port list
parameter N_BIT = 16;
//-------------Input Ports-----------------------------
input cl... | 7.602697 |
module clktimer_pwm #(
parameter BPS_PARA = 750000
) (
input clk,
input RSTn,
output reg clk_timer
);
reg [19:0] cnt = 0;
always @(posedge clk or negedge RSTn) begin
if (~RSTn) cnt <= 20'b0;
else if (cnt >= BPS_PARA - 1) cnt <= 20'b0;
else cnt <= cnt + 1'b1;
end
always @(posedge c... | 7.64583 |
module clktrans (
rst,
clk32,
clk_d1,
clk_d2
);
input rst; //复位信号，高电平有效
input clk32; //FPGA系统时钟:32MHz
output clk_d1; //双相时钟输出信号1
output clk_d2; //双相时钟输出信号2，与信号1相互正交
//产生周期为码速率的8倍(采样速率)，占空比为1：3的双相时钟
//双相时钟相位相差一个clk32时钟周期
//从这段程序可以看出，由于双相时钟clk_d1、clk_d2的周期为码元的采样周期，
//产生双相时钟信号的时钟频率不能小... | 7.601291 |
module clku (
clk,
rst,
cpu_clk,
gpu_clk
);
input wire clk;
input wire rst;
output wire cpu_clk;
output wire gpu_clk;
assign cpu_clk = clk;
graphic_pll pll (
.refclk(clk),
.rst(1'b0),
.outclk_0(gpu_clk)
);
endmodule
| 7.773213 |
module clkuart_pwm #(
parameter BPS_PARA = 347
) (
input bps_en,
input clk,
input RSTn,
output reg clk_uart
);
reg [12:0] cnt = 0;
always @(posedge clk or negedge RSTn) begin
if (~RSTn) cnt <= 13'b0;
else if ((cnt >= BPS_PARA - 1) || (!bps_en)) cnt <= 13'b0;
else cnt <= cnt + 1'b1;... | 7.355845 |
module ClkUnit (
SysClk,
EnableRx,
EnableTx,
Reset
);
input SysClk; // System Clock
output EnableRx; // Control signal
output EnableTx; // Control signal
input Reset;
wire SysClk;
wire EnableRx;
wire EnableTx;
wire Reset;
// Reset input
//================== End of entity =====... | 6.544212 |
module clkwiz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
inpu... | 7.198311 |
module clkwiz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 26.66... | 6.607219 |
module clk_1 (
input wire vga_clk, //输入工作时钟,频率25MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output reg flag
);
reg [24:0] cnt;
always @(posedge vga_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt = 25'b0;
else if (cnt == 24_999_999 - 1) cnt = 25'b0;
else cnt = cnt + 1'b1;
always @(... | 7.719737 |
module clk_100 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//------------------------------------
// Instantiation of the... | 6.901246 |
module clk_100Mhz_out (
// Clock out ports
output clk_out_100Mhz,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
clk_100Mhz_out_clk_wiz inst (
// Clock out ports
.clk_out_100Mhz(clk_out_100Mhz),
/... | 7.741749 |
module clk_100Mhz_out_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out_100Mhz,
// Status and control signals
input resetn,
output locked,
input clk_in1_p,
input clk_in1_n
);
// Input buffering
//------------------------------------
wire clk... | 7.741749 |
module clk_166M_83M ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1)... | 7.078535 |
module clk_166M_83M_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
... | 7.052103 |
module clk_166M_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 =... | 7.052103 |
module clk_2 (
input clk,
rst_n,
output reg clk_out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) clk_out <= 0;
else clk_out <= ~clk_out;
end
endmodule
| 8.239148 |
module clk_200_400 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//-----------------------... | 7.567368 |
module clk_200_400_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Pa... | 7.653434 |
module clk_200_400_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = ... | 6.762761 |
module clk_24_25_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
i... | 7.114806 |
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