code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module clk_24_25_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10... | 6.573187 |
module clk_25MHz_generator (
input wire i_clk_12MHz,
output wire o_clk_25MHz
);
`ifndef SYNTHESIS
// SIMULATION
assign o_clk_25MHz = i_clk_12MHz;
`else
// SYNTHESIS
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0001),
.DIVF(7'b1000010),
.DI... | 6.670856 |
module clk_32MHZ_to_25M_24M ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf (
.O(clkin1),
.I(CLK... | 6.800818 |
module of divided clock
// Uses modules:
//------------------------------------------------------------------
//Clock 4 Mhz
module clk_4(
input wire clk_w5 ,//100 Mhz on board Clock
input wire reset_b ,
output reg clk
);
reg [4:0] q; //
initial clk=0;
always @(posedge clk_w5 or posedge reset_b)
begin
if(r... | 6.690195 |
module clk_500_Hz (
clk_in,
reset,
clk_out
);
input clk_in, reset;
output clk_out;
reg clk_out;
integer i;
//***************************************************************
// The following verilog code will "divide" an incoming clock
// by the 32-bit decimal value specified in the "if condi... | 6.584336 |
module: Clk_50MHz
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Clk_50MHz_test;
// Inputs
reg CLK;
reg RST;
// Outputs
wire CLKOUT;
// Instantiate the Unit Under Test (UUT... | 6.578956 |
module clk_50to10 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//------------------------------------
// Instantiation of ... | 6.699722 |
module clk_5k (
clk_10k,
//clk_sys,//ʱ
rst_n,
clk_5k //ʱ
);
input clk_10k;
//input clk_sys;
input rst_n;
output clk_5k;
reg clk_5k;
/*
reg clk_10k_reg1;
reg clk_10k_reg2;
wire clk_10k_en;
*/
/*
always @ (posedge clk_sys)
begin
if (rst_n == 1'b0)
{clk_10k_reg1,c... | 6.534524 |
module clk_adjust (
CLK,
adjust,
clk_clk
);
input CLK, adjust;
output reg clk_clk;
wire clk_M;
wire clk_N;
initial begin
clk_clk <= 0;
end
divider a0 (
CLK,
clk_M,
clk_N
);
always @(posedge CLK) begin
case (adjust)
0: clk_clk <= clk_M;
1: clk_clk <=... | 7.805074 |
module divider (
CLK,
clk_M,
clk_N
); //Ƶ
input CLK; // ϵͳʱ
output reg clk_M, clk_N; // Ƶʱ
parameter M = 250_0000; // 40Hzʱ,N=fclk/fclk_N
parameter N = 2; // 50MHzʱ,N=fclk/fclk_N
reg [31:0] counter;
reg [31:0] counter2;
initial begin
clk_M <= 0;
counter <= 0;
clk_N <= 0;
c... | 7.389371 |
module clk_and2_cel (
output clkout, // AND output
input clk1, // clock 1
input clk2 // clock 2
);
assign clkout = clk1 & clk2;
endmodule
| 7.499595 |
module clk_and3_cel (
output clkout, // AND output
input clk1, // clock 1
input clk2, // clock 2
input clk3 // clock 3
);
assign clkout = clk1 & clk2 & clk3;
endmodule
| 8.061792 |
module clk_and4_cel (
output clkout, // AND output
input clk1, // clock 1
input clk2, // clock 2
input clk3, // clock 3
input clk4 // clock 3
);
assign clkout = clk1 & clk2 & clk3 & clk4;
endmodule
| 7.216788 |
module `BASE`MODULE ( i, o);
`undef MODULE
input i;
output o;
//E2_ifdef SIM_GBUF
assign o=i;
//E2_else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
//E2_endif
endmodule
| 7.581866 |
module `BASE`MODULE ( i, o);
`undef MODULE
input i;
output o;
assign o = i;
endmodule
| 7.581866 |
module `BASE`MODULE ( i, o);
`undef MODULE
input i;
output o;
assign o = i;
endmodule
| 7.581866 |
module `BASE`MODULE ( rst_n_i, rst_o, clk);
`undef MODULE
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
tmp <= 2'b11;
else
tmp <= {1'b0,tmp[1]};
`define MODULE gbuf
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
`undef MODULE
endmodule
| 7.581866 |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] ... | 7.581866 |
module
//E2_endif
///////////////////////////////////////////////////////////////////////////////
`else
///////////////////////////////////////////////////////////////////////////////
`ifdef ALTERA
`timescale 1 ps/1 ps
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
parame... | 6.869744 |
module
//E2_endif
///////////////////////////////////////////////////////////////////////////////
`else
// generic PLL
`timescale 1 ps/1 ps
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time = 20000;
param... | 6.869744 |
module clk_and_rst_n;
parameter CLK_INIT_VALUE = 1;
parameter HALF_CLOCK_PERIOD = 5;
parameter CYCLES_LIMIT = 100000;
reg clk, rst_n;
wire halt;
wire [15:0] PC_plus_1;
integer total_cycles;
cpu WISC_F14 (
.clk(clk),
.rst_n(rst_n),
.hlt(halt),
.pc(PC_plus_1)
);
initial clk =... | 7.123024 |
module clk_baudrate (
clkin,
rst_n,
clkout
);
input clkin;
input rst_n;
output clkout;
reg clkout;
parameter clks = 100000000;
parameter baudrate = 9600;
wire [31:0] cntmax;
integer cnt;
assign cntmax = (clks / baudrate / 16) - 1;
always @(posedge clkin or negedge rst_n)
if (!rst_... | 7.177681 |
module clk_blk (
CLKIN_IN,
RST_IN,
CLK0_OUT,
CLK180_OUT,
LOCKED_OUT
);
input CLKIN_IN;
input RST_IN;
output CLK0_OUT;
output CLK180_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLK0_BUF;
wire CLK180_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLK0_OUT = CLKFB_IN;
BUFG CL... | 7.026923 |
module clk_buffer (
input wire clk,
input wire [width-1:0] in,
output reg [width-1:0] q
);
parameter width = 8;
always @(posedge clk) begin
q <= in;
end
endmodule
| 7.371833 |
module clk_buffer_single (
input wire clk,
input wire in,
output reg q
);
always @(posedge clk) begin
q <= in;
end
endmodule
| 6.915944 |
module clk_buf_cel (
output clkout, // clock output
input clk // clock input
);
assign clkout = clk;
endmodule
| 6.5589 |
module clk_calc_audio ( // Clock in ports
input CLK_IN1,
// Clock out ports
output clk_calc,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking... | 6.800477 |
module clk_calc_audio_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
... | 6.800477 |
module clk_calc_audio_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1... | 6.800477 |
module clk_control_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ... | 6.531484 |
module clk_core (
// Clock out ports
output sys_clk_100M,
output scan_clk_10M,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
clk_core_clk_wiz inst (
// Clock out ports
.sys_clk_100M(sys_clk_100M),
... | 7.138707 |
module speed_cnt (
input clkin,
input rst,
input clken,
input [9:0] clk_freq,
output reg clkout
);
wire [31:0] limit;
assign limit = (25000000 / clk_freq);
reg [31:0] clkcount;
always @(posedge clkin) begin
if (rst) begin
clkcount = 0;
clkout = 1'b0;
end else begin
... | 7.029104 |
module Clk_Counter #(
parameter VAL = 15
) (
input clk,
input Reset,
input Count_Enable,
input [1:0] SelectMode,
output integer Count
);
always @(posedge clk) begin
if (SelectMode == 0 || SelectMode == 3) begin
if (Count_Enable == 1) begin
Count = Count + 1;
end else b... | 6.927346 |
module clk_counter_tb ();
// Entradas
reg clk;
reg rst;
// Saidas
wire if_enable;
wire pc_write;
integer old_count;
// Instanciando o Design Under Test (DUT)
clk_counter dut (
.clk(clk),
.rst(rst),
.if_enable(if_enable),
.pc_write(pc_write)
);
initial begin
$monito... | 6.695216 |
module clk_count_compare (
input comparing_clk,
input compared_clk,
input calibration_mode,
input clk_count_start,
input [14:0] count_untill,
output reg [14:0] compared_count
);
reg [14:0] comparing_clk_count;
always @(posedge comparing... | 7.092206 |
module clk_count_stop_tb ();
reg clk_in = 1'b0;
reg active = 1'b0;
reg reset = 1'b0;
reg [63:0] trg_count = 64'd0;
wire clk_out;
wire match;
always #20 clk_in <= !clk_in;
initial begin
// Non-active operation, clk_in == clk_out
#100;
// Activate module, set to stop after 5 clock cycles... | 6.753656 |
module clk_cross_Ctrl (
input done,
input clk,
input p_clk,
input rst,
input empty1,
input empty2,
output reg rd,
output reg wr_en,
output reg event_rdy
);
reg [2:0] state_init = 3'b000;
reg [2:0] state_wait1 = 'b001;
reg [2:0] state_wr = 3'b010;
reg [2:0] state_wait2 = 3'b0... | 7.281442 |
module cr_clkrst_top (
cpurst_b,
forever_cpuclk,
forever_cpuclk_nogated,
forever_jtgclk,
hadrst_b,
pad_cpu_rst_b,
pad_had_jtg_tclk,
pad_had_jtg_trst_b,
pad_had_rst_b,
pad_yy_test_mode,
pll_core_cpuclk,
trst_b
);
// &Ports; @23
input pad_cpu_rst_b;
input pad_had_jtg... | 6.784996 |
module clk_ctl (
// Outputs
clk_o,
// Inputs
mclk,
reset_n,
clk_div_ratio
);
//---------------------------------
// CLOCK Default Divider value.
// This value will be change from outside
//---------------------------------
parameter WD = 'h1;
//-------------------------------------... | 7.687611 |
module clk_d20 (
input clk_in,
input [4:0] div_base,
output reg clk
);
reg [4:0] counter;
always @(posedge clk_in) begin
if (counter == div_base) begin
counter <= 5'b00000;
clk = ~clk;
end else counter <= counter + 1'b1;
end // End of Always
endmodule
| 6.606414 |
module CLK_DDR ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primit... | 7.107878 |
module CLK_DDR_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
inp... | 7.265666 |
module CLK_DDR_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0... | 6.893278 |
module clk_den_flop (
input clk, // clock
input d, // data input
input den, // data enable
input rb, // Active low reset
output reg o // data output
);
// Flop with data enable
always @(posedge clk or negedge rb) begin : o_register
if (!rb) o <= 1'b0;
else... | 7.664265 |
module clk_diff (
input clk200P,
clk200N,
output clk200MHz
);
IBUFGDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
) IBUFGDS_inst (
... | 6.730363 |
module clk_dis1_count (
clk1,
rst_n,
op0,
op1,
op2,
op3,
op4,
op5
);
input clk1, rst_n; //声明时钟和复位信号，此处时钟为分频后的1KHz信号
output reg [5:0] op0 = 6'd0;
output reg [5:0] op1 = 6'd0;
output reg [5:0] op2 = 6'd0;
output reg [5:0] op3 = 6'd0;
output reg [5:0] op4 = 6'd0;
output reg [... | 6.735935 |
module clk_div (
input wire clk,
input wire reset,
output reg clk2,
output reg clk3,
output reg clk4,
output reg clk5
);
// div by 2, i.e., beta=0.75
always @(posedge clk) begin
if (reset) clk2 <= 0;
else clk2 <= ~clk2;
end
// div by 4, i.e., beta=0.875
always @(posedge... | 7.520262 |
module CLK_DIV10R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 10;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER ... | 6.791175 |
module CLK_DIV10RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 10;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DE... | 7.27307 |
module CLK_DIV10SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 10;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELA... | 7.269907 |
module CLK_DIV12 (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 12;
integer CLOCK_DIVIDER;
initial begin
CLOCK_DIVIDER = 0;
CLKDV = 1'b0;
end
always @(posedge CLKIN) begin
CLOCK_DIVIDER = CLOCK_DIVIDER + 1;
if (CLOCK_DIVIDER == (DIVID... | 6.851204 |
module CLK_DIV12R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 12;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER... | 6.900277 |
module CLK_DIV12RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 12;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DE... | 7.522873 |
module CLK_DIV12SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 12;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELA... | 7.16944 |
module CLK_DIV14 (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 14;
integer CLOCK_DIVIDER;
initial begin
CLOCK_DIVIDER = 0;
CLKDV = 1'b0;
end
always @(posedge CLKIN) begin
CLOCK_DIVIDER = CLOCK_DIVIDER + 1;
if (CLOCK_DIVIDER == (DIVID... | 7.22158 |
module CLK_DIV14R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 14;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER... | 7.205986 |
module CLK_DIV14RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 14;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DE... | 7.781944 |
module CLK_DIV14SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 14;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELA... | 7.589512 |
module CLK_DIV16 (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 16;
integer CLOCK_DIVIDER;
initial begin
CLOCK_DIVIDER = 0;
CLKDV = 1'b0;
end
always @(posedge CLKIN) begin
CLOCK_DIVIDER = CLOCK_DIVIDER + 1;
if (CLOCK_DIVIDER == (DIVID... | 6.804726 |
module CLK_DIV16R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 16;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER... | 7.03941 |
module CLK_DIV16RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 16;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DE... | 7.653218 |
module CLK_DIV16SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 16;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELA... | 7.220903 |
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @(posedge IN or posedge Reset)
if (Reset) OUT <= 0;
else OUT <= !OUT;
endmodule
| 7.23795 |
module CLK_DIV2R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 2;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER =... | 6.979549 |
module CLK_DIV2RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 2;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DELA... | 7.674124 |
module CLK_DIV2SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 2;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELAY_... | 7.446613 |
module clk_div3 (
input wire clk,
output reg clk_out
);
reg [1:0] pos_count = 2'b00;
reg [1:0] neg_count = 2'b00;
wire [1:0] r_nxt;
always @(posedge clk) begin
if (pos_count == 2) begin
pos_count <= 0;
clk_out <= 1'b1;
end else begin
pos_count <= pos_count + 1;
cl... | 6.961143 |
module CLK_DIV4 (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
localparam integer DIVIDE_BY = 4;
integer CLOCK_DIVIDER;
reg CLKDV;
initial begin
CLOCK_DIVIDER = 0;
CLKDV = 1'b0;
end
always @(posedge CLKIN) begin
CLOCK_DIVIDER = CLOCK_DIVIDER + 1;
if (CLOCK_DIVIDER == (DIVIDE_... | 7.109547 |
module CLK_DIV4R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 4;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER =... | 6.967399 |
module CLK_DIV4RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 4;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DELA... | 7.858228 |
module CLK_DIV4SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 4;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELAY_... | 7.544816 |
module CLK_DIV6 (
CLKIN,
CLKDV
);
input CLKIN;
output CLKDV;
integer CLOCK_DIVIDER;
localparam integer DIVIDE_BY = 6;
reg CLKDV;
initial begin
CLOCK_DIVIDER = 0;
CLKDV = 1'b0;
end
always @(posedge CLKIN) begin
CLOCK_DIVIDER = CLOCK_DIVIDER + 1;
if (CLOCK_DIVIDER == (DIVIDE_... | 6.770841 |
module CLK_DIV6R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 6;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER =... | 6.787281 |
module CLK_DIV6RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 6;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DELA... | 7.354142 |
module CLK_DIV6SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 6;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELAY_... | 7.225367 |
module clock_div7 (
output reg clk_div7,
input clock,
input rst_n
);
reg [5:0] temp;
always @(posedge clock or negedge rst_n) begin
if (!rst_n) begin
clk_div7 <= 1;
temp <= 6'b0;
end else begin
temp <= {temp[4:0], clk_div7};
clk_div7 <= temp[5];
end
end
endmodule
| 6.753249 |
module clk_div8 (
clk,
reset,
next_clk
);
input clk, reset;
output reg next_clk;
integer i;
always @(negedge reset, posedge clk) begin
if (~reset) begin
i = 0;
next_clk = 0;
end else begin
i = i + 1;
if (i == 10) begin
i = 0;
next_clk = next_clk + 1;... | 6.658873 |
module CLK_DIV8R (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 8;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer DELAY_RESET;
integer NO_BITS_REMAINING;
integer STARTUP;
initial begin
CLOCK_DIVIDER =... | 6.568032 |
module CLK_DIV8RSD (
CLKDV,
CDRST,
CLKIN
);
input CDRST, CLKIN;
output CLKDV;
reg CLKDV;
reg CDRST_i;
localparam integer DIVIDE_BY = 8;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DELA... | 7.075555 |
module CLK_DIV8SD (
CLKDV,
CLKIN
);
input CLKIN;
output CLKDV;
reg CLKDV;
localparam integer DIVIDE_BY = 8;
localparam integer DIVIDER_DELAY = 1;
integer CLOCK_DIVIDER;
integer START_WAIT_COUNT;
integer DELAY_START;
initial begin
CLOCK_DIVIDER = 0;
START_WAIT_COUNT = 0;
DELAY_... | 6.903206 |
module clk_divder_nbit (
clockin,
clockout
);
input clockin;
output wire clockout;
parameter n = 13;
reg [n:0] count = 0;
always @(posedge clockin) begin
count <= count + 1;
end
assign clockout = count[n];
endmodule
| 7.004289 |
module clk_divider #(
parameter divider = 16
) (
input clk,
input reset,
output reg clk_out
);
localparam half_divider = divider / 2;
localparam divider_minus_one = divider - 1;
reg [7:0] counter;
always @(posedge clk) begin
if (reset) clk_out <= 0;
else clk_out <= (counter < half_div... | 6.624712 |
module clk_divider #(
parameter WIDTH = 12, //number of bits to hold N
parameter N = 2604 //frequency * 1/(2*N) = out clk
) (
input clk,
output out
);
reg [WIDTH-1:0] r_reg;
wire [WIDTH-1:0] r_nxt;
reg clk_tracker;
always @(posedge clk) begin
if (r_nxt == N) begin
r_reg <= 0;
... | 6.624712 |
module clk_dividers #(
parameter N = 2
) (
input wire clk,
rst,
output reg clk_out
);
reg [7:0] counter;
always @(posedge clk or posedge rst)
if (!rst) counter <= 0;
else if (counter == N - 1) counter <= 0;
else counter <= counter + 1;
always @(posedge clk or posedge rst)
if (!r... | 8.130575 |
module clk_divider_7segment (
clk,
reset,
clk_1Hz
);
input clk, reset;
output clk_1Hz;
reg clk_1Hz = 1'b0;
reg [27:0] counter;
always @(posedge reset or posedge clk) begin
if (reset == 1'b1) begin
clk_1Hz <= 0;
counter <= 0;
end else begin
counter <= counter + 1;
... | 6.951338 |
module clk_divider_7segment (
clk,
reset,
clk_1Hz
);
input clk, reset;
output clk_1Hz;
reg clk_1Hz = 1'b0;
reg [27:0] counter;
always @(posedge reset or posedge clk) begin
if (reset == 1'b1) begin
clk_1Hz <= 0;
counter <= 0;
end else begin
counter <= counter + 1;
... | 6.951338 |
module clk_divider_by2 (
clk,
rst,
out_clk
);
output reg out_clk;
input clk;
input rst;
always @(posedge clk) begin
if (rst) out_clk <= 1'b0;
else out_clk <= ~out_clk;
end
endmodule
| 6.724605 |
module clk_divider_clk_wiz ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
wire clk_in1_clk_divider;
wire clk_in2_clk_divider;
IBUF clkin1_ibu... | 8.317195 |
module clk_divider_precise #(
//DEVIDE_CNT = 42.94967296 * fo
// parameter DEVIDE_CNT = 32'd175921860 //256000bps * 16
// parameter DEVIDE_CNT = 32'd87960930 //128000bps * 16
// parameter DEVIDE_CNT = 32'd79164837 //115200bps * 16
parameter DEVIDE_CNT = 32'd6597070 //9600bps * 16
) (
input c... | 6.891699 |
module clk_divider (
clk_in1,
clk_out1,
reset,
locked
);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_divider_clk_divider_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
... | 6.620262 |
module CLK_DIVIDER_TB ();
reg clk_in;
reg rst;
reg [12-1 : 0] clk_divider_odd;
reg [12-1 : 0] clk_divider_even;
wire clk_even;
wire [5-1 : 0] pwm_clk_out_odd;
wire clk_odd;
wire [5-1:0] pwm_clk_out_even;
CLK_DIVIDER DUT (
.clk_in(clk_in),
.pwm_clk_odd(pwm_clk_out_odd),
.pwm_clk_e... | 7.164135 |
module: clk_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clk_divider_test;
// Inputs
reg rst;
reg clk;
// Outputs
wire div_clk_2, div_clk_3, div_clk_4;
// Instant... | 6.64719 |
module clock_divider_v2 (
input reset,
input ref_clk,
output reg clk_out
);
parameter delay = 1000;
//100MHz to 100kHz, not sure what the Virtex 5 is
reg [9:0] count = 0;
initial clk_out = 0;
always @(posedge ref_clk) begin
if (count == (delay / 2) - 1) begin // constant division, evaluat... | 6.818038 |
module clk_divide_addr (
input clk,
input rst_n,
output reg clk_slow
);
reg [31:0] cnt_div;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) cnt_div <= 32'h0;
else if (cnt_div == 32'd99_999_999) cnt_div <= 32'h0;
else cnt_div <= cnt_div + 32'h1;
end
always @(posedge clk or neg... | 7.941209 |
module clk_divide_by_3 (
clk,
rst,
clk_div3
);
input clk, rst;
output [1:0] clk_div3;
reg [1:0] cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 0;
end else begin
if (cnt == 2'd2) cnt <= 0;
else cnt <= cnt + 1;
end
end
assign clk_div3 = cnt;
... | 6.857559 |
module: clk_divide
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clk_divide_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire clk_uart;
wire clk_sampling;
// Instantiate th... | 7.2281 |
module Clk_Division (
input clk_100MHz,
input [30:0] clk_mode,
output clk_out
);
reg Clk = 0;
reg flag = 0;
reg Is_Odd = 0;
integer Count = 0;
//Half cycle flag update
always @(negedge clk_100MHz) begin
Is_Odd = clk_mode[0]; //Determine whether the frequency division coefficient is an odd... | 6.754606 |
module clk_divn_even (
input clk,
input reset,
output clk_out
);
parameter WIDTH = 3; // Width of the register required
parameter N = 6; // We will divide by 12 for example in this case even number
reg [WIDTH-1:0] r_reg;
wire [WIDTH-1:0] r_nxt;
reg clk_track;
always @(posedge clk or posed... | 6.861972 |
module clk_divn_odd (
input clk,
input reset,
output clk_out
);
parameter WIDTH = 3;
parameter N = 5; // odd number required
reg [WIDTH-1:0] pos_count, neg_count;
wire [WIDTH-1:0] r_nxt;
always @(posedge clk)
if (reset) pos_count <= 0;
else if (pos_count == N - 1) pos_count <= 0;
... | 6.95911 |
module clk_div (
input clk,
input rst,
output reg clk_div
);
parameter constantNumber = 25;
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) count <= 32'b0;
else if (count == constantNumber - 1) count <= 32'b0;
else count <= count + 1;
end
always @(po... | 7.520262 |
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