code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module CLK_Div_16 (
clk_in,
reset,
clk_div16
);
input wire clk_in;
input wire reset;
output reg clk_div16;
reg [3:0] counter;
always @(posedge clk_in or posedge reset) begin
if (reset == 1'b1) counter = 3'b0;
counter = counter + 3'b1;
clk_div16 = counter[3];
end
endmodule
| 7.102812 |
module clk_div_2 (
input clk,
output reg clk_out
);
always @(posedge clk) begin
clk_out <= ~clk_out;
end
endmodule
| 7.129334 |
module clk_div3 (
clk,
reset,
clk_out
);
input clk;
input reset;
output clk_out;
reg [1:0] pos_count, neg_count;
wire [1:0] r_nxt;
always @(posedge clk)
if (reset) pos_count <= 0;
else if (pos_count == 2) pos_count <= 0;
else pos_count <= pos_count + 1;
always @(negedge clk)
... | 6.961143 |
module clk_div_30_seconds (
clk,
clk_d
);
parameter div_value = 1499999999;
input clk;
output clk_d;
reg clk_d;
reg [50:0] count;
initial begin
clk_d = 0;
count = 0;
end
always @(posedge clk) begin
if (count == div_value) count <= 0;
else count <= count + 1;
end
always @(pose... | 6.674669 |
module clk_div_45 (
clk_in, // Input Clock
enable, // Enable is sync with falling edge of clk_in
clk_out // Output Clock
);
// --------------Port Declaration-----------------------
input clk_in;
input enable;
output clk_out;
//--------------Port data type declaration-------------
wire ... | 6.661732 |
module clk_div_50 (
clk,
reset,
clk_50
);
input clk, reset;
output reg clk_50 = 0;
reg [23:0] clk_cnt = 0;
always @(posedge clk)
if (!reset) begin
clk_50 <= 0;
clk_cnt <= 0;
end else begin
if (clk_cnt == 24'd999999) begin
clk_50 <= ~clk_50;
clk_cnt <= 24... | 6.587373 |
module clk_div_5mhz (
clk,
rst,
clk_div
);
input clk;
input rst;
output reg clk_div;
localparam constNumber = 5;
reg [31:0] count;
always @(posedge clk, posedge rst) begin
if (rst) count <= 32'b0;
else if (count == constNumber - 1) count <= 32'b0;
else count <= count + 1;
end
... | 6.991852 |
module clk_div_clk_wiz ( // Clock in ports
input sys_clk,
// Clock out ports
output clk_50mhz,
output clk_25mhz,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
wire sys_clk_clk_div;
wire clk_in2_clk_div;
IBUF... | 7.908898 |
module clk_div_dec (
input clk,
input rstn,
input load,
output clk_div
);
parameter M = 5;
reg [15:0] div_mask_sf;
reg [15:0] div_mask;
assign div_mask = {M{1'b1}};
assign clk_div = (clk | (!div_mask_sf[0]));
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
div_... | 7.476789 |
module clk_div_display (
input clk,
output wire clk_out_state,
output wire clk_out_fast
);
reg [19:0] COUNT;
assign clk_out_state = COUNT[19];
assign clk_out_fast = COUNT[10];
initial begin
COUNT = 0;
end
always @(posedge clk) begin
COUNT = COUNT + 1;
if (COUNT >= 1000000) begin
... | 7.560825 |
module clk_div_even (
input clk,
input rstn,
output reg clk_div
);
parameter EVEN_NUM = 8;
wire [3:0] cnt_max;
reg [3:0] cnt;
assign cnt_max = (EVEN_NUM >> 1) - 1'b1;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 1'b0;
end else if (cnt == cnt_max) begin
... | 6.914403 |
module divider(
parameter NUM_DIV = 7;
)(
input clk,
input rst_n,
output reg clk_div
);
always @(posedge clk or negedge rst) begin
if(~rst)
cnt <= 3'b0;
else if(cnt < 3'b3)
cnt <= cnt + 3'd4;
else
cnt <= cnt - 3'b3;
end
always @(posedge clk or negedg... | 8.079227 |
module clk_div_hz #(
parameter integer FREQUENCY = 1
) (
input clk,
input rst,
input enable,
output reg dividedClk = 0,
output reg dividedPulse = 0
);
// calculate threshold value from frequency
localparam CLK_FREQ = 32'd16_000_000;
localparam THRESHOLD = CLK_FREQ / FREQUENCY / 2;
reg ... | 7.643949 |
module div_N (
input CLK,
output reg CLK_div_N
);
parameter N = 25000000;
reg [31:0] count = 0;
always @(posedge CLK) begin
if (count == 2 * N) count <= 0;
else count <= count + 1;
CLK_div_N = (count < N) ? 0 : 1;
end
endmodule
| 7.713354 |
module clk_div_odd (
input clk,
input rstn,
output reg clk_div
);
parameter ODD_NUM = 5;
wire [3:0] cnt_max;
wire [3:0] cnt_half;
reg [3:0] cnt;
reg clk_div_p;
reg clk_div_n;
assign cnt_max = ODD_NUM - 1'b1;
assign cnt_half = cnt_max >> 1;
assign clk_div = (clk_div_n | clk_div_p);
... | 8.46739 |
module clk_div (
sys_clk,
clk_50mhz,
clk_25mhz,
reset,
locked
);
input sys_clk;
output clk_50mhz;
output clk_25mhz;
input reset;
output locked;
wire clk_25mhz;
wire clk_50mhz;
wire locked;
wire reset;
(* IBUF_LOW_PWR *)wire sys_clk;
clk_div_clk_div_clk_wiz inst (
.clk_2... | 7.520262 |
module: clk_div_to_one
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clk_div_to_one_test;
// Inputs
reg clk_in;
// Outputs
wire clk_out;
// Instantiate the Unit Under ... | 6.814823 |
module clk_dll (
rst,
clk,
out_clk
);
input clk, rst;
output out_clk;
reg out_clk;
reg [24:0] cnt_clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
out_clk = 0;
cnt_clk = 0;
end else begin
cnt_clk <= cnt_clk + 1;
// if(cnt_clk == 24999999)
if... | 6.748082 |
module clk_dll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
inp... | 7.303014 |
module sync_reg_2 (
out_ptr,
in_ptr,
clk,
rst_n
);
output [2:0] out_ptr;
input [2:0] in_ptr;
input clk, rst_n;
reg [2:0] out1_ptr;
reg [2:0] out_ptr;
always @(posedge clk) begin
if (rst_n) {out_ptr, out1_ptr} <= 0;
else {out_ptr, out1_ptr} <= {out1_ptr, in_ptr};
end
endmodule
| 6.750972 |
module to move data demains clock domains //
// Date: Sept 2013 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: this modu... | 8.320286 |
module //
// Date: Jan 2014 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: ... | 8.238592 |
module clk_en106 (
input CLK,
input RST,
output reg CLK_O
);
//generate pulse signal with 1M hz frequency,with 10ns width, to enable some module
parameter cnt_max = 99;
reg [7:0] cnt = 8'b0;
always @(posedge CLK) begin
if (RST) cnt <= 8'b0;
else if (cnt == cnt_max) cnt <= 8'b0;
else cnt ... | 7.873244 |
module clk_en #(
parameter DIV = 12,
parameter OFFSET = 0
) (
input ref_clk,
output reg cen,
input [15:0] div,
input [1:0] fdiv
);
reg [15:0] cnt = OFFSET;
wire [15:0] cmax = div << {fdiv, 1'b0};
always @(posedge ref_clk) begin
if (fdiv != 2'b11) begin
if (cnt == cmax) begin
... | 7.473818 |
module clk_enable (
input wire clk_in,
input wire reset,
input wire [15:0] divider,
output reg clk_en
);
reg [15:0] count = 0;
always @(posedge clk_in) begin
if (reset == 1) begin
clk_en <= 0;
count <= 0;
end else begin
if (count >= divider) begin
clk_en <= 1'b1;... | 7.824564 |
module clk_enables (
input wire clk,
input wire CPUContention,
input wire [3:0] cpu_speed,
output wire clk14en,
output wire clk7en,
output wire clk7en_n,
output wire clk35en,
output wire clk35en_n,
output wire clk175en,
output reg clkcpu_enable
);
`include "config.vh"
// 28... | 7.423612 |
module clk_estimator #(
parameter EST_BITS = 20
) (
input rst,
input clk,
input meas_clk,
input cntr_ready,
output cntr_valid,
output [31:0] cntr_data
);
reg [EST_BITS-1:0] div_clk;
always @(posedge clk) begin
if (rst) begin
div_clk <= 0;
end else begin
... | 6.752075 |
module clk_even #(
parameter N = 4
) (
input clk,
rst_n,
output reg clk_out
);
localparam n = N / 2;
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
clk_out <= 0;
end else if (cnt == n - 1) begin
cnt <= 0;
clk_out <= ~clk_out... | 8.067636 |
module clk_fenpin (
input clk,
input rst_n,
output reg clk_1m
);
reg [25:0] clk_cnt; //分频计数器
//得到1Mhz分频时钟
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_cnt <= 5'd0;
clk_1m <= 1'b0;
end else if (clk_cnt < 26'd24) clk_cnt <= clk_cnt + 1'b1;
else begin
... | 6.943704 |
module clk_fm_demo_sample_pwm #(
parameter BPS_PARA = 25
) //400Khz(EOC)/BPS_PARA = audio samping rate. BPS_PARA=20: 20kHz
(
input FM_demod_en,
input EOC,
input RSTn,
output reg clk_fm_demo_sampling
);
reg [5:0] cnt = 0;
always @(posedge EOC or negedge RSTn) begin
if (~RSTn) cnt <= 6'b0;
... | 7.003943 |
module clk_for_spi (
input clk_in1,
output clk_out1,
output clk_out2,
input reset
);
wire clk_in1_mmcm, clkfbout_mmcm, clkfbout_buf_mmcm, clk_out1_mmcm, clk_out2_mmcm;
IBUF clkin1_ibufg (
.O(clk_in1_mmcm),
.I(clk_in1)
);
BUFG clkf_buf (
.O(clkfbout_buf_mmcm),
.I(clkf... | 6.712634 |
module Clk_fx_generator (
input sys_clk,
input rst_n,
output reg clk_fx
);
localparam DIVISION_FACTOR = 32'd100;
reg [31:0] clk_cnt;
always @(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
clk_cnt <= 32'd0;
clk_fx <= 1'b0;
end else if (clk_cnt >= ((DIVISION_... | 6.870696 |
module used by SandPiper default project.
module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);
assign gated_clk = free_clk;
endmodule
| 6.629148 |
module clk_gate_cel (
output clkout, // Clock gated
input clk, // Clock input
input en, // Clock enable
input te // Test enable
);
wire clk_en;
reg latch;
assign clk_en = te | en;
always @(clk or clk_en) begin
if (!clk) latch = clk_en;
end
assign clkout = latch & c... | 6.716697 |
module clk_gating_latch (
input wire clk,
input wire clk_en,
output wire clk_out
);
// use clock buffer on FPGA
// note that not all FPGAs have enough of these available
// so we use the latch as a fallback on certain boards (e.g., vc707)
`ifdef PITON_FPGA_SYNTH
assign clk_out = clk;
`else // ... | 7.390881 |
module is the clock generator for the design.
// It takes in a single clock input (nominally 100MHz), and generates
// three output clocks using a single clock generator:
// clk_rx - running at the same frequency as the input clock
// clk_tx - either running at the same frequency as the input ... | 6.808951 |
module clk_gen_80_2_80 (
input wire CLK_IN_80,
// Clock out ports
output wire CLK_OUT_80,
// Status and control signals
output wire LOCKED
);
wire clkin1;
wire clkout0;
wire clkout1;
// Input buffering
//------------------------------------
BUFG clkin1_buf (
.O(clkin1),
.I... | 6.591811 |
module clk_gen_83M ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),... | 7.271935 |
module clk_gen_83M_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
o... | 7.905335 |
module clk_gen_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = ... | 7.054851 |
module clk_gen_arty (
input wire i_clk,
input wire i_rst,
output wire o_clk_core,
output reg o_rst_core
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), // 100 MHz
.CLKOUT0_DIVIDE(64), // 2... | 7.284586 |
module clk_gen_basys3 (
input wire i_clk,
input wire i_rst,
output wire o_clk_core,
output reg o_rst_core
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOUT0_DIVIDE(64),
... | 6.947042 |
module clk_gen_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out,
input clk_in
);
// Input buffering
//------------------------------------
wire clk_in_clk_gen;
wire clk_in2_clk_gen;
IBUF clkin1_ibufg (
.O(clk_in_clk_gen),
.I(clk_in)
);
// Cl... | 7.807918 |
module clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input RESET,
outpu... | 7.160817 |
module clk_gen_nexys (
input i_clk,
input i_rst,
output o_clk_core,
output reg o_rst_core
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOUT0_DIVIDE(32),
.DIVC... | 6.616277 |
module clk_gen_nexys3 (
input wire clk_pad, // input clock, 100MHz
output wire clk_100m,
output wire clk_50m,
output wire clk_25m,
output wire clk_10m,
output wire locked
);
wire clk_pad_buf;
wire clk_100m_unbuf;
wire clk_50m_unbuf;
wire clk_25m_unbuf;
wire clk_10m_unbuf;
IBUFG ... | 6.616277 |
module clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 30.0... | 6.705399 |
module clk_gen_top ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED,
output WB_CLK,
output WB_RST,
output PCI_CLK,
output WB_CLK_2x,
output WB_RST_DELAY
);
wire pci_clk_i... | 6.685165 |
module clk_hz (
clk_in,
clk_out
);
input clk_in;
output clk_out;
reg clk_out;
reg [31:0] cnt;
parameter TIME = 1_000_000;
always @(posedge clk_in) begin
if (cnt == TIME / 2) begin
cnt <= 32'b0;
clk_out = !clk_out;
end else cnt <= cnt + 1'b1;
end
endmodule
| 6.563491 |
module clk_ibuf #(
parameter INPUT_CLK_TYPE = "DIFFERENTIAL" // input clock type
) (
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL"... | 6.565776 |
module clk_int_matcher (
input clk_in,
input active,
input [15:0] int_a,
input [15:0] int_b,
output clk_out,
output reg match = 1'b0
);
assign clk_out = (!active || (!match && active)) ? clk_in : 1'b0;
always @(negedge clk_in) begin
if (int_a == int_b) match <= 1'b1;
else match <... | 6.56869 |
module clk_int_matcher_tb ();
reg clk_in = 1'b0;
reg active = 1'b0;
reg [15:0] int_a = 16'd0;
reg [15:0] int_b = 16'd0;
wire clk_out;
wire match;
always #10 clk_in <= !clk_in;
always #10 int_a <= (!match && !clk_in) ? int_a + 1'b1 : int_a;
initial begin
// Non-active operation, clk_in == clk... | 6.56869 |
module clk_inv (
i_clk,
o_clk
);
input wire i_clk;
output wire o_clk;
assign o_clk = !i_clk;
endmodule
| 6.980372 |
module clk_inv_cel (
output clkout, // clock output
input clk // clock input
);
assign clkout = ~clk;
endmodule
| 6.882607 |
module clk_ip (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
clk_ip_0002 clk_ip_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0(outclk_0), // outclk0.clk
.locked (... | 7.195199 |
module
//
// BCLK and LRCLK are all generated synchronously to CLK_IN.
`timescale 1 ns/100 ps
module clk_lrclk_gen (reset, CLK_IN, BCLK, Brise, Bfall, LRCLK, LRrise, LRfall, Speed);
parameter BCLK_00 = 32; // desired number of BCLKs per half LRCLK cycle at Speed = 2'b00
parameter BCLK_01 = 32; /... | 6.694409 |
module clk_manage (
input clk,
input reset,
output CLK_int_delay,
output CLK_testsignal,
output CLK_data_out,
output CLK_fir_lagrange
);
parameter count_int_delay = 10;
parameter count_testsignal = 10;
parameter count_dataout = 10;
parameter count_fir_lagrange = 10;
parameter max_cou... | 7.348782 |
module clk_manager (
// Clock out ports
output clk_out_1,
output clk_out_2,
// Status and control signals
output locked,
// Clock in ports
input clk_in
);
clk_manager_clk_wiz inst (
// Clock out ports
.clk_out_1(clk_out_1),
.clk_out_2(clk_out_2),
// Status and c... | 7.189027 |
module clk_manager_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out_1,
output clk_out_2,
// Status and control signals
output locked,
input clk_in
);
// Input buffering
//------------------------------------
wire clk_in_clk_manager;
wire clk_in2_c... | 7.987412 |
module clk_mgr (
input wire clk,
input wire rst,
output wire clk_vga,
output reg clk_run
);
// 40MHz
clk_wiz_0 clk_wiz_0_dut (
.clk_i(clk),
.clk_40MHz(clk_vga)
);
// 60Hz
reg [`CNT_MAX_RUN_BIT_LEN-1:0] cnt_run;
// always @(posedge clk or posedge rst) begin
// if(rst) b... | 7.109354 |
module clk_mmcm (
// Clock out ports
output clk_200,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
clk_mmcm_clk_wiz inst (
// Clock out ports
.clk_200(clk_200),
// Status and control signals
.reset ... | 6.635304 |
module clk_mmcm_clk_wiz ( // Clock in ports
// Clock out ports
output clk_200,
// Status and control signals
input reset,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_mmcm;
wire clk_in2_clk_mmcm;
IB... | 8.173186 |
module clk_mmcm (
clk_200,
reset,
locked,
clk_in1
);
output clk_200;
input reset;
output locked;
input clk_in1;
wire clk_200;
(* IBUF_LOW_PWR *)wire clk_in1;
wire locked;
wire reset;
clk_mmcm_clk_mmcm_clk_wiz inst (
.clk_200(clk_200),
.clk_in1(clk_in1),
.locked (loc... | 6.635304 |
module CLK_MOD (
CLK,
RSTn,
CLK_OUT,
Count_REG
);
input CLK;
input RSTn;
input [31:0] Count_REG;
reg [31:0] Count;
output reg CLK_OUT;
always @(posedge CLK or negedge RSTn) begin
if (!RSTn) begin
Count <= 32'd0;
CLK_OUT <= 1'b1;
end else if (Count == Count_REG) be... | 7.796132 |
module clk_montitorTB ();
reg rst, preset;
reg [7:0] PSImin, PSImax, PIOset, FRO_min;
wire [7:0] setPeriod;
wire [7:0] cnt;
wire fail;
wire clk, up_ring, up;
inverter #(5, 41000) inv1 (
1'b1,
up
); //24Hz signal
inverter #(5, 15000) inv2 (
1'b1,
clk
); //100Hz signal
in... | 6.57413 |
module clk_monoflop (
input wire clk,
input wire trigger,
input wire enable,
output reg q = 0
);
reg previous = 0;
always @(posedge clk) begin
previous <= trigger & enable;
q <= trigger & ~previous & enable;
end
endmodule
| 7.924066 |
module clk_monoflop_tb;
parameter MASTER_PERIOD = 10;
// Inputs
wire clk;
clock_gen #(MASTER_PERIOD) mclk (clk);
// Inputs
reg trigger;
reg enable;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
clk_monoflop uut (
.clk(clk),
.trigger(trigger),
.enable(enable),
... | 6.821765 |
module clk_mux21 (
i_clk0,
i_clk1,
i_sel,
o_clk
);
input wire i_clk0;
input wire i_clk1;
input wire i_sel;
output wire o_clk;
assign o_clk = i_sel ? i_clk1 : i_clk0;
endmodule
| 6.894787 |
module nexys2 (
CE_IN,
CLKIN_IN,
CLR_IN,
PRE_IN,
RST_IN,
CLKDV_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
DDR_CLK0_OUT,
LOCKED_OUT
);
input CE_IN;
input CLKIN_IN;
input CLR_IN;
input PRE_IN;
input RST_IN;
output CLKDV_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output D... | 6.974591 |
module CLK_NO_HGHI (
clk,
rst,
in_b,
in_a,
out_a
);
input clk, rst;
input in_a, in_b;
output reg out_a;
wire clk_b;
always @(posedge clk_b or negedge rst) begin : block
if (!rst) out_a = 1'b0;
else out_a = in_a;
end
mod_b inst_b (
clk,
in_b,
clk_b
);
endmodu... | 6.519199 |
module CLK_NO_INPT (
clk,
port_a,
reset,
port_b
);
input clk;
input reset;
input port_a;
output port_b;
reg port_b;
wire clk_var;
assign clk_var = clk;
always @(posedge clk_var or negedge reset) begin
if (!reset) port_b <= 1'b0;
else port_b <= port_a;
end
endmodule
| 7.638653 |
module CLK_NR_DDBE (
clk,
out_a,
in_a
);
input clk, in_a;
output reg out_a;
always @(posedge clk) begin
if (clk) out_a <= in_a;
else out_a <= ~in_a;
end
endmodule
| 6.817715 |
module clk_odd1 #(
parameter N = 5
) (
input clk,
rst_n,
output clk_out
);
localparam n = N / 2; //对于N=5，n=2
reg [3:0] cnt; //只需1个计数器就可以
reg clk1, clk2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 0;
else cnt <= (cnt == N - 1) ? 0 : cnt + 1;
end
always @(pos... | 7.887297 |
module clk_odd2 #(
parameter N = 5
) (
input clk,
rst_n,
output clk_out
);
localparam n = N / 2;
reg [3:0] cnt;
reg clk1, clk2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 0;
else cnt <= (cnt == N - 1) ? 0 : cnt + 1;
end
always @(posedge clk or negedge rst_n) b... | 8.780772 |
module clk_or2_cel (
output clkout, // OR output
input clk1, // clock 1
input clk2 // clock 2
);
assign clkout = clk1 | clk2;
endmodule
| 7.745278 |
module clk_or3_cel (
output clkout, // OR output
input clk1, // clock 1
input clk2, // clock 2
input clk3 // clock 3
);
wire clkout_1_2;
wire clkout_3;
// First OR level for clk1 and clk2
clk_or2_cel clk_or2_1 (
.clkout(clkout_1_2), // OR output
.clk1 (clk1), // clock ... | 8.432733 |
module clk_pal (
input clkin, // 25 MHz, 0 deg
output clkout0, // 135 MHz, 0 deg
output clkout1, // 27 MHz, 0 deg
output locked
);
(* FREQUENCY_PIN_CLKI="25" *)
(* FREQUENCY_PIN_CLKOP="135" *)
(* FREQUENCY_PIN_CLKOS="27" *)
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP=... | 6.991233 |
module clk_pc (
input clk,
input wena,
input [31:0] data_in,
output [31:0] data_out
);
reg [31:0] data;
initial begin
data = 32'h00000000;
end
always @(posedge clk) if (wena) data[31:0] <= data_in[31:0]; //enable ,input
assign data_out = data;
endmodule
| 7.478479 |
module clk_int_matcher (
input clk_in,
input active,
input [15:0] int,
input [15:0] match,
output clk_out,
output stopped
);
assign clk_out = (!active || ((int == match) && active)) ? clk_in : 1'b0;
endmodule
| 6.56869 |
module clk_pixel (
input wire clk,
output reg clk_pixel
);
reg cnt;
initial begin
cnt <= 0;
clk_pixel <= 0;
end
always @(posedge clk) begin
if (cnt == 1) begin
cnt <= 0;
clk_pixel <= ~clk_pixel;
end else cnt <= 1;
end
endmodule
| 6.783715 |
module clk_pll_clk_wiz ( // Clock in ports
// Clock out ports
output cpu_clk,
output timer_clk,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_pll;
wire clk_in2_clk_pll;
IBUF clkin1_ibufg (
.O(clk_in1_clk_pll),
.I... | 7.350993 |
module clk_prescaler (
i_clk,
i_arst,
i_on,
i_divide_by,
o_clk_enable
);
input i_clk; // CLOCK_50, 50MHz system clock on Altera DE2 FPGA board, for example
input i_arst; // Reset signal
input i_on; // Count & work enable signal from CONFIG.ON bit (CONFIG[0])
input [6:0] i_divide_by; // ... | 8.224592 |
module clk_pulse (
input clk_200H,
input inp_0,
input inp_1,
output clk_pulse
);
wire inp_or;
reg FF1_reg, FF2_reg, FF3_reg;
reg FF1_next, FF2_next, FF3_next;
//2 Always blocks because of sequential Circuits. 1 Sequential and 1 Combinational
assign inp_or = inp_0 | inp_1;
//Debouncing C... | 7.128271 |
module clk_pwm (
input clk_i,
input rst_n,
output clk_o // 1 Hz
);
reg [24:0] cnt;
wire [24:0] cnt_nxt = (cnt == 25'd25000000) ? 25'd0 : cnt + 1'b1;
always @(posedge clk_i or negedge rst_n) begin
if (~rst_n) cnt <= 25'b0;
else cnt <= cnt_nxt;
end
reg clk;
always @(posedge clk_i ... | 6.624058 |
module clk_reg (
input clk,
input [31:0] in,
output reg [31:0] out
);
always @(posedge clk) begin
out <= in;
end
endmodule
| 8.31381 |
module clk_reset (
mclk,
reset_n,
rs_clk,
rs_reset_n,
sccb_clk,
sccb_reset_n,
cam_clk,
cam_reset_n,
pclk,
preset_n
);
input mclk;
input reset_n;
output rs_clk;
output rs_reset_n;
output sccb_clk;
output sccb_reset_n;
output cam_clk;
output cam_reset_n;
input pcl... | 7.5267 |
module instantiate the internal SB_HFOSC clock source in the
// Lattice ice40 UP device. It then connects it to the PLL, and
// finally connects the output from the PLL to the global clock net.
//
//
// Author: Joachim Strombergson
// Copyright (C) 2022 - Tillitis AB
// SPDX-License-Identifier: GPL-2.0-only
//
//======... | 6.637314 |
module CLK_RST (
input i_pon_rst_n
, input c_soft_tx_rst_n
, input c_soft_rx_rst_n
, input c_soft_pcs_rst_n
, input i_rgmii_tx_clk
, input i_rgmii_rx_clk
, input i_rgmii_tx_180_clk
, input i_rgmii_rx_180_clk
, input i_vl_tx_clk
, input i_vl_rx_0_clk
, input i_vl_rx_1_clk
... | 6.754737 |
module clk_rst_driver (
output reg clk,
output reg reset_n,
output wire reset
);
always #1 clk = !clk;
assign reset = !reset_n;
initial begin
clk = 0;
reset_n = 0;
@(negedge clk);
@(negedge clk);
reset_n = 1;
end
endmodule
| 6.776985 |
module clk_rst_gen #(
parameter CLK_FREQ = 10,
parameter RESET_CNT = 10,
parameter DIFF_CLOCK = 1
) (
output reg clk1,
output reg clk2,
output reg rst
);
initial begin
rst <= 1'b1;
#RESET_CNT;
rst <= 1'b0;
end
initial begin
clk1 <= 1'b0;
forever #CLK_FREQ clk1 <= ~... | 6.535102 |
module name - top_clock
// Version: tsn_chip_V1.0
// Created:
// by - li lijunshuai (1145331404@qq.com)
// at - 06.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// top of top_clock of chip
//
///////////////////////////////////////////////////... | 7.208437 |
module name - top_clock
// Version: tsn_chip_V1.0
// Created:
// by - li lijunshuai (1145331404@qq.com)
// at - 06.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// top of top_clock of chip
//
///////////////////////////////////////////////////... | 7.208437 |
module clk_rst_mngr (
input clk_in,
input rst_async_n,
input en_clk_div8,
output rst_sync_n,
output clk_out,
output clk_div2,
output clk_div4,
output clk_div8,
output clk_div8_proc
);
reg [2:0] counter;
reg synch_rst_reg1_n, synch_rst_reg2_n;
reg en_clk_div8_reg;
// clo... | 6.959516 |
module clk_rst_tb #(
parameter PERIOD = 5
) (
output reg clk,
output reg rst_n
);
initial begin
clk = 0;
forever begin
#PERIOD clk <= ~clk;
end
end
initial begin
rst_n <= 1'b1;
@(posedge clk);
rst_n <= 1'b0;
repeat (3) @(posedge clk);
rst_n <= 1'b1;
@(posedg... | 7.092123 |
module clk_rst_top (
clock,
hs_start,
sys_reset_n,
pwr_sq_reset_n,
ddr_clk,
dck_int,
sysclk,
clk_27m
);
input clock;
input hs_start;
output sys_reset_n;
output pwr_sq_reset_n;
output ddr_clk;
output dck_int;
output sysclk;
output clk_27m;
//Reg & Wire definition
re... | 6.547188 |
module version is 1.0
// Description : 下抽样模块
// 相关计算公式 : sample_fre = (Fs*2^32)/Fc (Fc = clk_AD)
//
// 端口定义 ： clk_AD ：AD最大采样时钟
// sample_fre ：采样率控制字
// clk_sample ：对应采样率下的时钟输出
// Note : 本代码遵循BSD开源协议
//==... | 6.626259 |
module clk_second (
input clkin,
input rst,
input clken,
output reg clkout
);
parameter clk_freq = 5;
parameter countlimit = 50000000 / 2 * clk_freq; // 自动计算计数次数
reg [31:0] clkcount;
always @(posedge clkin) begin
if (rst) begin
clkcount = 0;
clkout = 1'b0;
end else begin... | 6.859095 |
module clk_slow (
input CLK,
input Reset,
output reg [3:0] AN
);
reg [16:0] hide;
parameter DIVISION = 100000;
initial begin
hide <= 0;
AN <= 4'b0111;
end
always @(posedge CLK) begin
if (Reset == 0) begin
hide <= 0;
AN <= 4'b0000;
end else begin
hide <= hide ... | 6.785154 |
module clk_slow (
input clk,
output reg out
);
reg [15:0] cnt;
always @(posedge clk) begin
if (cnt == 499) begin
out <= ~out;
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
end
endmodule
| 6.785154 |
module clk_source (
input reset_in,
input clk_in,
output reset_out,
output clk_out
);
altera_reset_synchronizer sync (
.reset_in(reset_in),
.clk(clk_in),
.reset_out(reset_out)
);
assign clk_out = clk_in;
endmodule
| 7.178086 |
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