code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module clk_speed (
input clkin,
input rst,
input clken,
input [9:0] clk_freq,
output reg clkout
);
wire [31:0] countlimit;
assign countlimit = (25000000 / clk_freq);
reg [31:0] clkcount;
always @(posedge clkin) begin
if (rst) begin
clkcount = 0;
clkout = 1'b0;
end else... | 6.573381 |
module clk_src (
CLK05,
reset_rtl,
sys_diff_clock_clk_n,
sys_diff_clock_clk_p
);
output CLK05;
input reset_rtl;
input sys_diff_clock_clk_n;
input sys_diff_clock_clk_p;
wire clk_wiz_0_clk_out1;
wire reset_rtl_1;
wire sys_diff_clock_1_CLK_N;
wire sys_diff_clock_1_CLK_P;
assign CLK05 = ... | 6.858133 |
module clk_src_clk_wiz_0_1 (
// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_src_clk_wiz_0_1_clk_wiz inst (
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(... | 7.21657 |
module clk_src_clk_wiz_0_1_clk_wiz ( // Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUFDS clkin1_ibufgds (
.O (clk_... | 7.21657 |
module clk_src_swt (
input rstn,
input clk_src1,
input clk_src2,
input sel,
output clk_out
);
// some defines for wire connect
reg q1_p;
reg q1_n;
reg q2_p;
reg q2_n;
always @(negedge clk_src1 or negedge rstn) begin
if (!rstn) begin
q1_p <= 1'b0;
q1_n <= 1'b1;
e... | 7.603978 |
module clk_src_swt_tb ();
reg clk1;
reg clk0;
reg sel;
reg rstn;
wire clkout;
initial begin
clk1 = 0;
clk0 = 0;
sel = 0;
rstn = 1;
#10 rstn = 0;
#10 rstn = 1;
#50 sel = 1;
#50 sel = 0;
end
always #2 clk1 <= ~clk1;
always #4 clk0 <= ~clk0;
clk_src_swt dut (
... | 6.778883 |
module clk_src_wrapper (
CLK05,
reset_rtl,
sys_diff_clock_clk_n,
sys_diff_clock_clk_p
);
output CLK05;
input reset_rtl;
input sys_diff_clock_clk_n;
input sys_diff_clock_clk_p;
wire CLK05;
wire reset_rtl;
wire sys_diff_clock_clk_n;
wire sys_diff_clock_clk_p;
clk_src clk_src_i (
... | 7.551749 |
module clk_step (
input wire clk_i, // input clock source
input wire step_en, // enable step mode
input wire step_i, // step control
output reg clk_en, // clock enable signal
output reg clk_o // clock output
);
reg step_prev;
always @(negedge clk_i) begin
step_prev <= step_i;
clk_e... | 6.7531 |
module clk_stepper (
input clk_in,
input active,
input step,
output clk_out
);
reg step_lock;
assign clk_out = (!active && clk_in) || (step_lock && clk_in) ? 1'b1 : 1'b0;
always @(negedge clk_in) begin
if (step && active) begin
step_lock <= 1'b1;
end else step_lock <= 1'b0;
... | 6.94518 |
module clk_stepper_tb ();
reg clk_in = 1'b0;
reg active = 1'b0;
reg step = 1'b0;
wire clk_out;
always #10 clk_in <= !clk_in;
initial begin
// Non-active operation, clk_in == clk_out
#50;
// Activate module
active <= 1'b1;
// Step
#20 step <= 1'b1;
#20 step <= 1'b0;
... | 7.183721 |
module clk_stop (
reset,
lock,
eclk,
reset_datapath,
reset_datapath_out,
pll_stop,
stop
);
input reset;
input lock;
input eclk;
input reset_datapath;
input pll_stop;
output reset_datapath_out;
output stop;
reg reset_datapath_ff;
//use another ff to change stop_mem... | 7.094622 |
module clk_switch_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Par... | 8.216224 |
module clk_switch_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 1... | 7.263718 |
module clk_sys_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
input reset,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_sys;
wire c... | 7.084672 |
module clk_temp (
input clk,
input [31:0] a,
output [31:0] b
);
reg [31:0] temp;
always @(posedge clk) begin
temp = a;
end
assign b = temp;
endmodule
| 7.566077 |
module clk_test (
input wire clk,
output wire slow_clk
);
reg [2:0] cntr;
assign slow_clk = cntr[2];
initial begin
cntr = 0;
end
always @(posedge clk) begin
cntr <= cntr + 1'b1;
end
endmodule
| 6.59751 |
module clk_tester (
input clk_f,
input clk_2f,
input clk_4f,
output reg clk_32f,
output reg reset
);
initial begin
$dumpfile("clk_gen.vcd");
$dumpvars;
reset = 0;
#16 reset = 1;
#1024 $finish;
end
// Clock
initial clk_32f = 0;
always #2 clk_32f <= ~clk_32f;
endmodule... | 6.595989 |
module for clock testing
//
// Counts clock ticks (nothing exciting)
//
// Resets the counter on reads
//
///////////////////////////////////////////////////////////////////////////////
module clk_test_reg
(
// Register interface signals
input reg_req,
input ... | 6.624381 |
module clk_test_tb;
reg clk;
clk_test U0 (.clk(clk));
initial begin
clk = 0;
end
always #5 clk = !clk;
initial begin
$dumpfile("clk_test.vcd");
$dumpvars;
end
initial begin
$display("\t\ttime,\tclk,\ticycle");
//$monitor("%d,\t%b,\t%b",$time, clk,reset);
end
initial #5000... | 6.798828 |
module clk_timed_monoflop (
input wire clk,
input wire trigger,
input wire [PulseLengthWidth-1:0] pulselength,
input wire enable,
output reg q = 0
);
parameter PulseLengthWidth = 4;
reg triggered = 0;
reg [PulseLengthWidth-1:0] countdown = 0;
always @(posedge clk) begin
casez ({
... | 7.739794 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module for game
* @Author: Qin Boyu
* @Date: 2019-05-07 23:17:17
* @LastEditTime: 2019-05-19 10:20:57
*/
module clk_unit(
input clk,
input rst,
output reg clk_n
);
reg clk_n;
reg clk_tmp;
always @(posedge clk_tmp or posedge rst) begin
if (rst)
clk_n <= 0;
else
clk_n <=... | 7.288787 |
module clk_user_1 (
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
input reset,
// Clock in ports
input clk_in1
);
clk_user_1_clk_wiz inst (
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
// Status and control s... | 6.682785 |
module clk_user_1_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
input reset,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_user_1;
wire clk_in2_clk_u... | 7.341588 |
module clk_wiz_0 (
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
clk_wiz_0_clk_wiz inst (
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.re... | 6.750754 |
module clk_wiz_0 (
inclk0,
c0,
c1,
locked
);
input inclk0;
output c0;
output c1;
output locked;
endmodule
| 6.750754 |
module clk_wiz_0_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_wiz_0;
wire clk_in2_clk_wiz_0;... | 7.432971 |
module clk_wiz_0 (
clk_in1,
clk_out1
);
input clk_in1;
output clk_out1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
clk_wiz_0_clk_wiz_0_clk_wiz inst (
.clk_in1 (clk_in1),
.clk_out1(clk_out1)
);
endmodule
| 6.750754 |
module clk_wiz_0 (
clk_out1,
reset,
locked,
clk_in1
);
output clk_out1;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_wiz_0_clk_wiz_0_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
.loc... | 6.750754 |
module clk_wiz_1 (
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
clk_wiz_1_clk_wiz inst (
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.re... | 6.530545 |
module clk_wiz_1_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_wiz_1;
wire clk_in2_clk_wiz_1;... | 7.982864 |
module clk_wiz_1 (
clk_out1,
reset,
locked,
clk_in1
);
output clk_out1;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_wiz_1_clk_wiz_1_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
.loc... | 6.530545 |
module clk_wiz_200MHZ (
// Clock out ports
output clk_out,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in
);
clk_wiz_200MHZ_clk_wiz inst (
// Clock out ports
.clk_out(clk_out),
// Status and control signals
... | 7.184492 |
module clk_wiz_200MHZ_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out,
// Status and control signals
input reset,
output locked,
input clk_in
);
// Input buffering
//------------------------------------
wire clk_in_clk_wiz_200MHZ;
wire clk_in... | 7.184492 |
module clk_wiz_200MHZ (
clk_out,
reset,
locked,
clk_in
);
output clk_out;
input reset;
output locked;
input clk_in;
(* IBUF_LOW_PWR *)wire clk_in;
wire clk_out;
wire locked;
wire reset;
clk_wiz_200MHZ_clk_wiz_200MHZ_clk_wiz inst (
.clk_in (clk_in),
.clk_out(clk_out),
... | 7.184492 |
module clk_wiz_25m ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking pr... | 6.730412 |
module clk_wiz_25MHZ (
// Clock out ports
output clk_out,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in
);
clk_wiz_25MHZ_clk_wiz inst (
// Clock out ports
.clk_out(clk_out),
// Status and control signals
... | 6.59193 |
module clk_wiz_25MHZ_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out,
// Status and control signals
input reset,
output locked,
input clk_in
);
// Input buffering
//------------------------------------
wire clk_in_clk_wiz_25MHZ;
wire clk_in2_c... | 6.59193 |
module clk_wiz_25MHZ (
clk_out,
reset,
locked,
clk_in
);
output clk_out;
input reset;
output locked;
input clk_in;
(* IBUF_LOW_PWR *)wire clk_in;
wire clk_out;
wire locked;
wire reset;
clk_wiz_25MHZ_clk_wiz_25MHZ_clk_wiz inst (
.clk_in (clk_in),
.clk_out(clk_out),
.... | 6.59193 |
module clk_wiz_50_125mhz ( // Clock in ports
input CLK_IN_50,
// Clock out ports
output CLK_OUT_125,
output CLK_OUT_125_180
);
assign clkin1 = CLK_IN_50;
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
... | 6.814017 |
module clk_wiz_50_44mhz ( // Clock in ports
input CLK_IN_50,
// Clock out ports
output CLK_OUT_44
);
assign clkin1 = CLK_IN_50;
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are lab... | 6.893206 |
module clk_wiz_clk_wiz ( // Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_wiz;
wire clk_in2_clk_wiz;
IBUF clkin1_ibufg (
.O(clk_in1_clk_wiz),
.I(clk_in1)
);
... | 7.857552 |
module clk_wiz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
inp... | 7.741702 |
module clk_wiz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 5.0 ... | 6.680349 |
module clk_wiz_v3_3 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking p... | 8.16316 |
module clk_wiz_v3_3_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// P... | 6.880395 |
module clk_wiz_v3_3_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 =... | 6.880395 |
module clk_wiz_v3_6 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1)... | 7.966928 |
module clk_wiz_v3_6_0 ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin... | 6.681059 |
module clk_wiz_v3_6_0_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
... | 6.681059 |
module clk_wiz_v3_6_0_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1... | 6.681059 |
module clk_wiz_v3_6_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
... | 6.681059 |
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 =... | 6.681059 |
module handles the carry outs for each partial full adder
//Acts as a wrapper to individual carry_gen modules
module CLL #(parameter bits = 8) (
input Cin,
input [bits-1: 0] P, G,
output [bits-1: 0] Cout
);
//Create carry generator block for first bit
CARRY_GEN INST0(
.G(G[0]),
.P(P[0]),
... | 7.545049 |
module cpu_wb_cla_adder (
in1,
in2,
carry_in,
sum,
carry_out
);
parameter DATA_WID = 32;
input [DATA_WID - 1:0] in1;
input [DATA_WID - 1:0] in2;
input carry_in;
output [DATA_WID - 1:0] sum;
output carry_out;
//assign {carry_out, sum} = in1 + in2 + carry_in;
wire [DATA_WID - 1:0] g... | 6.868177 |
module clock_3 (
input clk_in,
output clk_out
);
reg [28:0] count = 28'd0;
parameter frecuencia = 20;
parameter div = 28'd100000000 / frecuencia;
always @(posedge clk_in) begin
count <= count + 28'd1;
if (count >= (div - 1)) count <= 28'd0;
end
assign clk_out = (count < div / 2) ? 1'b1 :... | 7.008273 |
module clock_digtal_counter0 (q,clk,reset);
output [:0] q;
input clk,reset;
T_FF tff0 (q[0], clk, reset);
T_FF tff1 (q[1], q[0], reset);
T_FF tff2 (q[2], q[1], reset);
T_FF tff3 (q[3], q[2], reset);
endmodule
| 6.864617 |
module D_FF (q, d, clk, reset);
output q;
input clk, reset;
reg q;
always @(psedge reset or negedge clk)
if (reser)
q = 1'b0;
else
q = d ;
endmodule
| 7.247133 |
module clock_digtal_counter1 (q,clk,reset);
output [:0] q;
input clk,reset;
T_FF tff0 (q[0], clk, reset);
T_FF tff1 (q[1], q[0], reset);
T_FF tff2 (q[2], q[1], reset);
T_FF tff3 (q[3], q[2], reset);
endmodule
| 6.864617 |
module D_FF (q, d, clk, reset);
output q;
input clk, reset;
reg q;
always @(psedge reset or negedge clk)
if (reser)
q = 1'b0;
else
q = d ;
endmodule
| 7.247133 |
module clock_divider (
clk_div,
clk
);
input clk;
output clk_div;
parameter width = 25;
reg [width-1:0] num;
wire [width-1:0] next_num;
always @(posedge clk) begin
num <= next_num;
end
assign next_num = num + 1;
assign clk_div = num[width-1];
endmodule
| 6.818038 |
module clock_buffer (
CLK,
CLK_GATE,
RST_N,
CLK_IN,
CLK_OUT
);
input CLK; // ignore
input CLK_GATE; // ignore
input RST_N; // ignore
input CLK_IN;
output CLK_OUT;
BUFG CLK_BUFG_INST (
.I(CLK_IN),
.O(CLK_OUT)
);
endmodule
| 6.922673 |
module clock_counter (
// Inputs
input clk,
input rst_btn,
// Outputs
output reg [3:0] led
);
wire rst;
reg div_clk;
reg [31:0] count;
localparam [31:0] max_count = 6000000 - 1;
// Reset is the inverse of the reset button
assign rst = ~rst_btn;
// Count up on (divided) clock risin... | 6.993724 |
module clock_divider #(
// Parameters
parameter MODULO = 6000000
) (
// Inputs
input clk,
input rst,
// Outputs
output tick
);
// Calculate number of bits needed for the counter
localparam WIDTH = (MODULO == 1) ? 1 : $clog2(MODULO);
// Internal storage elements
reg [WIDTH-1:0] c... | 6.818038 |
module clock_divider_tb ();
// Settings
localparam MODULO = 120; // 12 MHz / 120 = 100 kHz ticks
// Internal signals
wire tick;
// Internal storage elements
reg clk = 0;
reg rst = 0;
// Simulation time: 10000 * 1 us = 10 ms
localparam DURATION = 10000;
// Generate clock signal
always begin... | 6.818038 |
module CLOCK25_PLL (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
CLOCK25_PLL_0002 clock25_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.re... | 6.892947 |
module clock2gerente (
input clk1,
rst,
output reg clk2
);
always @(negedge clk1 or posedge rst) begin
if (rst == 1) clk2 <= 1'b0;
else clk2 <= ~clk2;
end
endmodule
| 6.984805 |
module clk_2Mbps (
saida,
inicio
);
output wire saida;
output wire inicio;
reg out;
reg out1;
assign saida = out;
assign inicio = out1;
initial begin
out = 0;
out1 = 1;
end
always begin
#250 out = ~out;
out1 = 0;
end
endmodule
| 7.198151 |
module Clock35MHz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//-------... | 6.984132 |
module Clock35MHz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
... | 6.980019 |
module Clock35MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 1... | 7.611257 |
module Clock50MHz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//------------------------------------
// Instantiation of ... | 7.037551 |
module Clock50MHz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
... | 6.834534 |
module Clock50MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 1... | 6.970235 |
module Clock65MHz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//-------... | 6.50261 |
module Clock65MHz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
... | 6.971163 |
module Clock65MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 1... | 7.613161 |
module Clock70HMz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking pri... | 6.759237 |
module Clock70HMz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
... | 7.139513 |
module Clock70HMz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 1... | 6.985335 |
module Clock70MHz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf (
.O(clkin1),
.I(CLK_IN1)
);
// Clocking primitive
//-------... | 7.071388 |
module Clock70MHz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
... | 7.247692 |
module Clock70MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 1... | 7.211287 |
module clockchange (
userclock,
switch2,
n0and1,
n2and3,
button2,
button3,
switch,
button0
);
input userclock; // 1 Hz clock goes in here
input switch, switch2;
input button2, button3, button0;
reg setState;
output [6:0] n2and3;
output [7:0] n0and1;
reg [7:0] n0and1;
... | 6.859638 |
module ClockChanger(clk_in, CE_out);
parameter CLOCK_PERIODS = 32'd10; // This will take original clock speed = C Hz, then produce output clock = C / CLOCK_PERIODS
// Instantiating this module
input clk_in;
reg [31:0] count = 0;
output wire CE_out = (count == CLOCK_PERIODS - 1);
always @(posedge clk_in) begin
//if (r... | 6.649359 |
module clockdemux4M (
saida,
inicio
);
output wire saida;
output wire inicio;
reg out;
reg out1;
assign saida = out;
assign inicio = out1;
initial begin
out = 0;
out1 = 1;
end
always begin
#125 out = ~out;
out1 = 0;
end
endmodule
| 6.909581 |
modules to be determined
// relative to each other. a clock divider with offset 1 occurs one
// (fast) clock later than a clock with offset 0.
module ClockDiv(CLK_IN, RST, PREEDGE, CLK_OUT);
parameter width = 2 ; // must be sufficient to hold upper
parameter lower = 1 ; //
parameter upper = 3 ;... | 7.692021 |
module ClockDiv16 (
inclk, // Input clock signal
outclk, // Output clock signal
reset_n
); // Active low reset signal
input inclk, reset_n;
output outclk;
// Count register
reg [15:0] cnt;
reg outclk;
// Use a 16 bit shift register to divide the clock by 16 counts.
always @(posedge inclk,... | 7.391288 |
module clockdivide2 (
input clk,
input rst,
input select,
output reg [31:0] OUT1,
output reg [31:0] OUT2,
output clkdivided1hz,
output clkdivided2hz,
output clkselect
);
always @(posedge clk or posedge rst) begin
if (rst) OUT1 <= 32'd0;
else if (OUT1 == 32'd50000000) OUT1 <= 3... | 7.39781 |
module ClockDivider #(
parameter REG_LEN = 8
) (
input wire clk,
input wire rst,
output wire out
);
reg [REG_LEN-1:0] clk_div;
always @(posedge clk) begin
if (rst) clk_div <= 0;
else clk_div <= clk_div + 1'b1;
end
assign out = clk_div[REG_LEN-1];
endmodule
| 7.886972 |
module ClockDivider2 (
output reg clk_out,
input clk_in
);
initial clk_out = 1'b0;
always @(posedge clk_in) begin
clk_out = ~clk_out; // Must use =, NOT <=
end
endmodule
| 6.821832 |
module ClockDivider2K (
input cin,
output cout
);
reg [14:0] counter = 15'd0;
parameter DIVISOR = 15'd25_000;
always @(posedge cin) begin
counter <= counter + 15'd1;
if (counter >= (DIVISOR - 1)) counter <= 15'd0;
end
assign cout = (counter < DIVISOR / 2) ? 1'b0 : 1'b1;
endmodule
| 6.821832 |
module ClockDivider500K (
input cin,
output cout
);
reg [18:0] counter = 18'd0;
parameter DIVISOR = 18'd100;
always @(posedge cin) begin
counter <= counter + 18'd1;
if (counter >= (DIVISOR - 1)) counter <= 18'd0;
end
assign cout = (counter < DIVISOR / 2) ? 1'b0 : 1'b1;
endmodule
| 6.596761 |
module ClockDivider5Hz (
input cin,
output cout
);
reg [25:0] counter = 26'd0;
parameter DIVISOR = 26'd10_000_000;
always @(posedge cin) begin
counter <= counter + 26'd1;
if (counter >= (DIVISOR - 1)) counter <= 26'd0;
end
assign cout = (counter < DIVISOR / 2) ? 1'b0 : 1'b1;
endmodule
| 6.596761 |
module ClockDividerInteger (
clock_o,
clock_i,
reset,
F_DIV
);
// Input and output
output clock_o; // Output clock
input clock_i; // Input clock
input reset; // Input reset
input F_DIV; // Input divider factor
parameter F_DIV_WIDTH = 32; // Input divider factor's bit number
// int... | 6.964374 |
module ClockDivider_10 (
clk,
rst,
oclk
);
input clk;
input rst;
output reg oclk;
reg [2:0] Q;
parameter n = 5;
//assign oclk=clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
oclk <= 0;
end else if (Q == n - 1) begin
Q <= 0;
oclk <= ~oclk;... | 6.683922 |
module ClockDivider_32 (
clk,
oclk,
rst
);
input clk;
input rst;
output reg oclk;
reg [3:0] Q;
parameter n = 16;
//assign oclk=clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
oclk <= 0;
end else if (Q == n - 1) begin
Q <= 0;
oclk <= ~oc... | 6.683922 |
module Clockdivider_4 (
clk,
oclk,
rst
);
input clk;
input rst;
output reg oclk;
reg [3:0] Q;
parameter n = 8;
//assign oclk=clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
oclk = 0;
end else if (Q == n - 1) begin
Q <= 0;
oclk = ~oclk;
... | 6.719041 |
module clockdivider_tb;
reg clk;
reg rst;
wire div2;
wire div4;
wire div8;
clockdivider dut (
.clk (clk),
.reset(rst),
.div2 (div2),
.div4 (div4),
.div8 (div8)
);
initial begin //Stimulus block
clk = 0;
rst = 0;
#50;
rst = 1;
#50;
rst = 0;
... | 6.641557 |
module ClockDivision25MHz (
input clk,
output reg clk_25MHz
);
// señal de reloj
initial begin
clk_25MHz = 0;
end
always @(posedge clk) clk_25MHz <= ~clk_25MHz;
endmodule
| 6.706653 |
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